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Merge pull request #4933 from haukepetersen/opt_sam3_clksetup

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cpu/sam3: cleaned up clock initialization
This commit is contained in:
Peter Kietzmann 2016-03-02 10:07:43 +01:00
commit 8e05e3152d
9 changed files with 89 additions and 522 deletions
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3
boards/arduino-due/board.c
View File

@ -29,9 +29,6 @@ void led_init(void);
void board_init(void)
{
/* initialize core clocks via CMSIS function provided by Atmel */
SystemInit();
/* initialize the CPU */
cpu_init();

15
boards/arduino-due/include/periph_conf.h
View File

@ -31,7 +31,20 @@ extern "C" {
* @name Clock configuration
* @{
*/
#define CLOCK_CORECLOCK (84000000U)
/* targeted system core clock */
#define CLOCK_CORECLOCK (84000000UL)
/* external oscillator clock */
#define CLOCK_EXT_OSC (12000000UL)
/* define PLL configuration
*
* The values must fulfill this equation:
* CORECLOCK = (EXT_OCS / PLL_DIV) * (PLL_MUL + 1)
*/
#define CLOCK_PLL_MUL (83)
#define CLOCK_PLL_DIV (12)
/* number of wait states before flash read and write operations */
#define CLOCK_FWS (4) /* 4 is save for 84MHz */
/** @} */
/**

215
boards/arduino-due/system_sam3xa.c
View File

@ -1,215 +0,0 @@
/*! \file *********************************************************************
*
* \brief Provides the low-level initialization functions that called
* on chip startup.
*
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following condition is met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
* microcontrollers.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
#include "sam3x8e.h"
/* @cond 0 */
/**INDENT-OFF**/
#ifdef __cplusplus
extern "C" {
#endif
/**INDENT-ON**/
/* @endcond */
/* Clock settings (84MHz) */
#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \
| CKGR_PLLAR_MULA(0xdUL) \
| CKGR_PLLAR_PLLACOUNT(0x3fUL) \
| CKGR_PLLAR_DIVA(0x1UL))
#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
/* Clock Definitions */
#define SYS_UTMIPLL (480000000UL) /* UTMI PLL frequency */
#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
/* FIXME: should be generated by sock */
uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
/**
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemFrequency variable.
*/
void SystemInit(void)
{
/* Set FWS according to SYS_BOARD_MCKR configuration */
EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
/* Initialize main oscillator */
if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
}
}
/* Switch to 3-20MHz Xtal oscillator */
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
}
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |
PMC_MCKR_CSS_MAIN_CLK;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
}
/* Initialize PLLA */
PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
}
/* Switch to main clock */
PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
}
/* Switch to PLLA */
PMC->PMC_MCKR = SYS_BOARD_MCKR;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
}
SystemCoreClock = CHIP_FREQ_CPU_MAX;
}
void SystemCoreClockUpdate(void)
{
/* Determine clock frequency according to clock register values */
switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
SystemCoreClock = CHIP_FREQ_XTAL_32K;
} else {
SystemCoreClock = CHIP_FREQ_SLCK_RC;
}
break;
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
SystemCoreClock = CHIP_FREQ_XTAL_12M;
} else {
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
case CKGR_MOR_MOSCRCF_4_MHz:
break;
case CKGR_MOR_MOSCRCF_8_MHz:
SystemCoreClock *= 2U;
break;
case CKGR_MOR_MOSCRCF_12_MHz:
SystemCoreClock *= 3U;
break;
default:
break;
}
}
break;
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
SystemCoreClock = CHIP_FREQ_XTAL_12M;
} else {
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
case CKGR_MOR_MOSCRCF_4_MHz:
break;
case CKGR_MOR_MOSCRCF_8_MHz:
SystemCoreClock *= 2U;
break;
case CKGR_MOR_MOSCRCF_12_MHz:
SystemCoreClock *= 3U;
break;
default:
break;
}
}
if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
CKGR_PLLAR_MULA_Pos) + 1U);
SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
CKGR_PLLAR_DIVA_Pos));
} else {
SystemCoreClock = SYS_UTMIPLL / 2U;
}
break;
}
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
SystemCoreClock /= 3U;
} else {
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >>
PMC_MCKR_PRES_Pos);
}
}
/**
* Initialize flash.
*/
void system_init_flash(uint32_t dw_clk)
{
/* Set FWS for embedded Flash access according to operating frequency */
if (dw_clk < CHIP_FREQ_FWS_0) {
EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
} else if (dw_clk < CHIP_FREQ_FWS_1) {
EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
} else if (dw_clk < CHIP_FREQ_FWS_2) {
EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
} else if (dw_clk < CHIP_FREQ_FWS_3) {
EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
} else {
EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
}
}
/* @cond 0 */
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/* @endcond */

4
boards/udoo/board.c
View File

@ -21,7 +21,6 @@
#include <stdio.h>
#include "board.h"
#include "system_sam3xa.h"
void led_init(void);
@ -29,9 +28,6 @@ void led_init(void);
void board_init(void)
{
/* initialize core clocks via STM-lib given function */
SystemInit();
/* initialize the CPU */
cpu_init();

15
boards/udoo/include/periph_conf.h
View File

@ -29,7 +29,20 @@ extern "C" {
* @name Clock configuration
* @{
*/
#define CLOCK_CORECLOCK (84000000U)
/* targeted system core clock */
#define CLOCK_CORECLOCK (84000000UL)
/* external oscillator clock */
#define CLOCK_EXT_OSC (12000000UL)
/* define PLL configuration
*
* The values must fulfill this equation:
* CORECLOCK = (EXT_OCS / PLL_DIV) * (PLL_MUL + 1)
*/
#define CLOCK_PLL_MUL (83)
#define CLOCK_PLL_DIV (12)
/* number of wait states before flash read and write operations */
#define CLOCK_FWS (4) /* 4 is save for 84MHz */
/** @} */
/**

213
boards/udoo/system_sam3xa.c
View File

@ -1,213 +0,0 @@
/*! \file *********************************************************************
*
* \brief Provides the low-level initialization functions that called
* on chip startup.
*
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following condition is met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
* microcontrollers.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
#include "sam3x8e.h"
/* @cond 0 */
/**INDENT-OFF**/
#ifdef __cplusplus
extern "C" {
#endif
/**INDENT-ON**/
/* @endcond */
/* Clock settings (84MHz) */
#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \
| CKGR_PLLAR_MULA(0xdUL) \
| CKGR_PLLAR_PLLACOUNT(0x3fUL) \
| CKGR_PLLAR_DIVA(0x1UL))
#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
/* Clock Definitions */
#define SYS_UTMIPLL (480000000UL) /* UTMI PLL frequency */
#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
/* FIXME: should be generated by sock */
uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
/**
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemFrequency variable.
*/
void SystemInit(void)
{
/* Set FWS according to SYS_BOARD_MCKR configuration */
EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
/* Initialize main oscillator */
if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
}
}
/* Switch to 3-20MHz Xtal oscillator */
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
}
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |
PMC_MCKR_CSS_MAIN_CLK;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
}
/* Initialize PLLA */
PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
}
/* Switch to main clock */
PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
}
/* Switch to PLLA */
PMC->PMC_MCKR = SYS_BOARD_MCKR;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
}
SystemCoreClock = CHIP_FREQ_CPU_MAX;
}
void SystemCoreClockUpdate(void)
{
/* Determine clock frequency according to clock register values */
switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
SystemCoreClock = CHIP_FREQ_XTAL_32K;
} else {
SystemCoreClock = CHIP_FREQ_SLCK_RC;
}
break;
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
SystemCoreClock = CHIP_FREQ_XTAL_12M;
} else {
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
case CKGR_MOR_MOSCRCF_4_MHz:
break;
case CKGR_MOR_MOSCRCF_8_MHz:
SystemCoreClock *= 2U;
break;
case CKGR_MOR_MOSCRCF_12_MHz:
SystemCoreClock *= 3U;
break;
default:
break;
}
}
break;
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
SystemCoreClock = CHIP_FREQ_XTAL_12M;
} else {
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
case CKGR_MOR_MOSCRCF_4_MHz:
break;
case CKGR_MOR_MOSCRCF_8_MHz:
SystemCoreClock *= 2U;
break;
case CKGR_MOR_MOSCRCF_12_MHz:
SystemCoreClock *= 3U;
break;
default:
break;
}
}
if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
CKGR_PLLAR_MULA_Pos) + 1U);
SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
CKGR_PLLAR_DIVA_Pos));
} else {
SystemCoreClock = SYS_UTMIPLL / 2U;
}
break;
}
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
SystemCoreClock /= 3U;
} else {
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >>
PMC_MCKR_PRES_Pos);
}
}
/**
* Initialize flash.
*/
void system_init_flash(uint32_t dw_clk)
{
/* Set FWS for embedded Flash access according to operating frequency */
if (dw_clk < CHIP_FREQ_FWS_0) {
EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
} else if (dw_clk < CHIP_FREQ_FWS_1) {
EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
} else if (dw_clk < CHIP_FREQ_FWS_2) {
EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
} else if (dw_clk < CHIP_FREQ_FWS_3) {
EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
} else {
EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
}
}
/* @cond 0 */
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/* @endcond */

62
cpu/sam3/cpu.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2014-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -18,6 +18,25 @@
*/
#include "cpu.h"
#include "periph_conf.h"
/**
* @brief Keys needed for editing certain PMC registers
* @{
*/
#define WPKEY (0x504D43)
#define MORKEY (0x37)
/** @} */
/**
* @brief Start-up time for external crystal (will be multiplied by 8)
*/
#define XTAL_STARTUP (8U)
/**
* @brief PLL is incremented to this value until considered stable
*/
#define PLL_CNT (64U)
/**
* @brief Initialize the CPU, set IRQ priorities
@ -28,4 +47,45 @@ void cpu_init(void)
WDT->WDT_MR |= WDT_MR_WDDIS;
/* initialize the Cortex-M core */
cortexm_init();
/* setup the flash wait states */
EFC0->EEFC_FMR = EEFC_FMR_FWS(CLOCK_FWS);
EFC1->EEFC_FMR = EEFC_FMR_FWS(CLOCK_FWS);
/* unlock write protect register for PMC module */
PMC->PMC_WPMR = PMC_WPMR_WPKEY(WPKEY);
/* activate the external crystal */
PMC->CKGR_MOR = (CKGR_MOR_KEY(MORKEY) |
CKGR_MOR_MOSCXTST(XTAL_STARTUP) |
CKGR_MOR_MOSCXTEN |
CKGR_MOR_MOSCRCEN);
/* wait for crystal to be stable */
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
/* select crystal to clock the main clock */
PMC->CKGR_MOR = (CKGR_MOR_KEY(MORKEY) |
CKGR_MOR_MOSCXTST(XTAL_STARTUP) |
CKGR_MOR_MOSCXTEN |
CKGR_MOR_MOSCRCEN |
CKGR_MOR_MOSCSEL);
/* wait for main oscillator selection to be complete */
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
/* setup PLLA */
PMC->CKGR_PLLAR = (CKGR_PLLAR_ONE |
CKGR_PLLAR_PLLACOUNT(PLL_CNT) |
CKGR_PLLAR_MULA(CLOCK_PLL_MUL) |
CKGR_PLLAR_DIVA(CLOCK_PLL_DIV));
/* wait for PLL to lock */
while (!(PMC->PMC_SR & PMC_SR_LOCKA));
/* before switching to PLLA, we need to switch to main clock */
PMC->PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
/* use PLLA as main clock source */
PMC->PMC_MCKR = PMC_MCKR_CSS_PLLA_CLK;
/* wait for master clock to be ready */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
}

3
cpu/sam3/include/sam3x8e.h
View File

@ -262,9 +262,6 @@ void WDT_Handler ( void );
#endif
#include <core_cm3.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_sam3xa.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/

81
cpu/sam3/include/system_sam3xa.h
View File

@ -1,81 +0,0 @@
/*! \file *********************************************************************
*
* \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
* for SAM3 devices.
*
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following condition is met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
* microcontrollers.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
#ifndef SYSTEM_SAM3X_H_INCLUDED
#define SYSTEM_SAM3X_H_INCLUDED
/* @cond @false */
/**INDENT-OFF**/
/**INDENT-ON**/
/* @endcond */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
/**
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void);
/**
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void);
/**
* Initialize flash.
*/
void system_init_flash(uint32_t dw_clk);
/* @cond @false */
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/* @endcond */
#endif /* SYSTEM_SAM3X_H_INCLUDED */