mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2025-12-24 14:03:55 +01:00
remove dev variable for cppcheck
Signed-off-by: dylad <dylan.laduranty@mesotic.com>
This commit is contained in:
dylad
parent
c81ae98068
commit
a3acd1d741
@ -86,15 +86,11 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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static int init_base(uart_t uart, uint32_t baudrate)
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{
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SercomUsart *dev;
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if ((unsigned int)uart >= UART_NUMOF) {
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return UART_NODEV;
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}
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/* get the devices base register */
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dev = _uart(uart);
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/* configure pins */
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gpio_init(uart_config[uart].rx_pin, GPIO_IN);
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gpio_init_mux(uart_config[uart].rx_pin, uart_config[uart].mux);
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@ -107,11 +103,11 @@ static int init_base(uart_t uart, uint32_t baudrate)
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/* enable sync and async clocks */
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uart_poweron(uart);
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/* reset the UART device */
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dev->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
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while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) {}
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_uart(uart)->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
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while (_uart(uart)->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) {}
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/* set asynchronous mode w/o parity, LSB first, TX and RX pad as specified
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* by the board in the periph_conf.h, x16 sampling and use internal clock */
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dev->CTRLA.reg = (SERCOM_USART_CTRLA_DORD |
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_uart(uart)->CTRLA.reg = (SERCOM_USART_CTRLA_DORD |
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SERCOM_USART_CTRLA_SAMPR(0x1) |
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SERCOM_USART_CTRLA_TXPO(uart_config[uart].tx_pad) |
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SERCOM_USART_CTRLA_RXPO(uart_config[uart].rx_pad) |
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@ -120,11 +116,11 @@ static int init_base(uart_t uart, uint32_t baudrate)
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SERCOM_USART_CTRLA_RUNSTDBY : 0));
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/* set baudrate */
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dev->BAUD.FRAC.FP = (baud % 10);
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dev->BAUD.FRAC.BAUD = (baud / 10);
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_uart(uart)->BAUD.FRAC.FP = (baud % 10);
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_uart(uart)->BAUD.FRAC.BAUD = (baud / 10);
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/* enable receiver and transmitter, use 1 stop bit */
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dev->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
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while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) {}
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_uart(uart)->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
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while (_uart(uart)->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) {}
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#elif CPU_FAM_SAML21
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/* Calculate the BAUD value */
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uint64_t temp1 = ((16 * ((uint64_t)baudrate)) << 32);
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@ -132,12 +128,12 @@ static int init_base(uart_t uart, uint32_t baudrate)
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uint64_t scale = ((uint64_t)1 << 32) - ratio;
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uint64_t baud_calculated = (65536 * scale) >> 32;
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dev->CTRLA.bit.ENABLE = 0; /* Disable to write, need to sync tho */
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while(dev->SYNCBUSY.bit.ENABLE) {}
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_uart(uart)->CTRLA.bit.ENABLE = 0; /* Disable to write, need to sync tho */
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while(_uart(uart)->SYNCBUSY.bit.ENABLE) {}
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/* set to LSB, asynchronous mode without parity, PAD0 Tx, PAD1 Rx,
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* 16x over-sampling, internal clk */
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dev->CTRLA.reg = SERCOM_USART_CTRLA_DORD \
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_uart(uart)->CTRLA.reg = SERCOM_USART_CTRLA_DORD \
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| SERCOM_USART_CTRLA_FORM(0x0) \
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| SERCOM_USART_CTRLA_SAMPA(0x0) \
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| SERCOM_USART_CTRLA_TXPO(uart_config[uart].tx_pad) \
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@ -148,11 +144,11 @@ static int init_base(uart_t uart, uint32_t baudrate)
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SERCOM_USART_CTRLA_RUNSTDBY : 0);
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/* Set baud rate */
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dev->BAUD.bit.BAUD = baud_calculated;
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_uart(uart)->BAUD.bit.BAUD = baud_calculated;
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/* enable receiver and transmitter, one stop bit*/
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dev->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
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while(dev->SYNCBUSY.bit.CTRLB) {}
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_uart(uart)->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
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while(_uart(uart)->SYNCBUSY.bit.CTRLB) {}
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uart_poweron(uart);
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#endif
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return UART_OK;
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@ -169,11 +165,6 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
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void uart_poweron(uart_t uart)
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{
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SercomUsart *dev;
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/* get the devices base register */
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dev = _uart(uart);
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#ifdef CPU_FAM_SAMD21
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PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << sercom_id(_uart(uart)));
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN |
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@ -183,72 +174,66 @@ void uart_poweron(uart_t uart)
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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#elif CPU_FAM_SAML21
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/* Enable the peripheral channel */
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GCLK->PCHCTRL[sercom_gclk_id[sercom_id(dev)]].reg |=
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GCLK->PCHCTRL[sercom_gclk_id[sercom_id(_uart(uart))]].reg |=
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GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(uart_config[uart].gclk_src);
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while (!(GCLK->PCHCTRL[sercom_gclk_id[sercom_id(dev)]].reg &
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while (!(GCLK->PCHCTRL[sercom_gclk_id[sercom_id(_uart(uart))]].reg &
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GCLK_PCHCTRL_CHEN)) {}
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if(sercom_gclk_id[sercom_id(dev)] < 5) {
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MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0 << sercom_id(dev);
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if(sercom_gclk_id[sercom_id(_uart(uart))] < 5) {
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MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0 << sercom_id(_uart(uart));
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}
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else {
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
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}
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while (dev->SYNCBUSY.reg) {}
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while (_uart(uart)->SYNCBUSY.reg) {}
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#endif
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/* finally, enable the device */
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dev->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
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_uart(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
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}
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void uart_poweroff(uart_t uart)
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{
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SercomUsart *dev;
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/* get the devices base register */
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dev = _uart(uart);
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#ifdef CPU_FAM_SAMD21
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PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << sercom_id(dev));
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GCLK->CLKCTRL.reg = ((SERCOM0_GCLK_ID_CORE + sercom_id(dev)) <<
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PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << sercom_id(_uart(uart)));
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GCLK->CLKCTRL.reg = ((SERCOM0_GCLK_ID_CORE + sercom_id(_uart(uart))) <<
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GCLK_CLKCTRL_ID_Pos);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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#elif CPU_FAM_SAML21
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/* Enable the peripheral channel */
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GCLK->PCHCTRL[sercom_gclk_id[sercom_id(dev)]].reg &= ~GCLK_PCHCTRL_CHEN;
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GCLK->PCHCTRL[sercom_gclk_id[sercom_id(_uart(uart))]].reg &= ~GCLK_PCHCTRL_CHEN;
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if(sercom_gclk_id[sercom_id(dev)] < 5) {
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MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << sercom_id(dev));
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if(sercom_gclk_id[sercom_id(_uart(uart))] < 5) {
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MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << sercom_id(_uart(uart)));
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}
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else {
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MCLK->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5;
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}
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while (dev->SYNCBUSY.reg) {}
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while (_uart(uart)->SYNCBUSY.reg) {}
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#endif
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}
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static inline void irq_handler(uint8_t uartnum)
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{
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SercomUsart *uart = _uart(uartnum);
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#ifdef CPU_FAM_SAMD21
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if (uart->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
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if (_uart(uartnum)->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
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/* interrupt flag is cleared by reading the data register */
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uart_ctx[uartnum].rx_cb(uart_ctx[uartnum].arg,
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(uint8_t)(uart->DATA.reg));
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(uint8_t)(_uart(uartnum)->DATA.reg));
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}
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else if (uart->INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) {
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else if (_uart(uartnum)->INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) {
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/* clear error flag */
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uart->INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
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_uart(uartnum)->INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
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}
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#elif CPU_FAM_SAML21
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if (uart->INTFLAG.bit.RXC) {
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if (_uart(uartnum)->INTFLAG.bit.RXC) {
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/* cleared by reading DATA regiser */
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uint8_t data = (uint8_t)uart->DATA.reg;
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uint8_t data = (uint8_t)_uart(uartnum)->DATA.reg;
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uart_ctx[uartnum].rx_cb(uart_ctx[uartnum].arg, data);
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}
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else if (uart->INTFLAG.bit.ERROR) {
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else if (_uart(uartnum)->INTFLAG.bit.ERROR) {
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/* clear error flag */
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uart->INTFLAG.reg |= SERCOM_USART_INTFLAG_ERROR;
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_uart(uartnum)->INTFLAG.reg |= SERCOM_USART_INTFLAG_ERROR;
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}
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#endif
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cortexm_isr_end();
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