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boards/nucleo-f3xx: adapt clock config

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This commit is contained in:
Vincent Dupont 2017-08-27 18:26:05 +02:00
parent 12a12108a7
commit a4b25ad4dc
14 changed files with 151 additions and 97 deletions
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6
boards/nucleo-f030/include/periph_conf.h
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@ -28,10 +28,10 @@ extern "C" {
#endif #endif
/** /**
* @name Clock settings * @name Clock settings
* *
* @note This is auto-generated from * @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c` * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz], /* give the target core clock (HCLK) frequency [in Hz],

6
boards/nucleo-f070/include/periph_conf.h
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@ -28,10 +28,10 @@ extern "C" {
#endif #endif
/** /**
* @name Clock settings * @name Clock settings
* *
* @note This is auto-generated from * @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c` * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz], /* give the target core clock (HCLK) frequency [in Hz],

6
boards/nucleo-f072/include/periph_conf.h
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@ -27,10 +27,10 @@ extern "C" {
#endif #endif
/** /**
* @name Clock settings * @name Clock settings
* *
* @note This is auto-generated from * @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c` * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz], /* give the target core clock (HCLK) frequency [in Hz],

6
boards/nucleo-f091/include/periph_conf.h
View File

@ -26,10 +26,10 @@ extern "C" {
#endif #endif
/** /**
* @name Clock settings * @name Clock settings
* *
* @note This is auto-generated from * @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c` * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz], /* give the target core clock (HCLK) frequency [in Hz],

6
boards/nucleo-f103/include/periph_conf.h
View File

@ -26,10 +26,10 @@ extern "C" {
#endif #endif
/** /**
* @name Clock settings * @name Clock settings
* *
* @note This is auto-generated from * @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c` * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz], /* give the target core clock (HCLK) frequency [in Hz],

33
boards/nucleo-f302/include/periph_conf.h
View File

@ -30,23 +30,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

33
boards/nucleo-f303/include/periph_conf.h
View File

@ -28,23 +28,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

35
boards/nucleo-f334/include/periph_conf.h
View File

@ -27,23 +27,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
**/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

33
boards/nucleo144-f303/include/periph_conf.h
View File

@ -26,23 +26,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

6
boards/nucleo32-f031/include/periph_conf.h
View File

@ -27,10 +27,10 @@ extern "C" {
#endif #endif
/** /**
* @name Clock settings * @name Clock settings
* *
* @note This is auto-generated from * @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c` * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz], /* give the target core clock (HCLK) frequency [in Hz],

6
boards/nucleo32-f042/include/periph_conf.h
View File

@ -26,10 +26,10 @@ extern "C" {
#endif #endif
/** /**
* @name Clock settings * @name Clock settings
* *
* @note This is auto-generated from * @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c` * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz], /* give the target core clock (HCLK) frequency [in Hz],

33
boards/nucleo32-f303/include/periph_conf.h
View File

@ -26,23 +26,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSI (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (64000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (64000000U)
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI) /* 0: no external high speed crystal available
/* the actual PLL values are automatically generated */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (16)
/** @} */ /** @} */
/** /**

6
boards/stm32f0discovery/include/periph_conf.h
View File

@ -26,10 +26,10 @@ extern "C" {
#endif #endif
/** /**
* @name Clock settings * @name Clock settings
* *
* @note This is auto-generated from * @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c` * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz], /* give the target core clock (HCLK) frequency [in Hz],

33
boards/stm32f3discovery/include/periph_conf.h
View File

@ -26,23 +26,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**