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at86rf231: disable SFD IRQ by default

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This commit is contained in:
Oleg Hahm 2015-05-05 22:50:14 +02:00
parent c8aff36237
commit a97ee2b0a4
3 changed files with 52 additions and 10 deletions
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3
drivers/ng_at86rf2xx/ng_at86rf2xx.c
View File

@ -154,8 +154,7 @@ void ng_at86rf2xx_reset(ng_at86rf2xx_t *dev)
ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__TRX_CTRL_2, tmp);
/* enable interrupts */
ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__IRQ_MASK,
(NG_AT86RF2XX_IRQ_STATUS_MASK__RX_START |
NG_AT86RF2XX_IRQ_STATUS_MASK__TRX_END));
NG_AT86RF2XX_IRQ_STATUS_MASK__TRX_END);
/* go into RX state */
ng_at86rf2xx_set_state(dev, NG_AT86RF2XX_STATE_RX_AACK_ON);

12
drivers/ng_at86rf2xx/ng_at86rf2xx_getset.c
View File

@ -154,6 +154,12 @@ void ng_at86rf2xx_set_option(ng_at86rf2xx_t *dev, uint16_t option, bool state)
tmp &= ~(NG_AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK);
ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__CSMA_SEED_1, tmp);
break;
case NG_AT86RF2XX_OPT_TELL_RX_START:
DEBUG("[ng_at86rf2xx] opt: enabling SFD IRQ\n");
tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__IRQ_MASK);
tmp |= NG_AT86RF2XX_IRQ_STATUS_MASK__RX_START;
ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__IRQ_MASK, tmp);
break;
default:
/* do nothing */
break;
@ -185,6 +191,12 @@ void ng_at86rf2xx_set_option(ng_at86rf2xx_t *dev, uint16_t option, bool state)
tmp |= NG_AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK;
ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__CSMA_SEED_1, tmp);
break;
case NG_AT86RF2XX_OPT_TELL_RX_START:
DEBUG("[ng_at86rf2xx] opt: disabling SFD IRQ\n");
tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__IRQ_MASK);
tmp &= ~NG_AT86RF2XX_IRQ_STATUS_MASK__RX_START;
ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__IRQ_MASK, tmp);
break;
default:
/* do nothing */
break;

47
drivers/ng_at86rf2xx/ng_at86rf2xx_netdev.c
View File

@ -357,7 +357,6 @@ static int _get(ng_netdev_t *device, ng_netconf_opt_t opt,
ng_at86rf2xx_t *dev = (ng_at86rf2xx_t *) device;
switch (opt) {
uint8_t irq_mask;
case NETCONF_OPT_ADDRESS:
if (max_len < sizeof(uint16_t)) {
@ -488,10 +487,24 @@ static int _get(ng_netdev_t *device, ng_netconf_opt_t opt,
}
return sizeof(ng_netconf_enable_t);
case NETCONT_OPT_SFD_INT:
irq_mask = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__IRQ_MASK);
ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__IRQ_MASK,
(irq_mask ^ NG_AT86RF2XX_IRQ_STATUS_MASK__RX_START));
case NETCONF_OPT_RX_START_IRQ:
*((ng_netconf_enable_t *)val) =
!!(dev->options & NG_AT86RF2XX_OPT_TELL_RX_START);
return sizeof(ng_netconf_enable_t);
case NETCONF_OPT_RX_END_IRQ:
*((ng_netconf_enable_t *)val) =
!!(dev->options & NG_AT86RF2XX_OPT_TELL_RX_END);
return sizeof(ng_netconf_enable_t);
case NETCONF_OPT_TX_START_IRQ:
*((ng_netconf_enable_t *)val) =
!!(dev->options & NG_AT86RF2XX_OPT_TELL_TX_START);
return sizeof(ng_netconf_enable_t);
case NETCONF_OPT_TX_END_IRQ:
*((ng_netconf_enable_t *)val) =
!!(dev->options & NG_AT86RF2XX_OPT_TELL_TX_END);
return sizeof(ng_netconf_enable_t);
default:
@ -606,6 +619,26 @@ static int _set(ng_netdev_t *device, ng_netconf_opt_t opt,
((bool *)val)[0]);
return sizeof(ng_netconf_enable_t);
case NETCONF_OPT_RX_START_IRQ:
ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_RX_START,
((bool *)val)[0]);
return sizeof(ng_netconf_enable_t);
case NETCONF_OPT_RX_END_IRQ:
ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_RX_END,
((bool *)val)[0]);
return sizeof(ng_netconf_enable_t);
case NETCONF_OPT_TX_START_IRQ:
ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_TX_START,
((bool *)val)[0]);
return sizeof(ng_netconf_enable_t);
case NETCONF_OPT_TX_END_IRQ:
ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_TX_END,
((bool *)val)[0]);
return sizeof(ng_netconf_enable_t);
default:
return -ENOTSUP;
}
@ -650,9 +683,7 @@ static void _isr_event(ng_netdev_t *device, uint32_t event_type)
state = ng_at86rf2xx_get_state(dev);
if (irq_mask & NG_AT86RF2XX_IRQ_STATUS_MASK__RX_START) {
if (dev->event_cb && (dev->options & NG_AT86RF2XX_OPT_TELL_RX_START)) {
dev->event_cb(NETDEV_EVENT_RX_STARTED, NULL);
}
dev->event_cb(NETDEV_EVENT_RX_STARTED, NULL);
DEBUG("[ng_at86rf2xx] EVT - RX_START\n");
}
if (irq_mask & NG_AT86RF2XX_IRQ_STATUS_MASK__TRX_END) {