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Merge pull request #7041 from OTAkeys/pr/stm32f413vg

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cpu/stm32f4: add stm32f413vg support
This commit is contained in:
Martine Lenders 2017-06-29 14:48:14 +02:00 committed by GitHub
commit abe2d44861
4 changed files with 78 additions and 7 deletions
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6
cpu/stm32f4/include/cpu_conf.h
View File

@ -33,7 +33,7 @@
#include "vendor/stm32f411xe.h"
#elif defined(CPU_MODEL_STM32F412ZG)
#include "vendor/stm32f412zx.h"
#elif defined(CPU_MODEL_STM32F413ZH)
#elif defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F413VG)
#include "vendor/stm32f413xx.h"
#elif defined(CPU_MODEL_STM32F415RG)
#include "vendor/stm32f415xx.h"
@ -52,7 +52,11 @@ extern "C" {
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U)
#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F413VG)
#define CPU_IRQ_NUMOF (102U)
#else
#define CPU_IRQ_NUMOF (82U)
#endif
#define CPU_FLASH_BASE FLASH_BASE
/** @} */

30
cpu/stm32f4/ldscripts/stm32f413vg.ld Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (C) 2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32f4
* @{
*
* @file
* @brief Memory definitions for the STM32F413VG
*
* @author Vincent Dupont <vincent@otakeys.com>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1M
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f413zh.ld
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@ -21,8 +21,7 @@
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1536K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}

46
cpu/stm32f4/vectors.c
View File

@ -105,13 +105,28 @@ WEAK_DEFAULT void isr_dma2_stream7(void);
WEAK_DEFAULT void isr_usart6(void);
WEAK_DEFAULT void isr_i2c3_ev(void);
WEAK_DEFAULT void isr_i2c3_er(void);
#if defined(CPU_MODEL_STM32F413ZH)
/* STM32F413 specific interrupt vectors (CAN3)
#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F413VG)
/* STM32F413 specific interrupt vectors
* See RM0430, part 10.2 */
WEAK_DEFAULT void isr_can3_tx(void);
WEAK_DEFAULT void isr_can3_rx0(void);
WEAK_DEFAULT void isr_can3_rx1(void);
WEAK_DEFAULT void isr_can3_sce(void);
WEAK_DEFAULT void isr_usart7(void);
WEAK_DEFAULT void isr_usart8(void);
WEAK_DEFAULT void isr_spi4(void);
WEAK_DEFAULT void isr_spi5(void);
WEAK_DEFAULT void isr_sai1(void);
WEAK_DEFAULT void isr_uart9(void);
WEAK_DEFAULT void isr_uart10(void);
WEAK_DEFAULT void isr_quadspi(void);
WEAK_DEFAULT void isr_fmpi2c1_ev(void);
WEAK_DEFAULT void isr_fmpi2c1_er(void);
WEAK_DEFAULT void isr_lptim1(void);
WEAK_DEFAULT void isr_dfsdm2_flt0(void);
WEAK_DEFAULT void isr_dfsdm2_flt1(void);
WEAK_DEFAULT void isr_dfsdm2_flt2(void);
WEAK_DEFAULT void isr_dfsdm2_flt3(void);
#else
WEAK_DEFAULT void isr_otg_hs_ep1_out(void);
WEAK_DEFAULT void isr_otg_hs_ep1_in(void);
@ -220,20 +235,43 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void*) isr_usart6, /* USART6 */
(void*) isr_i2c3_ev, /* I2C3 event */
(void*) isr_i2c3_er, /* I2C3 error */
#if defined(CPU_MODEL_STM32F413ZH)
#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F413VG)
(void*) isr_can3_tx, /* CAN3 TX */
(void*) isr_can3_rx0, /* CAN3 RX0 */
(void*) isr_can3_rx1, /* CAN3 RX1 */
(void*) isr_can3_sce, /* CAN3 SCE */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#else
(void*) isr_otg_hs_ep1_out, /* USB OTG HS End Point 1 Out */
(void*) isr_otg_hs_ep1_in, /* USB OTG HS End Point 1 In */
(void*) isr_otg_hs_wkup, /* USB OTG HS Wakeup through EXTI */
(void*) isr_otg_hs, /* USB OTG HS */
(void*) isr_dcmi, /* DCMI */
#endif
(void*) isr_cryp, /* CRYP crypto */
#endif
(void*) isr_hash_rng, /* Hash and Rng */
(void*) isr_fpu, /* FPU */
#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F413VG)
(void*) isr_usart7, /* USART7 */
(void*) isr_usart8, /* USART8 */
(void*) isr_spi4, /* SPI4 */
(void*) isr_spi5, /* SPI5 */
(void*) (0UL), /* Reserved */
(void*) isr_sai1, /* SAI1 */
(void*) isr_uart9, /* UART9 */
(void*) isr_uart10, /* UART10 */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) isr_quadspi, /* QuadSPI */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) isr_fmpi2c1_ev, /* FMPI2C1 Event */
(void*) isr_fmpi2c1_er, /* FMPI2C1 Error */
(void*) isr_lptim1, /* LP TIM1 */
(void*) isr_dfsdm2_flt0, /* DFSDM2 Filter 0 */
(void*) isr_dfsdm2_flt1, /* DFSDM2 Filter 1 */
(void*) isr_dfsdm2_flt2, /* DFSDM2 Filter 2 */
(void*) isr_dfsdm2_flt3, /* DFSDM2 Filter 3 */
#endif
};