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https://github.com/RIOT-OS/RIOT.git
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cpu/esp32/irq_arch: migration to ESP-IDF v5.4
This commit is contained in:
Gunar Schorcht
parent
ea8462e633
commit
ac4281035a
@ -35,24 +35,33 @@ extern "C" {
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*
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* @{
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*/
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#define CPU_INUM_RMT 1 /**< Level interrupt with low priority 1 */
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/* On Xtensa-based ESP32x SoCs, interrupt 0 is reserved for the WiFi interface
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* and interrupt 1 is available. However, since interrupt 0 is not available on
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* RISC-V-based ESP32x SoCs, interrupt 1 is used for the WiFi interface instead.
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* Therefore, we use interrupt 1 for the RMT peripheral on Xtensa-based ESP32x
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* SoCs, but we use interrupt 11 for the RMT peripheral on RISC-V-based ESP32x
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* SoCs. Interrupt 11 is reserved for profiling on Xtensa-based ESP32x SoCs. */
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#if defined(__XTENSA__)
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# define CPU_INUM_RMT 1 /**< Level interrupt with low priority 1 */
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#else
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# define CPU_INUM_RMT 11 /**< Level interrupt with low priority 1 */
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#endif
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#define CPU_INUM_GPIO 2 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_CAN 3 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_UART 4 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_USB 8 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_BLE 5 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_RTT 9 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_SERIAL_JTAG 10 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_SERIAL_JTAG 10 /**< Edge interrupt with low priority 1 */
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#define CPU_INUM_I2C 12 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_WDT 13 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_SOFTWARE 17 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_UART 13 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_CAN 17 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_ETH 18 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_LCD 18 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_TIMER 19 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_USB 18 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_FRC2 20 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_SYSTIMER 20 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_BLE 21 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_SDMMC 23 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_CACHEERR 25 /**< Level interrupt with high priority 4 */
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#define CPU_INUM_SDMMC 21 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_TIMER 22 /**< Edge interrupt with medium priority 2 */
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#define CPU_INUM_WDT 23 /**< Level interrupt with medium priority 3 */
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#define CPU_INUM_SOFTWARE 29 /**< Software interrupt with medium priority 3 */
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/** @} */
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/**
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@ -19,14 +19,17 @@
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*/
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#include "irq_arch.h"
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#include "log.h"
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#include "esp_attr.h"
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#include "esp_bit_defs.h"
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#include "esp_cpu.h"
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#include "esp_err.h"
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#include "freertos/FreeRTOS.h"
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#include "hal/interrupt_controller_types.h"
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#include "hal/interrupt_controller_ll.h"
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#include "rom/ets_sys.h"
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#include "soc/interrupts.h"
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#include "soc/periph_defs.h"
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#include "soc/soc.h"
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#include "esp_intr_alloc.h"
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#define ENABLE_DEBUG 0
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@ -44,83 +47,84 @@ typedef struct intr_handle_data_t {
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/* TODO change to a clearer approach */
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static const struct intr_handle_data_t _irq_data_table[] = {
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#ifndef __XTENSA__
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{ ETS_FROM_CPU_INTR0_SOURCE, CPU_INUM_SOFTWARE, 1 },
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#endif
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{ ETS_TG0_WDT_LEVEL_INTR_SOURCE, CPU_INUM_WDT, 1 },
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{ ETS_TG0_T0_LEVEL_INTR_SOURCE, CPU_INUM_RTT, 1 },
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#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
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#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
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{ ETS_TG0_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
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#endif
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#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2)
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{ ETS_TG0_LACT_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
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#endif
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#if !defined(CPU_FAM_ESP32C2)
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#if SOC_TIMER_GROUPS > 1
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{ ETS_TG1_T0_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
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#endif
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#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
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# if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
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{ ETS_TG1_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
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# endif /* SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1 */
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#endif /* SOC_TIMER_GROUPS > 1 */
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#if defined(CPU_FAM_ESP32)
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{ ETS_TG0_LACT_LEVEL_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
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#elif defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3) || defined(CPU_FAM_ESP32C3)
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{ ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
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#else
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# error "Platform implementation is missing"
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#endif
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{ ETS_UART0_INTR_SOURCE, CPU_INUM_UART, 1 },
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{ ETS_UART1_INTR_SOURCE, CPU_INUM_UART, 1 },
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#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
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#if SOC_UART_NUM > 2
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{ ETS_UART2_INTR_SOURCE, CPU_INUM_UART, 1 },
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#endif
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{ ETS_GPIO_INTR_SOURCE, CPU_INUM_GPIO, 1 },
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{ ETS_I2C_EXT0_INTR_SOURCE, CPU_INUM_I2C, 1 },
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#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
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#if SOC_I2C_NUM > 1
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{ ETS_I2C_EXT1_INTR_SOURCE, CPU_INUM_I2C, 1 },
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#endif
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#if defined(CPU_FAM_ESP32)
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#if defined(SOC_BLE_SUPPORTED)
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# if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S3) || defined(CPU_FAM_ESP32C3)
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{ ETS_RWBLE_INTR_SOURCE, CPU_INUM_BLE, 2 },
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# else
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# error "Platform implementation is missing"
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# endif
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#endif /* SOC_BLE_SUPPORTED */
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#if defined(SOC_EMAC_SUPPORTED)
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{ ETS_ETH_MAC_INTR_SOURCE, CPU_INUM_ETH, 1 },
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#endif
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#if !defined(CPU_FAM_ESP32C2)
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#if defined(SOC_RMT_SUPPORTED)
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{ ETS_RMT_INTR_SOURCE, CPU_INUM_RMT, 1 },
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#endif
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#if defined(SOC_SDMMC_HOST_SUPPORTED)
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{ ETS_SDIO_HOST_INTR_SOURCE, CPU_INUM_SDMMC, 2 },
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#endif
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#if defined(SOC_TWAI_SUPPORTED)
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{ ETS_TWAI_INTR_SOURCE, CPU_INUM_CAN, 1 },
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{ ETS_TIMER2_INTR_SOURCE, CPU_INUM_FRC2, 2 },
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#endif
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#if !defined(CPU_FAM_ESP32)
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{ ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
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#endif
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{ ETS_INTERNAL_SW1_INTR_SOURCE, CPU_INUM_BLE, 2 },
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#if defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
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#if defined(SOC_USB_OTG_SUPPORTED)
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{ ETS_USB_INTR_SOURCE, CPU_INUM_USB, 1 },
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#endif
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#if defined(ETS_USB_SERIAL_JTAG_INTR_SOURCE)
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#if defined(SOC_USB_SERIAL_JTAG_SUPPORTED)
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{ ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG, 1 },
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#endif
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{ ETS_RMT_INTR_SOURCE, CPU_INUM_RMT, 1 },
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#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2)
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{ ETS_I2S0_INTR_SOURCE, CPU_INUM_LCD, 1 },
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#elif defined(CPU_FAM_ESP32S3)
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{ ETS_LCD_CAM_INTR_SOURCE, CPU_INUM_LCD, 1 },
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#endif
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#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
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{ ETS_SDIO_HOST_INTR_SOURCE, CPU_INUM_SDMMC, 2 },
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#endif
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};
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#define IRQ_DATA_TABLE_SIZE ARRAY_SIZE(_irq_data_table)
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#if defined(CPU_FAM_ESP32) && MODULE_ESP_LCD && MODULE_ESP_ETH
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#error "esp_eth and esp_lcd can't be used at the same time because of an interrupt conflict"
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#endif
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void esp_irq_init(void)
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{
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#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
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/* to avoid to do it in every component, we initialize levels here once */
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for (unsigned i = 0; i < IRQ_DATA_TABLE_SIZE; i++) {
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intr_cntrl_ll_set_int_level(_irq_data_table[i].intr, _irq_data_table[i].level);
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esp_cpu_intr_set_priority(_irq_data_table[i].intr, _irq_data_table[i].level);
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}
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#endif
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}
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void esp_intr_enable_source(int inum)
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{
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intr_cntrl_ll_enable_interrupts(BIT(inum));
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esp_cpu_intr_enable(BIT(inum));
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}
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void esp_intr_disable_source(int inum)
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{
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intr_cntrl_ll_disable_interrupts(BIT(inum));
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esp_cpu_intr_disable(BIT(inum));
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}
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esp_err_t esp_intr_enable(intr_handle_t handle)
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@ -150,6 +154,8 @@ esp_err_t esp_intr_disable(intr_handle_t handle)
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esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler,
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void *arg, intr_handle_t *ret_handle)
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{
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DEBUG("%s source=%d flags=0x%04"PRIx16" handler=%p arg=%p\n",
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__func__, source, (uint16_t)flags, handler, arg);
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unsigned i;
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for (i = 0; i < IRQ_DATA_TABLE_SIZE; i++) {
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if (_irq_data_table[i].src == source) {
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@ -158,6 +164,8 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler,
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}
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if (i == IRQ_DATA_TABLE_SIZE) {
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LOG_ERROR("%s source=%d not found in interrupt allocation table\n",
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__func__, source);
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return ESP_ERR_NOT_FOUND;
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}
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@ -165,16 +173,16 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler,
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intr_matrix_set(PRO_CPU_NUM, _irq_data_table[i].src, _irq_data_table[i].intr);
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/* set the interrupt handler */
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intr_cntrl_ll_set_int_handler(_irq_data_table[i].intr, handler, arg);
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esp_cpu_intr_set_handler(_irq_data_table[i].intr, handler, arg);
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#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
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/* set interrupt level given by flags */
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intr_cntrl_ll_set_int_level(_irq_data_table[i].intr, esp_intr_flags_to_level(flags));
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esp_cpu_intr_set_priority(_irq_data_table[i].intr, esp_intr_flags_to_level(flags));
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#endif
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/* enable the interrupt if ESP_INTR_FLAG_INTRDISABLED is not set */
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if ((flags & ESP_INTR_FLAG_INTRDISABLED) == 0) {
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intr_cntrl_ll_enable_interrupts(BIT(_irq_data_table[i].intr));
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esp_cpu_intr_enable(BIT(_irq_data_table[i].intr));
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}
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if (ret_handle) {
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@ -204,3 +212,24 @@ int esp_intr_get_cpu(intr_handle_t handle)
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{
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return PRO_CPU_NUM;
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}
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static volatile uint32_t esp_intr_noniram_state;
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static uint32_t esp_intr_noniram_call_counter = 0;
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void IRAM_ATTR esp_intr_noniram_disable(void)
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{
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if (esp_intr_noniram_call_counter == 0) {
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esp_intr_noniram_state = irq_disable();
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}
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esp_intr_noniram_call_counter++;
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}
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void IRAM_ATTR esp_intr_noniram_enable(void)
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{
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if (esp_intr_noniram_call_counter) {
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esp_intr_noniram_call_counter--;
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if (esp_intr_noniram_call_counter == 0) {
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irq_restore(esp_intr_noniram_state);
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}
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};
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}
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@ -304,8 +304,11 @@ static NORETURN void IRAM system_init (void)
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extern void board_init(void);
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board_init();
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/* route a software interrupt source to CPU as trigger for thread yields */
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#ifndef __XTENSA__
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/* route a software interrupt source to CPU as trigger for thread yields,
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* we use an internal software interrupt on Xtensa-based ESP32x SoCs */
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intr_matrix_set(PRO_CPU_NUM, ETS_FROM_CPU_INTR0_SOURCE, CPU_INUM_SOFTWARE);
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#endif
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/* set thread yield handler and enable the software interrupt */
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intr_cntrl_ll_set_int_handler(CPU_INUM_SOFTWARE, thread_yield_isr, NULL);
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intr_cntrl_ll_enable_interrupts(BIT(CPU_INUM_SOFTWARE));
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@ -21,8 +21,7 @@
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#include "irq_arch.h"
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#include "esp_attr.h"
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#include "hal/interrupt_controller_types.h"
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#include "hal/interrupt_controller_ll.h"
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#include "esp_cpu.h"
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#include "soc/periph_defs.h"
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#define ENABLE_DEBUG 0
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@ -286,6 +286,9 @@ void IRAM_ATTR thread_yield_higher(void)
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ets_soft_int_type = ETS_SOFT_INT_YIELD;
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WSR(BIT(ETS_SOFT_INUM), interrupt);
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critical_exit();
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#elif defined(__XTENSA__)
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/* generate the software interrupt to switch the context */
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WSR(BIT(CPU_INUM_SOFTWARE), interrupt);
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#elif defined(DPORT_CPU_INTR_FROM_CPU_0_REG)
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/* generate the software interrupt to switch the context */
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
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