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board/samr21-xpro: made cpu clock configurable

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This commit is contained in:
Hauke Petersen 2015-05-19 18:12:23 +02:00
parent fecc105063
commit acb06d8fe8
2 changed files with 64 additions and 32 deletions
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3
boards/samr21-xpro/include/board.h
View File

@ -23,6 +23,7 @@
#define __BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C" {
@ -31,7 +32,7 @@ extern "C" {
/**
* Define the nominal CPU core clock in this board
*/
#define F_CPU (8000000UL)
#define F_CPU (CLOCK_CORECLOCK)
/**
* Assign the hardware timer

93
boards/samr21-xpro/include/periph_conf.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -11,9 +11,11 @@
* @{
*
* @file
* @brief Peripheral MCU configuration for the Atmel SAM R21 Xplained Pro board
* @brief Configuration of CPU peripherals for the Atmel SAM R21 Xplained
* Pro board
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>s
*/
#ifndef __PERIPH_CONF_H
@ -23,26 +25,72 @@
extern "C" {
#endif
/**
* @brief External oscillator and clock configuration
*
* For selection of the used CORECLOCK, we have implemented two choices:
*
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
* - usage of the internal 8MHz oscillator directly, divided by N if needed
*
*
* The PLL option allows for the usage of a wider frequency range and a more
* stable clock with less jitter. This is why we use this option as default.
*
* The target frequency is computed from the PLL multiplier and the PLL divisor.
* Use the following formula to compute your values:
*
* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
*
* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
*
*
* The internal Oscillator used directly can lead to a slightly better power
* efficiency to the cost of a less stable clock. Use this option when you know
* what you are doing! The actual core frequency is adjusted as follows:
*
* CORECLOCK = 8MHz / DIV
*
* NOTE: A core clock frequency below 1MHz is not recommended
*
* @{
*/
#define CLOCK_USE_PLL (1)
#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#else
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#endif
/** @} */
/**
* @name Timer peripheral configuration
* @{
*/
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1
/* Timer 0 configuration */
#define TIMER_0_DEV TC3->COUNT16
#define TIMER_0_CHANNELS 2
#define TIMER_0_MAX_VALUE (0xffff)
#define TIMER_0_ISR isr_tc3
#define TIMER_0_DEV TC3->COUNT16
#define TIMER_0_CHANNELS 2
#define TIMER_0_MAX_VALUE (0xffff)
#define TIMER_0_ISR isr_tc3
/* Timer 1 configuration */
#define TIMER_1_DEV TC4->COUNT32
#define TIMER_1_CHANNELS 2
#define TIMER_1_MAX_VALUE (0xffffffff)
#define TIMER_1_ISR isr_tc4
#define TIMER_1_DEV TC4->COUNT32
#define TIMER_1_CHANNELS 2
#define TIMER_1_MAX_VALUE (0xffffffff)
#define TIMER_1_ISR isr_tc4
/** @} */
/**
@ -51,9 +99,6 @@ extern "C" {
*/
#define UART_NUMOF (1U)
#define UART_0_EN 1
#define UART_1_EN 0
#define UART_2_EN 0
#define UART_3_EN 0
#define UART_IRQ_PRIO 1
/* UART 0 device configuration */
@ -65,16 +110,6 @@ extern "C" {
#define UART_0_TX_PIN (4)
#define UART_0_RX_PIN (5)
#define UART_0_PINS (PORT_PA04 | PORT_PA05)
#define UART_0_REF_F (8000000UL)
/* UART 1 device configuration */
#define UART_1_DEV
#define UART_1_IRQ
#define UART_1_ISR
/* UART 1 pin configuration */
#define UART_1_PORT
#define UART_1_PINS
/** @} */
@ -91,7 +126,6 @@ extern "C" {
#define SPI_IRQ_0 SERCOM4_IRQn
#define SPI_0_DOPO (1)
#define SPI_0_DIPO (0)
#define SPI_0_F_REF (8000000UL)
#define SPI_0_SCLK_DEV PORT->Group[2]
#define SPI_0_SCLK_PIN (18)
@ -107,7 +141,6 @@ extern "C" {
#define SPI_IRQ_1 SERCOM5_IRQn
#define SPI_1_DOPO (1)
#define SPI_1_DIPO (2)
#define SPI_1_F_REF (8000000UL)
#define SPI_1_SCLK_DEV PORT->Group[1]
#define SPI_1_SCLK_PIN (23)
@ -138,8 +171,6 @@ extern "C" {
#define I2C_SDA PIN_PA16
#define I2C_SCL PIN_PA17
#define I2C_0_PINS (PORT_PA16 | PORT_PA17)
/* Default Clock Source on reset OSC8M - 8MHz */
#define I2C_0_REF_F (8000000UL)
/**
* @name Random Number Generator configuration