kaspar/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2025-12-24 22:13:52 +01:00
Code Releases Activity

k60: Use BITBAND_REG32

Browse Source 
- Use BITBAND_REG32 instead of BITBAND_REG for improved code readability.
 - Remove BITBAND_PERIPH* from cpu-conf.h
 - Remove BITBAND_REG from MK60D10.h, MK60DZ10.h
This commit is contained in:
Joakim Gebart 2015-05-16 09:53:06 +02:00
parent 7b4450bd0a
commit af3263b0a2
3 changed files with 8 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
cpu/k60/include/MK60D10.h
View File

@ -68,14 +68,16 @@
** Update of startup files - possibility to override DefaultISR added.
** - rev. 1.8 (2014-10-14)
** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0
** - rev. 1.8-jg (2015-05-18)
** Removed BITBAND_REG macro.
**
** ###################################################################
*/
/*!
* @file MK60D10.h
* @version 1.8
* @date 2014-10-14
* @version 1.8-jg
* @date 2015-05-18
* @brief CMSIS Peripheral Access Layer for MK60D10
*
* CMSIS Peripheral Access Layer for MK60D10
@ -127,7 +129,6 @@ extern "C"
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can

2
cpu/k60/include/MK60DZ10.h
View File

@ -46,6 +46,7 @@
** Gap between end of interrupt vector table and flash configuration field filled by default ISR.
** - rev. 1.2-jg (2015-05-18)
** Added BITBAND_REG32, BITBAND_REG16, BITBAND_REG8, BITBAND_REGADDR macros from MK60D10.h.
** Removed BITBAND_REG macro.
**
** ###################################################################
*/
@ -88,7 +89,6 @@ extern "C"
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can

21
cpu/k60/include/cpu-conf.h
View File

@ -121,8 +121,8 @@ extern "C"
* @{
*/
#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
#define LPTIMER_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1) /**< Enable LPTMR0 clock gate */
#define LPTIMER_CLKDIS() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0) /**< Disable LPTMR0 clock gate */
#define LPTIMER_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1) /**< Enable LPTMR0 clock gate */
#define LPTIMER_CLKDIS() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0) /**< Disable LPTMR0 clock gate */
#define LPTIMER_CLKSRC_MCGIRCLK 0 /**< internal reference clock (4MHz) */
#define LPTIMER_CLKSRC_LPO 1 /**< PMC 1kHz output */
#define LPTIMER_CLKSRC_ERCLK32K 2 /**< RTC clock 32768Hz */
@ -213,7 +213,7 @@ extern "C"
/**
* @brief Enable clock gate on LLWU module.
*/
#define LLWU_UNLOCK() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
#define LLWU_UNLOCK() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
/**
* @brief Internal modules whose interrupts are mapped to LLWU wake up sources.
@ -309,21 +309,6 @@ typedef enum llwu_wakeup_pin {
*/
#define BITBAND_VAR8(var, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit))))
/**
* @brief Bitband 32 bit access to peripheral register
*/
#define BITBAND_PERIPH32(reg, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(reg), (bit))))
/**
* @brief Bitband 16 bit access to peripheral register
*/
#define BITBAND_PERIPH16(reg, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(reg), (bit))))
/**
* @brief Bitband 8 bit access to peripheral register
*/
#define BITBAND_PERIPH8(reg, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(reg), (bit))))
/** @} */
#ifdef __cplusplus
}