mirror of
https://github.com/RIOT-OS/RIOT.git
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Merge pull request #21837 from crasbe/pr/nucleo-wl55jc-rtc-support_new
boards/nucleo-wl55jc, cpu/stm32: enable RTC support, increase RTC accuracy
This commit is contained in:
crasbe
GitHub
commit
b1256ffb1b
@ -5,6 +5,7 @@ CPU_MODEL = stm32wle5jc
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_lpuart
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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@ -5,6 +5,7 @@ CPU_MODEL = stm32wl55jc
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_lpuart
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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@ -35,7 +35,8 @@ ifneq (,$(filter $(CPU_FAM),c0 f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl))
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endif
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ifneq (,$(filter $(CPU_FAM),f0 f2 f3 f4 f7 l0 l1 l4 l5 u5 wb wl))
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CPU_MODELS_WITHOUT_RTC_BKPR += stm32f030% stm32f070%
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CPU_MODELS_WITHOUT_RTC_BKPR += stm32f030% stm32f070% \
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stm32f302%
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ifeq (,$(filter $(CPU_MODELS_WITHOUT_RTC_BKPR),$(CPU_MODEL)))
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FEATURES_PROVIDED += periph_rtc_mem
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endif
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@ -26,109 +26,112 @@
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/* map some CPU specific register names */
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#if defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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#define EN_REG (RCC->CSR)
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#define EN_BIT (RCC_CSR_RTCEN)
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#define CLKSEL_MASK (RCC_CSR_RTCSEL)
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#define CLKSEL_LSE (RCC_CSR_RTCSEL_LSE)
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#define CLKSEL_LSI (RCC_CSR_RTCSEL_LSI)
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# define EN_REG (RCC->CSR)
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# define EN_BIT (RCC_CSR_RTCEN)
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# define CLKSEL_MASK (RCC_CSR_RTCSEL)
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# define CLKSEL_LSE (RCC_CSR_RTCSEL_LSE)
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# define CLKSEL_LSI (RCC_CSR_RTCSEL_LSI)
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#else
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#define EN_REG (RCC->BDCR)
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#define EN_BIT (RCC_BDCR_RTCEN)
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#define CLKSEL_MASK (RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
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#define CLKSEL_LSE (RCC_BDCR_RTCSEL_0)
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#define CLKSEL_LSI (RCC_BDCR_RTCSEL_1)
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# define EN_REG (RCC->BDCR)
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# define EN_BIT (RCC_BDCR_RTCEN)
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# define CLKSEL_MASK (RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
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# define CLKSEL_LSE (RCC_BDCR_RTCSEL_0)
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# define CLKSEL_LSI (RCC_BDCR_RTCSEL_1)
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#endif
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/* map some EXTI register names */
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
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defined(CPU_FAM_STM32G4)
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#define EXTI_REG_RTSR (EXTI->RTSR1)
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#define EXTI_REG_FTSR (EXTI->FTSR1)
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#define EXTI_REG_PR (EXTI->PR1)
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#define EXTI_REG_IMR (EXTI->IMR1)
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#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32U5)
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#define EXTI_REG_RTSR (EXTI->RTSR1)
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#define EXTI_REG_FTSR (EXTI->FTSR1)
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#define EXTI_REG_PR (EXTI->RPR1)
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#define EXTI_REG_IMR (EXTI->IMR1)
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# define EXTI_REG_RTSR (EXTI->RTSR1)
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# define EXTI_REG_FTSR (EXTI->FTSR1)
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# define EXTI_REG_PR (EXTI->PR1)
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# define EXTI_REG_IMR (EXTI->IMR1)
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#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
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# define EXTI_REG_RTSR (EXTI->RTSR1)
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# define EXTI_REG_FTSR (EXTI->FTSR1)
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# define EXTI_REG_PR (EXTI->RPR1)
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# define EXTI_REG_IMR (EXTI->IMR1)
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#elif defined(CPU_FAM_STM32L5)
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#define EXTI_REG_IMR (EXTI->IMR1)
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# define EXTI_REG_IMR (EXTI->IMR1)
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#else
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#define EXTI_REG_RTSR (EXTI->RTSR)
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#define EXTI_REG_FTSR (EXTI->FTSR)
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#define EXTI_REG_PR (EXTI->PR)
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#define EXTI_REG_IMR (EXTI->IMR)
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# define EXTI_REG_RTSR (EXTI->RTSR)
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# define EXTI_REG_FTSR (EXTI->FTSR)
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# define EXTI_REG_PR (EXTI->PR)
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# define EXTI_REG_IMR (EXTI->IMR)
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#endif
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/* map some RTC register names and bitfield */
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#if defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0)
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#define RTC_REG_ISR RTC->ICSR
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#define RTC_REG_SR RTC->SR
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#define RTC_REG_SCR RTC->SCR
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#define RTC_ISR_RSF RTC_ICSR_RSF
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#define RTC_ISR_INIT RTC_ICSR_INIT
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#define RTC_ISR_INITF RTC_ICSR_INITF
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#define RTC_ISR_ALRAWF RTC_ICSR_ALRAWF
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#define RTC_ISR_ALRAF RTC_SR_ALRAF
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#elif defined(CPU_FAM_STM32L5)
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#define RTC_REG_ISR RTC->ICSR
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#define RTC_REG_SR RTC->SR
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#define RTC_REG_SCR RTC->SCR
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#define RTC_ISR_RSF RTC_ICSR_RSF
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#define RTC_ISR_INIT RTC_ICSR_INIT
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#define RTC_ISR_INITF RTC_ICSR_INITF
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# define RTC_REG_ISR RTC->ICSR
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# define RTC_REG_SR RTC->SR
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# define RTC_REG_SCR RTC->SCR
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# define RTC_ISR_RSF RTC_ICSR_RSF
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# define RTC_ISR_INIT RTC_ICSR_INIT
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# define RTC_ISR_INITF RTC_ICSR_INITF
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# define RTC_ISR_INITS RTC_ICSR_INITS
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# define RTC_ISR_ALRAWF RTC_ICSR_ALRAWF
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# define RTC_ISR_ALRAF RTC_SR_ALRAF
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#elif defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
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# define RTC_REG_ISR RTC->ICSR
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# define RTC_REG_SR RTC->SR
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# define RTC_REG_SCR RTC->SCR
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# define RTC_ISR_RSF RTC_ICSR_RSF
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# define RTC_ISR_INIT RTC_ICSR_INIT
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# define RTC_ISR_INITF RTC_ICSR_INITF
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# define RTC_ISR_INITS RTC_ICSR_INITS
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#elif defined(CPU_FAM_STM32U5)
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#define RTC_REG_ISR RTC->ICSR
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#define RTC_REG_SR RTC->SR
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#define RTC_REG_SCR RTC->SCR
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#define RTC_ISR_RSF RTC_ICSR_RSF
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#define RTC_ISR_INIT RTC_ICSR_INIT
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#define RTC_ISR_INITF RTC_ICSR_INITF
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#define RTC_ISR_ALRAF RTC_SR_ALRAF
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# define RTC_REG_ISR RTC->ICSR
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# define RTC_REG_SR RTC->SR
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# define RTC_REG_SCR RTC->SCR
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# define RTC_ISR_RSF RTC_ICSR_RSF
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# define RTC_ISR_INIT RTC_ICSR_INIT
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# define RTC_ISR_INITF RTC_ICSR_INITF
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# define RTC_ISR_INITS RTC_ICSR_INITS
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# define RTC_ISR_ALRAF RTC_SR_ALRAF
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#else
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#define RTC_REG_ISR RTC->ISR
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# define RTC_REG_ISR RTC->ISR
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#endif
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/* interrupt line name mapping */
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
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defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
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#define IRQN (RTC_IRQn)
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#define ISR_NAME isr_rtc
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# define IRQN (RTC_IRQn)
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# define ISR_NAME isr_rtc
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#elif defined(CPU_FAM_STM32G0)
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#define IRQN (RTC_TAMP_IRQn)
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#define ISR_NAME isr_rtc_tamp
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# define IRQN (RTC_TAMP_IRQn)
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# define ISR_NAME isr_rtc_tamp
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#else
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#define IRQN (RTC_Alarm_IRQn)
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#define ISR_NAME isr_rtc_alarm
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# define IRQN (RTC_Alarm_IRQn)
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# define ISR_NAME isr_rtc_alarm
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#endif
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/* EXTI bitfield mapping */
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#if defined(CPU_FAM_STM32L4)
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#define EXTI_IMR_BIT (EXTI_IMR1_IM18)
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#define EXTI_FTSR_BIT (EXTI_FTSR1_FT18)
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#define EXTI_RTSR_BIT (EXTI_RTSR1_RT18)
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#define EXTI_PR_BIT (EXTI_PR1_PIF18)
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#elif defined(CPU_FAM_STM32L5)
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#define EXTI_IMR_BIT (EXTI_IMR1_IM17)
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# define EXTI_IMR_BIT (EXTI_IMR1_IM18)
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# define EXTI_FTSR_BIT (EXTI_FTSR1_FT18)
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# define EXTI_RTSR_BIT (EXTI_RTSR1_RT18)
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# define EXTI_PR_BIT (EXTI_PR1_PIF18)
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#elif defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
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# define EXTI_IMR_BIT (EXTI_IMR1_IM17)
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#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
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#define EXTI_IMR_BIT (EXTI_IMR1_IM17)
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#define EXTI_FTSR_BIT (EXTI_FTSR1_FT17)
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#define EXTI_RTSR_BIT (EXTI_RTSR1_RT17)
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#define EXTI_PR_BIT (EXTI_PR1_PIF17)
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# define EXTI_IMR_BIT (EXTI_IMR1_IM17)
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# define EXTI_FTSR_BIT (EXTI_FTSR1_FT17)
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# define EXTI_RTSR_BIT (EXTI_RTSR1_RT17)
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# define EXTI_PR_BIT (EXTI_PR1_PIF17)
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#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32U5)
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#define EXTI_IMR_BIT (EXTI_IMR1_IM11)
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#define EXTI_FTSR_BIT (EXTI_FTSR1_FT11)
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#define EXTI_RTSR_BIT (EXTI_RTSR1_RT11)
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#define EXTI_PR_BIT (EXTI_RPR1_RPIF11)
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# define EXTI_IMR_BIT (EXTI_IMR1_IM11)
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# define EXTI_FTSR_BIT (EXTI_FTSR1_FT11)
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# define EXTI_RTSR_BIT (EXTI_RTSR1_RT11)
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# define EXTI_PR_BIT (EXTI_RPR1_RPIF11)
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#else
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#if defined(CPU_FAM_STM32L0)
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#define EXTI_IMR_BIT (EXTI_IMR_IM17)
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#else
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#define EXTI_IMR_BIT (EXTI_IMR_MR17)
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#endif
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#define EXTI_FTSR_BIT (EXTI_FTSR_TR17)
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#define EXTI_RTSR_BIT (EXTI_RTSR_TR17)
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#define EXTI_PR_BIT (EXTI_PR_PR17)
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# if defined(CPU_FAM_STM32L0)
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# define EXTI_IMR_BIT (EXTI_IMR_IM17)
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# else
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# define EXTI_IMR_BIT (EXTI_IMR_MR17)
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# endif
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# define EXTI_FTSR_BIT (EXTI_FTSR_TR17)
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# define EXTI_RTSR_BIT (EXTI_RTSR_TR17)
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# define EXTI_PR_BIT (EXTI_PR_PR17)
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#endif
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/* write protection values */
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@ -147,62 +150,62 @@
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#define ALRM_M_MASK (RTC_ALRMAR_MNU | RTC_ALRMAR_MNT)
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#define ALRM_S_MASK (RTC_ALRMAR_SU | RTC_ALRMAR_ST)
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#ifndef RTC_DR_YU_Pos
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#define RTC_DR_YU_Pos (16U)
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# define RTC_DR_YU_Pos (16U)
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#endif
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#ifndef RTC_DR_MU_Pos
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#define RTC_DR_MU_Pos (8U)
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# define RTC_DR_MU_Pos (8U)
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#endif
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#ifndef RTC_DR_DU_Pos
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#define RTC_DR_DU_Pos (0U)
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# define RTC_DR_DU_Pos (0U)
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#endif
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#ifndef RTC_TR_HU_Pos
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#define RTC_TR_HU_Pos (16U)
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# define RTC_TR_HU_Pos (16U)
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#endif
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#ifndef RTC_TR_MNU_Pos
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#define RTC_TR_MNU_Pos (8U)
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# define RTC_TR_MNU_Pos (8U)
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#endif
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#ifndef RTC_TR_SU_Pos
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#define RTC_TR_SU_Pos (0U)
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# define RTC_TR_SU_Pos (0U)
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#endif
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#ifndef RTC_ALRMAR_DU_Pos
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#define RTC_ALRMAR_DU_Pos (24U)
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# define RTC_ALRMAR_DU_Pos (24U)
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#endif
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#ifndef RTC_ALRMAR_HU_Pos
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#define RTC_ALRMAR_HU_Pos (16U)
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# define RTC_ALRMAR_HU_Pos (16U)
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#endif
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#ifndef RTC_ALRMAR_MNU_Pos
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#define RTC_ALRMAR_MNU_Pos (8U)
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# define RTC_ALRMAR_MNU_Pos (8U)
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#endif
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#ifndef RTC_ALRMAR_SU_Pos
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#define RTC_ALRMAR_SU_Pos (0U)
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# define RTC_ALRMAR_SU_Pos (0U)
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#endif
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/* figure out sync and async prescaler */
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#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
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#define PRE_SYNC (255)
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#define PRE_ASYNC (127)
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# define PRE_SYNC (255)
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# define PRE_ASYNC (127)
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#elif (CLOCK_LSI == 40000)
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#define PRE_SYNC (319)
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#define PRE_ASYNC (124)
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# define PRE_SYNC (319)
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# define PRE_ASYNC (124)
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#elif (CLOCK_LSI == 37000)
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#define PRE_SYNC (295)
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#define PRE_ASYNC (124)
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# define PRE_SYNC (295)
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# define PRE_ASYNC (124)
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#elif (CLOCK_LSI == 32000)
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#define PRE_SYNC (249)
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#define PRE_ASYNC (127)
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# define PRE_SYNC (249)
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# define PRE_ASYNC (127)
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#else
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#error "rtc: unable to determine RTC SYNC and ASYNC prescalers from LSI value"
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# error "RTC: unable to determine RTC SYNC and ASYNC prescalers from LSI value"
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#endif
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/* struct tm counts years since 1900 but RTC has only two-digit year, hence the offset */
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#define YEAR_OFFSET (RIOT_EPOCH - 1900)
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/* Use a magic number to determine the initial RTC source. This will be used
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to know if a reset of the RTC is required at initialization. */
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* to know if a reset of the RTC is required at initialization. */
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#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
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#define MAGIC_CLCK_NUMBER (0x1970)
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# define MAGIC_CLCK_NUMBER (0x1970)
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#else
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#define MAGIC_CLCK_NUMBER (0x1971)
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# define MAGIC_CLCK_NUMBER (0x1971)
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#endif
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static struct {
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@ -228,6 +231,14 @@ static int bcd2val(uint32_t val, int shift, uint32_t mask)
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return (((tmp >> 4) * 10) + (tmp & 0x0f));
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}
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void rtc_lock(void)
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{
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/* lock RTC device */
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RTC->WPR = 0xff;
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/* disable backup clock domain */
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stmclk_dbp_lock();
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}
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void rtc_unlock(void)
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{
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/* enable backup clock domain */
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@ -235,20 +246,22 @@ void rtc_unlock(void)
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/* unlock RTC */
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RTC->WPR = WPK1;
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RTC->WPR = WPK2;
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}
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static inline void rtc_enter_init_mode(void)
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{
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rtc_unlock();
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/* enter RTC init mode */
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RTC_REG_ISR |= RTC_ISR_INIT;
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while (!(RTC_REG_ISR & RTC_ISR_INITF)) {}
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}
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void rtc_lock(void)
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static inline void rtc_exit_init_mode(void)
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{
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/* exit RTC init mode */
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RTC_REG_ISR &= ~RTC_ISR_INIT;
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while (RTC_REG_ISR & RTC_ISR_INITF) {}
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/* lock RTC device */
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RTC->WPR = 0xff;
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/* disable backup clock domain */
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stmclk_dbp_lock();
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rtc_lock();
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}
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void rtc_init(void)
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@ -256,47 +269,53 @@ void rtc_init(void)
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stmclk_dbp_unlock();
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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/* Compare the stored magic number with the current one. If it's different
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it means the clock source has changed and thus a RTC reset is
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required. */
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* it means the clock source has changed and thus a RTC reset is
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* required. */
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if (RTC->BKP0R != MAGIC_CLCK_NUMBER) {
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RCC->CSR |= RCC_CSR_RTCRST;
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RCC->CSR &= ~RCC_CSR_RTCRST;
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RTC->BKP0R = MAGIC_CLCK_NUMBER; /* Store the new magic number */
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}
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#endif
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stmclk_dbp_lock();
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/* enable low frequency clock */
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stmclk_enable_lfclk();
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/* select input clock and enable the RTC */
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stmclk_dbp_unlock();
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#if defined(CPU_FAM_STM32L5)
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#if defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
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periph_clk_en(APB1, RCC_APB1ENR1_RTCAPBEN);
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#elif defined(CPU_FAM_STM32G0)
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periph_clk_en(APB1, RCC_APBENR1_RTCAPBEN);
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#elif defined(CPU_FAM_STM32U5)
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periph_clk_en(APB3, RCC_APB3ENR_RTCAPBEN);
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#endif
|
||||
EN_REG &= ~(CLKSEL_MASK);
|
||||
|
||||
#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
|
||||
EN_REG |= (CLKSEL_LSE | EN_BIT);
|
||||
if ((EN_REG & (CLKSEL_MASK | EN_BIT)) != (CLKSEL_LSE | EN_BIT)) {
|
||||
EN_REG &= ~(CLKSEL_MASK);
|
||||
EN_REG |= (CLKSEL_LSE | EN_BIT);
|
||||
}
|
||||
#else
|
||||
EN_REG |= (CLKSEL_LSI | EN_BIT);
|
||||
if ((EN_REG & (CLKSEL_MASK | EN_BIT)) != (CLKSEL_LSI | EN_BIT)) {
|
||||
EN_REG &= ~(CLKSEL_MASK);
|
||||
EN_REG |= (CLKSEL_LSI | EN_BIT);
|
||||
}
|
||||
#endif
|
||||
|
||||
rtc_unlock();
|
||||
/* reset configuration */
|
||||
RTC->CR = 0;
|
||||
RTC_REG_ISR = RTC_ISR_INIT;
|
||||
/* configure prescaler (RTC PRER) */
|
||||
RTC->PRER = (PRE_SYNC | (PRE_ASYNC << 16));
|
||||
rtc_lock();
|
||||
if (!(RTC_REG_ISR & RTC_ISR_INITS))
|
||||
{
|
||||
rtc_enter_init_mode();
|
||||
/* reset configuration */
|
||||
RTC->CR = 0;
|
||||
/* configure prescaler (RTC PRER) */
|
||||
RTC->PRER = (PRE_SYNC | (PRE_ASYNC << 16));
|
||||
rtc_exit_init_mode();
|
||||
}
|
||||
|
||||
/* configure the EXTI channel, as RTC interrupts are routed through it.
|
||||
* Needs to be configured to trigger on rising edges. */
|
||||
EXTI_REG_IMR |= EXTI_IMR_BIT;
|
||||
#if !defined(CPU_FAM_STM32L5)
|
||||
#if !(defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL))
|
||||
EXTI_REG_FTSR &= ~(EXTI_FTSR_BIT);
|
||||
EXTI_REG_RTSR |= EXTI_RTSR_BIT;
|
||||
EXTI_REG_PR = EXTI_PR_BIT;
|
||||
@ -310,15 +329,14 @@ int rtc_set_time(struct tm *time)
|
||||
/* normalize input */
|
||||
rtc_tm_normalize(time);
|
||||
|
||||
rtc_unlock();
|
||||
|
||||
rtc_enter_init_mode();
|
||||
RTC->DR = (val2bcd((time->tm_year - YEAR_OFFSET), RTC_DR_YU_Pos, DR_Y_MASK) |
|
||||
val2bcd(time->tm_mon + 1, RTC_DR_MU_Pos, DR_M_MASK) |
|
||||
val2bcd(time->tm_mday, RTC_DR_DU_Pos, DR_D_MASK));
|
||||
RTC->TR = (val2bcd(time->tm_hour, RTC_TR_HU_Pos, TR_H_MASK) |
|
||||
val2bcd(time->tm_min, RTC_TR_MNU_Pos, TR_M_MASK) |
|
||||
val2bcd(time->tm_sec, RTC_TR_SU_Pos, TR_S_MASK));
|
||||
rtc_lock();
|
||||
rtc_exit_init_mode();
|
||||
while (!(RTC_REG_ISR & RTC_ISR_RSF)) {}
|
||||
|
||||
return 0;
|
||||
@ -326,6 +344,16 @@ int rtc_set_time(struct tm *time)
|
||||
|
||||
int rtc_get_time(struct tm *time)
|
||||
{
|
||||
/* After waking up from standby, the RSF flag has to be manually cleared.
|
||||
* To be safe, we do it every time even though we might not have been in
|
||||
* standby before. */
|
||||
rtc_unlock();
|
||||
RTC_REG_ISR &= ~RTC_ISR_RSF;
|
||||
rtc_lock();
|
||||
|
||||
/* waiting for the RSF bit to be set again before accessing the time */
|
||||
while (!(RTC_REG_ISR & RTC_ISR_RSF)) {};
|
||||
|
||||
/* save current time */
|
||||
uint32_t tr = RTC->TR;
|
||||
uint32_t dr = RTC->DR;
|
||||
@ -360,7 +388,7 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
|
||||
val2bcd(time->tm_sec, RTC_ALRMAR_SU_Pos, ALRM_S_MASK));
|
||||
|
||||
/* Enable Alarm A */
|
||||
#if !defined(CPU_FAM_STM32L5)
|
||||
#if !(defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL))
|
||||
RTC_REG_ISR &= ~(RTC_ISR_ALRAF);
|
||||
#else
|
||||
RTC_REG_SCR = RTC_SCR_CALRAF;
|
||||
@ -393,7 +421,7 @@ void rtc_clear_alarm(void)
|
||||
|
||||
RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE);
|
||||
|
||||
#if !defined(CPU_FAM_STM32L5) && !defined(CPU_FAM_STM32U5)
|
||||
#if !(defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL))
|
||||
while (!(RTC_REG_ISR & RTC_ISR_ALRAWF)) {}
|
||||
#else
|
||||
RTC_REG_SCR = RTC_SCR_CALRAF;
|
||||
@ -421,7 +449,8 @@ void rtc_poweroff(void)
|
||||
|
||||
void ISR_NAME(void)
|
||||
{
|
||||
#if !defined(CPU_FAM_STM32L5) && !defined(CPU_FAM_STM32G0) && !defined(CPU_FAM_STM32U5)
|
||||
#if !(defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32G0) || \
|
||||
defined(CPU_FAM_STM32U5))
|
||||
if (RTC_REG_ISR & RTC_ISR_ALRAF) {
|
||||
if (isr_ctx.cb != NULL) {
|
||||
isr_ctx.cb(isr_ctx.arg);
|
||||
|
||||
@ -138,7 +138,7 @@ int main(void)
|
||||
}
|
||||
|
||||
time = (struct tm){
|
||||
.tm_year = 2020 - 1900, /* years are counted from 1900 */
|
||||
.tm_year = 2025 - 1900, /* years are counted from 1900 */
|
||||
.tm_mon = 1, /* 0 = January, 11 = December */
|
||||
.tm_mday = 28,
|
||||
.tm_hour = 23,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user