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Merge pull request #10088 from unwireddevices/riot-fix-adxl345
drivers/adxl345: fix ADXL345 driver
This commit is contained in:
José Alamos
GitHub
commit
b3ec93d957
@ -23,14 +23,18 @@
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#include "assert.h"
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#include "periph/i2c.h"
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#include "byteorder.h"
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#include "adxl345.h"
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#include "adxl345_regs.h"
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#include "adxl345_params.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#define BUS (dev->params->i2c)
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#define ADDR (dev->params->addr)
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#define ADXL345_BUS (dev->params->i2c)
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#define ADXL345_ADDR (dev->params->addr)
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#define ADXL345_PARAM_SCALE_FACTOR (4)
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int adxl345_init(adxl345_t *dev, const adxl345_params_t* params)
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{
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@ -42,29 +46,30 @@ int adxl345_init(adxl345_t *dev, const adxl345_params_t* params)
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dev->params = (adxl345_params_t*)params;
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/* get scale_factor from full_res and range parameters */
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dev->scale_factor = (dev->params->full_res ? 3.9 : (dev->params->range * 3.9));
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dev->scale_factor = (dev->params->full_res ? ADXL345_PARAM_SCALE_FACTOR : (4 << dev->params->range));
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/* Acquire exclusive access */
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i2c_acquire(BUS);
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i2c_acquire(ADXL345_BUS);
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/* test if the target device responds */
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i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_CHIP_ID_REG, ®, 0);
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if (reg != ACCEL_ADXL345_CHIP_ID) {
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i2c_release(BUS);
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i2c_read_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_CHIP_ID_REG, ®, 0);
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if (reg != ADXL345_CHIP_ID) {
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i2c_release(ADXL345_BUS);
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DEBUG("[adxl345] init - error: invalid id value [0x%02x]\n", (int)reg);
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return ADXL345_NODEV;
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}
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/* configure the user offset */
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i2c_write_regs(BUS, ADDR, ACCEL_ADXL345_OFFSET_X, dev->params->offset, 3, 0);
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i2c_write_regs(ADXL345_BUS, ADXL345_ADDR, ADXL345_OFFSET_X, dev->params->offset, 3, 0);
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/* Basic device setup */
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reg = (dev->params->full_res | dev->params->range);
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_DATA_FORMAT, reg, 0);
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_BW_RATE, dev->params->rate, 0);
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reg = (dev->params->full_res ? ADXL345_FULL_RES : 0);
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reg |= dev->params->range;
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_DATA_FORMAT, reg, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_BW_RATE, dev->params->rate, 0);
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/* Put device in measure mode */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, MEASURE_BIT, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_POWER_CTL, ADXL345_MEASURE_BIT, 0);
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/* Release the bus */
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i2c_release(BUS);
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i2c_release(ADXL345_BUS);
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DEBUG("[adxl345] init: successful\n");
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@ -73,17 +78,25 @@ int adxl345_init(adxl345_t *dev, const adxl345_params_t* params)
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void adxl345_read(const adxl345_t *dev, adxl345_data_t *data)
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{
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int8_t result[6];
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int16_t result[3];
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assert(dev && data);
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i2c_acquire(BUS);
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i2c_read_regs(BUS, ADDR, ACCEL_ADXL345_DATA_X0, result, 6, 0);
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i2c_release(BUS);
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i2c_acquire(ADXL345_BUS);
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i2c_read_regs(ADXL345_BUS, ADXL345_ADDR, ADXL345_DATA_X0, (void *)result, 6, 0);
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i2c_release(ADXL345_BUS);
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data->x = (((result[1] << 8)+result[0]) * dev->scale_factor);
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data->y = (((result[3] << 8)+result[2]) * dev->scale_factor);
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data->z = (((result[5] << 8)+result[4]) * dev->scale_factor);
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/* ADXL345 returns value in little endian, so swap is needed on big endian
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* platforms. See Analog Devices ADXL345 datasheet page 27. */
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#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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for (int i = 0; i < 3; i++) {
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result[i] = byteorder_swaps((uint16_t)result[i]);
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}
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#endif
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data->x = result[0] * dev->scale_factor;
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data->y = result[1] * dev->scale_factor;
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data->z = result[2] * dev->scale_factor;
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}
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void adxl345_set_interrupt(const adxl345_t *dev)
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@ -92,38 +105,38 @@ void adxl345_set_interrupt(const adxl345_t *dev)
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DEBUG("[adxl345] Update interruptions configuration\n");
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i2c_acquire(BUS);
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i2c_acquire(ADXL345_BUS);
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/* Set threshold */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_TAP, dev->interrupt.thres_tap, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_THRESH_TAP, dev->interrupt.thres_tap, 0);
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/* Set Map */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_INT_MAP, dev->interrupt.map, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_INT_MAP, dev->interrupt.map, 0);
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/* Set Duration */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_DUR, dev->interrupt.thres_dur, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_TAP_DUR, dev->interrupt.thres_dur, 0);
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/* Enable axes */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_AXES, dev->interrupt.tap_axes, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_TAP_AXES, dev->interrupt.tap_axes, 0);
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/* Set source */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_INT_SOURCE, dev->interrupt.source, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_INT_SOURCE, dev->interrupt.source, 0);
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/* Set latent threshold */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_LAT, dev->interrupt.thres_latent, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_TAP_LAT, dev->interrupt.thres_latent, 0);
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/* Set window threshold */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_WIN, dev->interrupt.thres_window, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_TAP_WIN, dev->interrupt.thres_window, 0);
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/* Set activity threshold */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_ACT, dev->interrupt.thres_act, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_THRESH_ACT, dev->interrupt.thres_act, 0);
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/* Set inactivity threshold */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_INACT, dev->interrupt.thres_inact, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_THRESH_INACT, dev->interrupt.thres_inact, 0);
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/* Set inactivity time */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TIME_INACT, dev->interrupt.time_inact, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_TIME_INACT, dev->interrupt.time_inact, 0);
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/* Set free-fall threshold */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_FF, dev->interrupt.thres_ff, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_THRESH_FF, dev->interrupt.thres_ff, 0);
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/* Set free-fall time */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TIME_FF, dev->interrupt.time_ff, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_TIME_FF, dev->interrupt.time_ff, 0);
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/* Set axis control */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_ACT_INACT_CTL, dev->interrupt.act_inact, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_ACT_INACT_CTL, dev->interrupt.act_inact, 0);
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/* Enable interrupt */
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_INT_ENABLE, dev->interrupt.enable, 0);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_INT_ENABLE, dev->interrupt.enable, 0);
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/* Release the bus */
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i2c_release(BUS);
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i2c_release(ADXL345_BUS);
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}
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void adxl345_set_measure(const adxl345_t *dev)
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@ -134,11 +147,11 @@ void adxl345_set_measure(const adxl345_t *dev)
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DEBUG("[adxl345] set device to measure mode\n");
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i2c_acquire(BUS);
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i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, ®, 0);
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reg |= MEASURE_BIT;
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg, 0);
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i2c_release(BUS);
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i2c_acquire(ADXL345_BUS);
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i2c_read_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_POWER_CTL, ®, 0);
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reg |= ADXL345_MEASURE_BIT;
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_POWER_CTL, reg, 0);
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i2c_release(ADXL345_BUS);
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}
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void adxl345_set_standby(const adxl345_t *dev)
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@ -149,11 +162,11 @@ void adxl345_set_standby(const adxl345_t *dev)
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DEBUG("[adxl345] set device to standby mode\n");
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i2c_acquire(BUS);
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i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, ®, 0);
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reg &= ~MEASURE_BIT;
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg, 0);
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i2c_release(BUS);
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i2c_acquire(ADXL345_BUS);
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i2c_read_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_POWER_CTL, ®, 0);
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reg &= ~ADXL345_MEASURE_BIT;
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_POWER_CTL, reg, 0);
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i2c_release(ADXL345_BUS);
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}
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void adxl345_set_sleep(const adxl345_t *dev)
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@ -164,11 +177,11 @@ void adxl345_set_sleep(const adxl345_t *dev)
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DEBUG("[adxl345] set device to sleep mode\n");
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i2c_acquire(BUS);
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i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, ®, 0);
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reg |= SLEEP_BIT;
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg, 0);
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i2c_release(BUS);
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i2c_acquire(ADXL345_BUS);
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i2c_read_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_POWER_CTL, ®, 0);
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reg |= ADXL345_SLEEP_BIT;
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_POWER_CTL, reg, 0);
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i2c_release(ADXL345_BUS);
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}
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void adxl345_set_autosleep(const adxl345_t *dev)
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@ -179,11 +192,11 @@ void adxl345_set_autosleep(const adxl345_t *dev)
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DEBUG("[adxl345] set device to autosleep mode\n");
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i2c_acquire(BUS);
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i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, ®, 0);
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reg |= AUTOSLEEP_BIT;
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg, 0);
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i2c_release(BUS);
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i2c_acquire(ADXL345_BUS);
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i2c_read_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_POWER_CTL, ®, 0);
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reg |= ADXL345_AUTOSLEEP_BIT;
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_POWER_CTL, reg, 0);
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i2c_release(ADXL345_BUS);
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}
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void adxl345_set_bandwidth_rate(const adxl345_t *dev, uint8_t bw_rate)
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@ -194,11 +207,11 @@ void adxl345_set_bandwidth_rate(const adxl345_t *dev, uint8_t bw_rate)
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DEBUG("[adxl345] set device rate to %d Hz\n", (int)bw_rate);
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i2c_acquire(BUS);
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i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_BW_RATE, ®, 0);
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i2c_acquire(ADXL345_BUS);
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i2c_read_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_BW_RATE, ®, 0);
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reg |= bw_rate;
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_BW_RATE, reg, 0);
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i2c_release(BUS);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_BW_RATE, reg, 0);
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i2c_release(ADXL345_BUS);
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}
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void adxl345_set_fifo_mode(const adxl345_t *dev, uint8_t mode,
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@ -211,8 +224,8 @@ void adxl345_set_fifo_mode(const adxl345_t *dev, uint8_t mode,
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DEBUG("[adxl345] set fifo mode to %d, output trigger to %d and trigger "
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"value to :%d\n", (int)mode, (int)output, (int)value);
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i2c_acquire(BUS);
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reg = ((mode << FIFO_MODE_POS) | (output << FIFO_TRIGGER_POS) | value);
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i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_FIFO_CTL, reg, 0);
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i2c_release(BUS);
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i2c_acquire(ADXL345_BUS);
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reg = ((mode << ADXL345_FIFO_MODE_POS) | (output << ADXL345_FIFO_TRIGGER_POS) | value);
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i2c_write_reg(ADXL345_BUS, ADXL345_ADDR, ADXL345_FIFO_CTL, reg, 0);
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i2c_release(ADXL345_BUS);
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}
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@ -53,9 +53,7 @@ extern "C" {
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#ifndef ADXL345_PARAM_OFFSET
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#define ADXL345_PARAM_OFFSET { 0, 0, 0 }
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#endif
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#ifndef ADXL345_PARAM_SCALE_FACTOR
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#define ADXL345_PARAM_SCALE_FACTOR (3.9)
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#endif
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#ifndef ADXL345_PARAMS
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#define ADXL345_PARAMS { .i2c = ADXL345_PARAM_I2C, \
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.addr = ADXL345_PARAM_ADDR, \
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@ -27,113 +27,115 @@
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* @name Register addresses
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* @{
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*/
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#define ACCEL_ADXL345_CHIP_ID_REG (0x00) /**< Device ID */
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#define ACCEL_ADXL345_THRESH_TAP (0x1D) /**< Tap threshold */
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#define ACCEL_ADXL345_OFFSET_X (0x1E) /**< X-axis offset */
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#define ACCEL_ADXL345_OFFSET_Y (0x1F) /**< Y-axis offset */
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#define ACCEL_ADXL345_OFFSET_Z (0x20) /**< Z-axis offset */
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#define ACCEL_ADXL345_TAP_DUR (0x21) /**< Tap duration */
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#define ACCEL_ADXL345_TAP_LAT (0x22) /**< Tap latency */
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#define ACCEL_ADXL345_TAP_WIN (0x23) /**< Tap window */
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#define ACCEL_ADXL345_THRESH_ACT (0x24) /**< Activity threshold */
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#define ACCEL_ADXL345_THRESH_INACT (0x25) /**< Inactivity threshold */
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#define ACCEL_ADXL345_TIME_INACT (0x26) /**< Inactivity time */
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#define ACCEL_ADXL345_ACT_INACT_CTL (0x27) /**< Axis enable control for activity and inactivity detection */
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#define ACCEL_ADXL345_THRESH_FF (0x28) /**< Free-fall threshold */
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#define ACCEL_ADXL345_TIME_FF (0x29) /**< Free-fall time */
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#define ACCEL_ADXL345_TAP_AXES (0x2A) /**< Axis control for single tap/double tap */
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#define ACCEL_ADXL345_ACT_TAP_STATUS (0x2B) /**< Source of single tap/double tap */
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#define ACCEL_ADXL345_BW_RATE (0x2C) /**< Data rate and power mode control */
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#define ACCEL_ADXL345_POWER_CTL (0x2D) /**< Power-saving features control */
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#define ACCEL_ADXL345_INT_ENABLE (0x2E) /**< Interrupt enable control */
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#define ACCEL_ADXL345_INT_MAP (0x2F) /**< Interrupt mapping control */
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#define ACCEL_ADXL345_INT_SOURCE (0x30) /**< Source of interrupts */
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#define ACCEL_ADXL345_DATA_FORMAT (0x31) /**< Data format control */
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#define ACCEL_ADXL345_DATA_X0 (0x32) /**< X-Axis Data 0 */
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#define ACCEL_ADXL345_DATA_X1 (0x33) /**< X-Axis Data 1 */
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#define ACCEL_ADXL345_DATA_Y0 (0x34) /**< Y-Axis Data 0 */
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#define ACCEL_ADXL345_DATA_Y1 (0x35) /**< Y-Axis Data 1 */
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#define ACCEL_ADXL345_DATA_Z0 (0x36) /**< Z-Axis Data 0 */
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#define ACCEL_ADXL345_DATA_Z1 (0x37) /**< Z-Axis Data 1 */
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#define ACCEL_ADXL345_FIFO_CTL (0x38) /**< FIFO control */
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#define ACCEL_ADXL345_FIFO_STATUS (0x39) /**< FIFO status */
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#define ADXL345_CHIP_ID_REG (0x00) /**< Device ID */
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#define ADXL345_THRESH_TAP (0x1D) /**< Tap threshold */
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#define ADXL345_OFFSET_X (0x1E) /**< X-axis offset */
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#define ADXL345_OFFSET_Y (0x1F) /**< Y-axis offset */
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#define ADXL345_OFFSET_Z (0x20) /**< Z-axis offset */
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#define ADXL345_TAP_DUR (0x21) /**< Tap duration */
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#define ADXL345_TAP_LAT (0x22) /**< Tap latency */
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#define ADXL345_TAP_WIN (0x23) /**< Tap window */
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#define ADXL345_THRESH_ACT (0x24) /**< Activity threshold */
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#define ADXL345_THRESH_INACT (0x25) /**< Inactivity threshold */
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#define ADXL345_TIME_INACT (0x26) /**< Inactivity time */
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#define ADXL345_ACT_INACT_CTL (0x27) /**< Axis enable control for activity and inactivity detection */
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#define ADXL345_THRESH_FF (0x28) /**< Free-fall threshold */
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#define ADXL345_TIME_FF (0x29) /**< Free-fall time */
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#define ADXL345_TAP_AXES (0x2A) /**< Axis control for single tap/double tap */
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#define ADXL345_ACT_TAP_STATUS (0x2B) /**< Source of single tap/double tap */
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#define ADXL345_BW_RATE (0x2C) /**< Data rate and power mode control */
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#define ADXL345_POWER_CTL (0x2D) /**< Power-saving features control */
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||||
#define ADXL345_INT_ENABLE (0x2E) /**< Interrupt enable control */
|
||||
#define ADXL345_INT_MAP (0x2F) /**< Interrupt mapping control */
|
||||
#define ADXL345_INT_SOURCE (0x30) /**< Source of interrupts */
|
||||
#define ADXL345_DATA_FORMAT (0x31) /**< Data format control */
|
||||
#define ADXL345_DATA_X0 (0x32) /**< X-Axis Data 0 */
|
||||
#define ADXL345_DATA_X1 (0x33) /**< X-Axis Data 1 */
|
||||
#define ADXL345_DATA_Y0 (0x34) /**< Y-Axis Data 0 */
|
||||
#define ADXL345_DATA_Y1 (0x35) /**< Y-Axis Data 1 */
|
||||
#define ADXL345_DATA_Z0 (0x36) /**< Z-Axis Data 0 */
|
||||
#define ADXL345_DATA_Z1 (0x37) /**< Z-Axis Data 1 */
|
||||
#define ADXL345_FIFO_CTL (0x38) /**< FIFO control */
|
||||
#define ADXL345_FIFO_STATUS (0x39) /**< FIFO status */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Device ID for ADXL345
|
||||
* @{
|
||||
*/
|
||||
#define ACCEL_ADXL345_CHIP_ID (0xE5)
|
||||
#define ADXL345_CHIP_ID (0xE5)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Resolution masks for output data
|
||||
* @{
|
||||
*/
|
||||
#define RES_10_BITS (0x03FF)
|
||||
#define RES_11_BITS (0x07FF)
|
||||
#define RES_12_BITS (0x0FFF)
|
||||
#define RES_13_BITS (0x1FFF)
|
||||
#define ADXL345_RES_10_BITS (0x03FF)
|
||||
#define ADXL345_RES_11_BITS (0x07FF)
|
||||
#define ADXL345_RES_12_BITS (0x0FFF)
|
||||
#define ADXL345_RES_13_BITS (0x1FFF)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name bits definitions for ACT_INACT_CTL register
|
||||
* @{
|
||||
*/
|
||||
#define INACT_Z_ENABLE (1 << 0)
|
||||
#define INACT_Y_ENABLE (1 << 1)
|
||||
#define INACT_X_ENABLE (1 << 2)
|
||||
#define INACT_ACDC (1 << 3)
|
||||
#define ACT_Z_ENABLE (1 << 4)
|
||||
#define ACT_Y_ENABLE (1 << 5)
|
||||
#define ACT_X_ENABLE (1 << 6)
|
||||
#define ACT_ACDC (1 << 7)
|
||||
#define ADXL345_INACT_Z_ENABLE (1 << 0)
|
||||
#define ADXL345_INACT_Y_ENABLE (1 << 1)
|
||||
#define ADXL345_INACT_X_ENABLE (1 << 2)
|
||||
#define ADXL345_INACT_ACDC (1 << 3)
|
||||
#define ADXL345_ACT_Z_ENABLE (1 << 4)
|
||||
#define ADXL345_ACT_Y_ENABLE (1 << 5)
|
||||
#define ADXL345_ACT_X_ENABLE (1 << 6)
|
||||
#define ADXL345_ACT_ACDC (1 << 7)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name bits definitions for TAP_AXES register
|
||||
* @{
|
||||
*/
|
||||
#define TAP_Z_ENABLE (1 << 0)
|
||||
#define TAP_Y_ENABLE (1 << 1)
|
||||
#define TAP_X_ENABLE (1 << 2)
|
||||
#define SUPPRESS (1 << 3)
|
||||
#define TAP_ALL_ENABLE (TAP_Z_ENABLE|TAP_Y_ENABLE|TAP_X_ENABLE)
|
||||
#define ADXL345_TAP_Z_ENABLE (1 << 0)
|
||||
#define ADXL345_TAP_Y_ENABLE (1 << 1)
|
||||
#define ADXL345_TAP_X_ENABLE (1 << 2)
|
||||
#define ADXL345_SUPPRESS (1 << 3)
|
||||
#define ADXL345_TAP_ALL_ENABLE (ADXL345_TAP_Z_ENABLE | \
|
||||
ADXL345_TAP_Y_ENABLE | \
|
||||
ADXL345_TAP_X_ENABLE)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name bits definitions for ACT_TAP_STATUS register
|
||||
* @{
|
||||
*/
|
||||
#define TAP_Z_SRC (1 << 0)
|
||||
#define TAP_Y_SRC (1 << 1)
|
||||
#define TAP_X_SRC (1 << 2)
|
||||
#define ASLEEP (1 << 3)
|
||||
#define ACT_Z_SRC (1 << 4)
|
||||
#define ACT_Y_SRC (1 << 5)
|
||||
#define ACT_X_SRC (1 << 6)
|
||||
#define ADXL345_TAP_Z_SRC (1 << 0)
|
||||
#define ADXL345_TAP_Y_SRC (1 << 1)
|
||||
#define ADXL345_TAP_X_SRC (1 << 2)
|
||||
#define ADXL345_ASLEEP (1 << 3)
|
||||
#define ADXL345_ACT_Z_SRC (1 << 4)
|
||||
#define ADXL345_ACT_Y_SRC (1 << 5)
|
||||
#define ADXL345_ACT_X_SRC (1 << 6)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name bits definitions for BW_RATE register
|
||||
* @{
|
||||
*/
|
||||
#define RATE_MASK (0x0F)
|
||||
#define LOWPOWER (1 << 4)
|
||||
#define ADXL345_RATE_MASK (0x0F)
|
||||
#define ADXL345_LOWPOWER (1 << 4)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name bits definitions for PWR_CTL register
|
||||
* @{
|
||||
*/
|
||||
#define WAKEUP_8HZ (0x00)
|
||||
#define WAKEUP_4HZ (0x01)
|
||||
#define WAKEUP_2HZ (0x02)
|
||||
#define WAKEUP_1HZ (0x03)
|
||||
#define SLEEP_BIT (1 << 2)
|
||||
#define MEASURE_BIT (1 << 3)
|
||||
#define AUTOSLEEP_BIT (1 << 4)
|
||||
#define LINK_BIT (1 << 5)
|
||||
#define ADXL345_WAKEUP_8HZ (0x00)
|
||||
#define ADXL345_WAKEUP_4HZ (0x01)
|
||||
#define ADXL345_WAKEUP_2HZ (0x02)
|
||||
#define ADXL345_WAKEUP_1HZ (0x03)
|
||||
#define ADXL345_SLEEP_BIT (1 << 2)
|
||||
#define ADXL345_MEASURE_BIT (1 << 3)
|
||||
#define ADXL345_AUTOSLEEP_BIT (1 << 4)
|
||||
#define ADXL345_LINK_BIT (1 << 5)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
@ -141,45 +143,45 @@
|
||||
* registers
|
||||
* @{
|
||||
*/
|
||||
#define OVERRUN (1 << 0)
|
||||
#define WATERMARK (1 << 1)
|
||||
#define FREEFALL (1 << 2)
|
||||
#define INACTIVITY (1 << 3)
|
||||
#define ACTIVITY (1 << 4)
|
||||
#define DOUBLE_TAP (1 << 5)
|
||||
#define SINGLE_TAP (1 << 6)
|
||||
#define DATA_READY (1 << 7)
|
||||
#define ADXL345_OVERRUN (1 << 0)
|
||||
#define ADXL345_WATERMARK (1 << 1)
|
||||
#define ADXL345_FREEFALL (1 << 2)
|
||||
#define ADXL345_INACTIVITY (1 << 3)
|
||||
#define ADXL345_ACTIVITY (1 << 4)
|
||||
#define ADXL345_DOUBLE_TAP (1 << 5)
|
||||
#define ADXL345_SINGLE_TAP (1 << 6)
|
||||
#define ADXL345_DATA_READY (1 << 7)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name bits definitions for DATA_FORMAT register
|
||||
* @{
|
||||
*/
|
||||
#define RANGE_MASK (0x03)
|
||||
#define JUSTIFY (1 << 2)
|
||||
#define FULL_RES (1 << 3)
|
||||
#define INT_INVERT (1 << 5)
|
||||
#define SPI_BIT (1 << 6)
|
||||
#define SELF_TEST (1 << 7)
|
||||
#define ADXL345_RANGE_MASK (0x03)
|
||||
#define ADXL345_JUSTIFY (1 << 2)
|
||||
#define ADXL345_FULL_RES (1 << 3)
|
||||
#define ADXL345_INT_INVERT (1 << 5)
|
||||
#define ADXL345_SPI_BIT (1 << 6)
|
||||
#define ADXL345_SELF_TEST (1 << 7)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name bits definitions for FIFO_CTL register
|
||||
* @{
|
||||
*/
|
||||
#define SAMPLES_MASK (0x0F)
|
||||
#define FIFO_TRIGGER_POS (4)
|
||||
#define FIFO_TRIGGER (1 << FIFO_TRIGGER_POS)
|
||||
#define FIFO_MODE_POS (6)
|
||||
#define FIFO_MODE_MASK (0xC0)
|
||||
#define ADXL345_SAMPLES_MASK (0x0F)
|
||||
#define ADXL345_FIFO_TRIGGER_POS (4)
|
||||
#define ADXL345_FIFO_TRIGGER (1 << ADXL345_FIFO_TRIGGER_POS)
|
||||
#define ADXL345_FIFO_MODE_POS (6)
|
||||
#define ADXL345_FIFO_MODE_MASK (0xC0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name bits definitions for FIFO_STATUS register
|
||||
* @{
|
||||
*/
|
||||
#define FIFO_ENTRIES_MASK (0x3F)
|
||||
#define FIFO_TRIG (1 << 7)
|
||||
#define ADXL345_FIFO_ENTRIES_MASK (0x3F)
|
||||
#define ADXL345_FIFO_TRIG (1 << 7)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -53,10 +53,10 @@ enum {
|
||||
* @brief Define ADXL345 sensitivity
|
||||
*/
|
||||
enum {
|
||||
ADXL345_RANGE_2G = 1, /**< +/- 2 g Full Scale Range */
|
||||
ADXL345_RANGE_4G = 2, /**< +/- 4 g Full Scale Range */
|
||||
ADXL345_RANGE_8G = 4, /**< +/- 8 g Full Scale Range */
|
||||
ADXL345_RANGE_16G = 8 /**< +/- 16 g Full Scale Range */
|
||||
ADXL345_RANGE_2G = 0, /**< +/- 2 g Full Scale Range */
|
||||
ADXL345_RANGE_4G = 1, /**< +/- 4 g Full Scale Range */
|
||||
ADXL345_RANGE_8G = 2, /**< +/- 8 g Full Scale Range */
|
||||
ADXL345_RANGE_16G = 3 /**< +/- 16 g Full Scale Range */
|
||||
};
|
||||
|
||||
/**
|
||||
@ -159,7 +159,7 @@ typedef struct {
|
||||
typedef struct {
|
||||
adxl345_params_t *params; /**< Device configuration */
|
||||
adxl345_interrupt_t interrupt; /**< Interrupts configuration */
|
||||
float scale_factor; /**< Scale factor for converting value to mg */
|
||||
int16_t scale_factor; /**< Scale factor for converting value to mg */
|
||||
} adxl345_t;
|
||||
|
||||
/**
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user