mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2025-12-24 05:53:49 +01:00
cpu/esp32: small sdkconfig cleanups
This commit is contained in:
Gunar Schorcht
parent
226f97cb01
commit
b5314db4a3
@ -30,7 +30,7 @@
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* ESP-IDF files. This avoids to update vendor code.
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*/
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#ifndef LD_FILE_GEN
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#include "soc/soc_caps.h"
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# include "soc/soc_caps.h"
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#endif
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/**
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@ -39,7 +39,7 @@
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* Determined with `git describe --tags` in `$ESP32_SDK_DIR`
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*/
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#if !defined(IDF_VER)
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#include "esp_idf_ver.h"
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# include "esp_idf_ver.h"
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#endif
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#ifndef DOXYGEN
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@ -51,27 +51,27 @@
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* can be overridden by an application specific configuration.
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*/
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#ifdef CONFIG_CONSOLE_UART_NUM
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#define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM
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# define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM
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#else
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#define CONFIG_ESP_CONSOLE_UART_NUM 0
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# define CONFIG_ESP_CONSOLE_UART_NUM 0
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#endif
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#define CONFIG_ESP_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE
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#define CONFIG_ESP_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE
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#define CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM CONFIG_ESP_CONSOLE_UART_NUM
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#define CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM CONFIG_ESP_CONSOLE_UART_NUM
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/**
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* Log output configuration (DO NOT CHANGE)
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*/
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#ifndef CONFIG_LOG_DEFAULT_LEVEL
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#define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL
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# define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL
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#endif
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#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL
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#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL
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/**
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* System specific configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_NEWLIB_NANO
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#define CONFIG_NEWLIB_NANO_FORMAT 1
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#if MODULE_NEWLIB_NANO
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# define CONFIG_NEWLIB_NANO_FORMAT 1
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#endif
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#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
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@ -82,10 +82,11 @@
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#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1
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#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584
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#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1
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#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
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#define CONFIG_ESP_TIMER_TASK_AFFINITY 0
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#define CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0 1
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#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
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#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
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#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
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#define CONFIG_APP_BUILD_BOOTLOADER 1
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@ -102,44 +103,32 @@
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/**
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* BLE driver configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_BLE
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#define CONFIG_BT_ENABLED 1
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#define CONFIG_BT_CONTROLLER_ENABLED 1
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#define CONFIG_BT_CONTROLLER_ONLY 1
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#define CONFIG_ESP_COEX_ENABLED 1
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#define CONFIG_ESP_WIFI_ENABLED 1 /* WiFi module has to be enabled */
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#define CONFIG_SOC_BT_SUPPORTED SOC_BT_SUPPORTED
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#define CONFIG_SOC_PM_SUPPORT_BT_PD SOC_PM_SUPPORT_BT_PD
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#define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP SOC_PM_SUPPORT_BT_WAKEUP
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#ifndef MODULE_ESP_WIFI_ANY
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#define CONFIG_ESP_PHY_ENABLED 1
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#define CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME 10
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#define CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME 50
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#define CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME 15
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#endif
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#else
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#define CONFIG_BT_ENABLED 0
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#if MODULE_ESP_BLE
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# define CONFIG_BT_ENABLED 1
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# define CONFIG_BT_CONTROLLER_ENABLED 1
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# define CONFIG_BT_CONTROLLER_ONLY 1
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# define CONFIG_SOC_BT_SUPPORTED SOC_BT_SUPPORTED
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# define CONFIG_SOC_PM_SUPPORT_BT_PD SOC_PM_SUPPORT_BT_PD
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# define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP SOC_PM_SUPPORT_BT_WAKEUP
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#endif
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/**
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* SPI RAM configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_SPI_RAM
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#define CONFIG_SPIRAM 1
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#define CONFIG_SPIRAM_TYPE_AUTO 1
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#define CONFIG_SPIRAM_SIZE -1
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#define CONFIG_SPIRAM_SPEED_40M 1
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#define CONFIG_SPIRAM_SPEED 40
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#define CONFIG_SPIRAM_BOOT_INIT 1
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#define CONFIG_SPIRAM_USE_MALLOC 1 /* using malloc requires QStaticQueue */
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#define CONFIG_SPIRAM_USE_CAPS_ALLOC 0 /* using cap instead of malloc */
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#define CONFIG_SPIRAM_MEMTEST 1
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#define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384
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#define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
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#define CONFIG_SOC_SPIRAM_SUPPORTED SOC_SPIRAM_SUPPORTED
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#define CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND 1
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#if MODULE_ESP_SPI_RAM
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# define CONFIG_SPIRAM 1
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# define CONFIG_SPIRAM_TYPE_AUTO 1
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# define CONFIG_SPIRAM_SIZE -1
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# define CONFIG_SPIRAM_SPEED_40M 1
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# define CONFIG_SPIRAM_SPEED 40
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# define CONFIG_SPIRAM_BOOT_INIT 1
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# define CONFIG_SPIRAM_USE_MALLOC 1 /* using malloc requires QStaticQueue */
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# define CONFIG_SPIRAM_USE_CAPS_ALLOC 0 /* using cap instead of malloc */
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# define CONFIG_SPIRAM_MEMTEST 1
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# define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384
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# define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
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# define CONFIG_SOC_SPIRAM_SUPPORTED SOC_SPIRAM_SUPPORTED
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# define CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND 1
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#endif
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/**
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@ -162,17 +151,17 @@
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/**
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* RTC Clock configuration
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*/
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#ifdef MODULE_ESP_RTC_TIMER_32K
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#define CONFIG_RTC_CLK_SRC_EXT_CRYS 1
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#if MODULE_ESP_RTC_TIMER_32K
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# define CONFIG_RTC_CLK_SRC_EXT_CRYS 1
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#else
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#define CONFIG_RTC_CLK_SRC_INT_RC 1
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# define CONFIG_RTC_CLK_SRC_INT_RC 1
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#endif
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/**
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* Ethernet driver configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_ETH
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#define CONFIG_ETH_ENABLED 1
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#if MODULE_ESP_ETH
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# define CONFIG_ETH_ENABLED 1
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#endif
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/**
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@ -182,101 +171,114 @@
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!defined(CONFIG_FLASHMODE_DIO) && \
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!defined(CONFIG_FLASHMODE_QOUT) && \
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!defined(CONFIG_FLASHMODE_QIO)
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#error "Flash mode not configured"
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# error "Flash mode not configured"
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#endif
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/**
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* Wi-Fi driver configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_WIFI_ANY
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#define CONFIG_CRYPTO_INTERNAL 1
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#define CONFIG_ESP_PHY_ENABLED 1
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#define CONFIG_ESP_WIFI_ENABLED 1
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#if MODULE_ESP_WIFI_ANY
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# define CONFIG_ESP_WIFI_ENABLED 1
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# define CONFIG_ESP_WIFI_AMPDU_RX_ENABLED 1
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# define CONFIG_ESP_WIFI_AMPDU_TX_ENABLED 1
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# define CONFIG_ESP_WIFI_AUTH_WPA2_PSK 1
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# define CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM 32
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# define CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM 32
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# define CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF 0
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# define CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER 1
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# define CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM 32
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# define CONFIG_ESP_WIFI_ENABLE_SAE_PK 0 /* default 1 for WPA3 */
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# define CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA 0 /* default 1 for WPA3 */
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# define CONFIG_ESP_WIFI_ENABLE_WPA3_SAE 0 /* default 1 for WPA3 */
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# define CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM 7
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# define CONFIG_ESP_WIFI_GMAC_SUPPORT 1
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# define CONFIG_ESP_WIFI_IRAM_OPT 0 /* default 1 */
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# define CONFIG_ESP_WIFI_MBEDTLS_CRYPTO 0 /* default 1 for WPA3 */
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# define CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT 0 /* default 1 for WPA3 */
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# define CONFIG_ESP_WIFI_MGMT_SBUF_NUM 32
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# define CONFIG_ESP_WIFI_NVS_ENABLED MODULE_ESP_IDF_NVS_FLASH
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# define CONFIG_ESP_WIFI_PW_ID ""
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# define CONFIG_ESP_WIFI_RX_BA_WIN 6
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# define CONFIG_ESP_WIFI_RX_IRAM_OPT 0 /* default 1 */
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# define CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF 5
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# define CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN 752
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# define CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE 1
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# define CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM 10
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# define CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER 1
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# define CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0 1
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# define CONFIG_ESP_WIFI_TX_BA_WIN 6
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# define CONFIG_ESP_WIFI_TX_BUFFER_TYPE 1
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# define CONFIG_CRYPTO_INTERNAL 1
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# if MODULE_ESP_WIFI_AP || MODULE_ESP_NOW
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# define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
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# endif
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# if MODULE_ESP_WIFI_ENTERPRISE
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# define CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT 1
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# endif
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#endif
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#define CONFIG_ESP_WIFI_AMPDU_RX_ENABLED 1
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#define CONFIG_ESP_WIFI_AMPDU_TX_ENABLED 1
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#define CONFIG_ESP_WIFI_AUTH_WPA2_PSK 1
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#define CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM 32
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#define CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM 32
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#define CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF 0
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#define CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER 1
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#define CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM 32
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#define CONFIG_ESP_WIFI_ENABLE_SAE_PK 0 /* default 1 for WPA3 */
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#define CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA 0 /* default 1 for WPA3 */
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#define CONFIG_ESP_WIFI_ENABLE_WPA3_SAE 0 /* default 1 for WPA3 */
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#define CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM 7
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#define CONFIG_ESP_WIFI_GMAC_SUPPORT 1
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#define CONFIG_ESP_WIFI_IRAM_OPT 0 /* default 1 */
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#define CONFIG_ESP_WIFI_MBEDTLS_CRYPTO 0 /* default 1 for WPA3 */
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#define CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT 0 /* default 1 for WPA3 */
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#define CONFIG_ESP_WIFI_MGMT_SBUF_NUM 32
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#define CONFIG_ESP_WIFI_PW_ID ""
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#define CONFIG_ESP_WIFI_RX_BA_WIN 6
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#define CONFIG_ESP_WIFI_RX_IRAM_OPT 0 /* default 1 */
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#define CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF 5
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#define CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME 10
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#define CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME 50
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#define CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME 15
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#define CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN 752
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#define CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE 1
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#define CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM 10
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#define CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER 1
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#define CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0 1
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#define CONFIG_ESP_WIFI_TX_BA_WIN 6
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#define CONFIG_ESP_WIFI_TX_BUFFER_TYPE 1
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#if defined(MODULE_ESP_IDF_NVS_FLASH) && !defined(CPU_FAM_ESP32C3)
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#define CONFIG_ESP_WIFI_NVS_ENABLED 1
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#endif
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#if defined(MODULE_ESP_WIFI_AP) || defined(MODULE_ESP_NOW)
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#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
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#endif
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#if defined(MODULE_ESP_WIFI_ENTERPRISE)
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#define CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT 1
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#endif
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#if defined(MODULE_ESP_BLE)
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#define CONFIG_ESP_COEX_SW_COEXIST_ENABLE 1
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#endif
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#endif
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/**
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* PHY configuration
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*/
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#if MODULE_ESP_IDF_NVS_ENABLED
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#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1
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#if SOC_PHY_SUPPORTED
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# define CONFIG_ESP_PHY_ENABLED 1
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# define CONFIG_ESP_PHY_CALIBRATION_MODE 0
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# define CONFIG_ESP_PHY_MAX_TX_POWER 20
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# define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
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# define CONFIG_ESP_PHY_RF_CAL_PARTIAL 1
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# if MODULE_ESP_IDF_NVS_FLASH
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# define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1
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# endif
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#endif
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#define CONFIG_ESP_PHY_MAX_TX_POWER 20
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#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
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/**
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* Coexist configuration (DO NOT CHANGE)
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*/
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#if !SOC_WIRELESS_HOST_SUPPORTED
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# define CONFIG_ESP_COEX_ENABLED 1
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# if CONFIG_ESP_WIFI_ENABLED && CONFIG_BT_ENABLED
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# define CONFIG_ESP_COEX_SW_COEXIST_ENABLE 1
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# endif
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# if 0
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/* TODO:
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* CONFIG_SW_COEXIST_ENABLE is deprecated but still used in code.
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* It is not defined in IDF sdkconfigs and does not work if defined. */
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# define CONFIG_SW_COEXIST_ENABLE 1
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# endif
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#endif /* !SOC_WIRELESS_HOST_SUPPORTED */
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/**
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* Flashpage configuration
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*/
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#ifndef CONFIG_ESP_FLASHPAGE_CAPACITY
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#ifdef MODULE_PERIPH_FLASHPAGE
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#if CONFIG_ESP_FLASHPAGE_CAPACITY_64K
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x10000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_128K
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x20000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_256K
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x40000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_512K
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_1M
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x100000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_2M
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x200000
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#else
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
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#endif
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#else /* MODULE_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE */
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x0
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#endif /* MODULE_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE */
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#if MODULE_PERIPH_FLASHPAGE
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# if CONFIG_ESP_FLASHPAGE_CAPACITY_64K
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# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x10000
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# elif CONFIG_ESP_FLASHPAGE_CAPACITY_128K
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# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x20000
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# elif CONFIG_ESP_FLASHPAGE_CAPACITY_256K
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# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x40000
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# elif CONFIG_ESP_FLASHPAGE_CAPACITY_512K
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# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
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# elif CONFIG_ESP_FLASHPAGE_CAPACITY_1M
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# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x100000
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# elif CONFIG_ESP_FLASHPAGE_CAPACITY_2M
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# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x200000
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# else
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# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
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# endif
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#else /* MODULE_PERIPH_FLASHPAGE */
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# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x0
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#endif /* MODULE_PERIPH_FLASHPAGE */
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#endif /* !CONFIG_ESP_FLASHPAGE_CAPACITY */
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@ -284,95 +286,85 @@
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* LCD driver configuration
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*/
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#if MODULE_ESP_IDF_LCD
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#ifndef CONFIG_LCD_DATA_BUF_SIZE
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#define CONFIG_LCD_DATA_BUF_SIZE 512
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#endif
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#define CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE CONFIG_LCD_DATA_BUF_SIZE
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# ifndef CONFIG_LCD_DATA_BUF_SIZE
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# define CONFIG_LCD_DATA_BUF_SIZE 512
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# endif
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# define CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE CONFIG_LCD_DATA_BUF_SIZE
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#endif
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/**
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* @brief Include ESP32x family specific SDK configuration
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*/
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#if defined(CPU_FAM_ESP32)
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#include "sdkconfig_esp32.h"
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# include "sdkconfig_esp32.h"
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#elif defined(CPU_FAM_ESP32C3)
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#include "sdkconfig_esp32c3.h"
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# include "sdkconfig_esp32c3.h"
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#elif defined(CPU_FAM_ESP32S2)
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#include "sdkconfig_esp32s2.h"
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# include "sdkconfig_esp32s2.h"
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#elif defined(CPU_FAM_ESP32S3)
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#include "sdkconfig_esp32s3.h"
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# include "sdkconfig_esp32s3.h"
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#else
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#error "ESP32x family implementation missing"
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# error "ESP32x family implementation missing"
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#endif
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#ifndef CONFIG_MMU_PAGE_SIZE
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#define CONFIG_MMU_PAGE_SIZE_64KB 1
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#define CONFIG_MMU_PAGE_SIZE 0x10000
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# define CONFIG_MMU_PAGE_SIZE_64KB 1
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# define CONFIG_MMU_PAGE_SIZE 0x10000
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#endif
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#ifndef CONFIG_FREERTOS_NUMBER_OF_CORES
|
||||
#define CONFIG_FREERTOS_NUMBER_OF_CORES 1
|
||||
# define CONFIG_FREERTOS_NUMBER_OF_CORES 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_ESP_DEBUG_OCDAWARE 1
|
||||
#define CONFIG_ESP_DEBUG_OCDAWARE 1
|
||||
|
||||
#define CONFIG_ADC_SUPPRESS_DEPRECATE_WARN 1
|
||||
#define CONFIG_ADC_SUPPRESS_DEPRECATE_WARN 1
|
||||
|
||||
#define CONFIG_HEAP_POISONING_DISABLED 1
|
||||
#define CONFIG_HEAP_TRACING_OFF 1
|
||||
#define CONFIG_LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP 1
|
||||
|
||||
#define CONFIG_ULP_COPROC_RESERVE_MEM 0
|
||||
#define CONFIG_ULP_COPROC_RESERVE_MEM 0
|
||||
|
||||
#ifdef SOC_RTC_MEM_SUPPORTED
|
||||
#define CONFIG_SOC_RTC_MEM_SUPPORTED 1
|
||||
# define CONFIG_SOC_RTC_MEM_SUPPORTED 1
|
||||
#endif
|
||||
#ifdef SOC_RTC_FAST_MEM_SUPPORTED
|
||||
#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
# define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#endif
|
||||
#ifdef SOC_RTC_SLOW_SUPPORTED
|
||||
#define CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED 1
|
||||
# define CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* SDMMC Host configuration
|
||||
*/
|
||||
#ifdef SOC_SDMMC_HOST_SUPPORTED
|
||||
|
||||
#define CONFIG_SOC_SDMMC_HOST_SUPPORTED SOC_SDMMC_HOST_SUPPORTED
|
||||
#define CONFIG_SOC_SDMMC_DELAY_PHASE_NUM SOC_SDMMC_DELAY_PHASE_NUM
|
||||
#define CONFIG_SOC_SDMMC_NUM_SLOTS SOC_SDMMC_NUM_SLOTS
|
||||
#define CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK SOC_SDMMC_SUPPORT_XTAL_CLOCK
|
||||
#define CONFIG_SOC_SDMMC_USE_GPIO_MATRIX SOC_SDMMC_USE_GPIO_MATRIX
|
||||
#define CONFIG_SOC_SDMMC_USE_IOMUX SOC_SDMMC_USE_IOMUX
|
||||
|
||||
# define CONFIG_SOC_SDMMC_HOST_SUPPORTED SOC_SDMMC_HOST_SUPPORTED
|
||||
# define CONFIG_SOC_SDMMC_DELAY_PHASE_NUM SOC_SDMMC_DELAY_PHASE_NUM
|
||||
# define CONFIG_SOC_SDMMC_NUM_SLOTS SOC_SDMMC_NUM_SLOTS
|
||||
# define CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK SOC_SDMMC_SUPPORT_XTAL_CLOCK
|
||||
# define CONFIG_SOC_SDMMC_USE_GPIO_MATRIX SOC_SDMMC_USE_GPIO_MATRIX
|
||||
# define CONFIG_SOC_SDMMC_USE_IOMUX SOC_SDMMC_USE_IOMUX
|
||||
#endif /* SOC_SDMMC_HOST_SUPPORTED */
|
||||
|
||||
/**
|
||||
* USB Serial/JTAG configuration
|
||||
*/
|
||||
#ifdef SOC_USB_SERIAL_JTAG_SUPPORTED
|
||||
|
||||
#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1
|
||||
|
||||
#define CONFIG_SOC_EFUSE_DIS_USB_JTAG SOC_EFUSE_DIS_USB_JTAG
|
||||
#define CONFIG_SOC_EFUSE_HARD_DIS_JTAG SOC_EFUSE_HARD_DIS_JTAG
|
||||
#define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG SOC_EFUSE_SOFT_DIS_JTAG
|
||||
|
||||
#ifndef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
|
||||
#define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
|
||||
#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED (CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG || \
|
||||
CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG)
|
||||
|
||||
#define CONFIG_USJ_ENABLE_USB_SERIAL_JTAG CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
|
||||
|
||||
# ifndef CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
|
||||
# define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1
|
||||
# endif
|
||||
# ifndef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
|
||||
# define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG 0
|
||||
# endif
|
||||
# define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED (CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG || \
|
||||
CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG)
|
||||
# define CONFIG_SOC_EFUSE_DIS_USB_JTAG SOC_EFUSE_DIS_USB_JTAG
|
||||
# define CONFIG_SOC_EFUSE_HARD_DIS_JTAG SOC_EFUSE_HARD_DIS_JTAG
|
||||
# define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG SOC_EFUSE_SOFT_DIS_JTAG
|
||||
# define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1
|
||||
# define CONFIG_USJ_ENABLE_USB_SERIAL_JTAG CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
|
||||
#endif /* SOC_USB_SERIAL_JTAG_SUPPORTED */
|
||||
|
||||
/* should be RIOT_APPLICATION but PROJECT_NAME must be less than 24 characters */
|
||||
|
||||
@ -34,28 +34,28 @@ extern "C" {
|
||||
|
||||
/* Mapping of Kconfig defines to the respective enumeration values */
|
||||
#if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_2
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
|
||||
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_5
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
|
||||
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_10
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
|
||||
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_20
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
|
||||
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_40
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
|
||||
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_80
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_160
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
|
||||
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_240
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Defines the CPU frequency [values = 2, 5, 10, 20, 40, 80, 160, 240]
|
||||
*/
|
||||
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
@ -63,13 +63,12 @@ extern "C" {
|
||||
/**
|
||||
* ESP32 specific RTC clock configuration
|
||||
*/
|
||||
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
|
||||
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
|
||||
|
||||
#ifdef MODULE_ESP_RTC_TIMER_32K
|
||||
#define CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_NONE 1
|
||||
#define CONFIG_RTC_XTAL_CAL_RETRY 1
|
||||
|
||||
#define CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES 5
|
||||
# define CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_NONE 1
|
||||
# define CONFIG_RTC_XTAL_CAL_RETRY 1
|
||||
# define CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
@ -128,79 +127,76 @@ extern "C" {
|
||||
* This is configured at the board level, defaulting to 40.
|
||||
*/
|
||||
#ifndef CONFIG_XTAL_FREQ
|
||||
#define CONFIG_XTAL_FREQ 0
|
||||
# define CONFIG_XTAL_FREQ 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* ESP32 specific SPI RAM configuration
|
||||
*/
|
||||
#ifdef MODULE_ESP_SPI_RAM
|
||||
#define CONFIG_D0WD_PSRAM_CLK_IO 17
|
||||
#define CONFIG_D0WD_PSRAM_CS_IO 16
|
||||
#define CONFIG_D2WD_PSRAM_CLK_IO 9
|
||||
#define CONFIG_D2WD_PSRAM_CS_IO 10
|
||||
#define CONFIG_PICO_PSRAM_CS_IO 10
|
||||
#define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1
|
||||
#define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8
|
||||
#define CONFIG_SPIRAM_CACHE_WORKAROUND 1
|
||||
#define CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 1
|
||||
#define CONFIG_SPIRAM_MODE_QUAD 1
|
||||
#define CONFIG_SPIRAM_SPIWP_SD3_PIN 7
|
||||
# define CONFIG_D0WD_PSRAM_CLK_IO 17
|
||||
# define CONFIG_D0WD_PSRAM_CS_IO 16
|
||||
# define CONFIG_D2WD_PSRAM_CLK_IO 9
|
||||
# define CONFIG_D2WD_PSRAM_CS_IO 10
|
||||
# define CONFIG_PICO_PSRAM_CS_IO 10
|
||||
# define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1
|
||||
# define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8
|
||||
# define CONFIG_SPIRAM_CACHE_WORKAROUND 1
|
||||
# define CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 1
|
||||
# define CONFIG_SPIRAM_MODE_QUAD 1
|
||||
# define CONFIG_SPIRAM_SPIWP_SD3_PIN 7
|
||||
#endif
|
||||
|
||||
/**
|
||||
* ESP32 specific ETH configuration
|
||||
*/
|
||||
#ifdef MODULE_ESP_ETH
|
||||
#define CONFIG_ETH_USE_ESP32_EMAC 1
|
||||
#define CONFIG_ETH_PHY_INTERFACE_RMII 1
|
||||
#define CONFIG_ETH_RMII_CLK_INPUT 1
|
||||
#define CONFIG_ETH_RMII_CLK_IN_GPIO 0
|
||||
#define CONFIG_ETH_DMA_BUFFER_SIZE 512
|
||||
#define CONFIG_ETH_DMA_RX_BUFFER_NUM 10
|
||||
#define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
|
||||
# define CONFIG_ETH_USE_ESP32_EMAC 1
|
||||
# define CONFIG_ETH_PHY_INTERFACE_RMII 1
|
||||
# define CONFIG_ETH_RMII_CLK_INPUT 1
|
||||
# define CONFIG_ETH_RMII_CLK_IN_GPIO 0
|
||||
# define CONFIG_ETH_DMA_BUFFER_SIZE 512
|
||||
# define CONFIG_ETH_DMA_RX_BUFFER_NUM 10
|
||||
# define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* ESP32 specific BLE driver configuration (DO NOT CHANGE)
|
||||
*/
|
||||
#ifdef MODULE_ESP_BLE
|
||||
#define CONFIG_BT_ALARM_MAX_NUM 50
|
||||
#define CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
|
||||
#define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
|
||||
#define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
|
||||
#define CONFIG_BTDM_BLE_CHAN_ASS_EN 1
|
||||
#define CONFIG_BTDM_BLE_DEFAULT_SCA_250PPM 1
|
||||
#define CONFIG_BTDM_BLE_PING_EN 1
|
||||
#define CONFIG_BTDM_BLE_SCAN_DUPL 1
|
||||
#define CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF 1
|
||||
#define CONFIG_BTDM_CTRL_BLE_MAX_CONN 3
|
||||
#define CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF 3
|
||||
#define CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF 0
|
||||
#define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF 0
|
||||
#define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 0
|
||||
#define CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED 1
|
||||
#define CONFIG_BTDM_CTRL_HCI_MODE_VHCI 1
|
||||
#define CONFIG_BTDM_CTRL_HLI 0 /* ESP-IDF uses 1 by default */
|
||||
#define CONFIG_BTDM_CTRL_LPCLK_SEL_MAIN_XTAL 1
|
||||
#define CONFIG_BTDM_CTRL_MODE_BLE_ONLY 1
|
||||
#define CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG 1
|
||||
#define CONFIG_BTDM_CTRL_MODEM_SLEEP 1
|
||||
#define CONFIG_BTDM_CTRL_PCM_FSYNCSHP_EFF 1
|
||||
#define CONFIG_BTDM_CTRL_PCM_POLAR_EFF 0
|
||||
#define CONFIG_BTDM_CTRL_PCM_ROLE_EFF 0
|
||||
#define CONFIG_BTDM_CTRL_PINNED_TO_CORE 0
|
||||
#define CONFIG_BTDM_CTRL_PINNED_TO_CORE_0 1
|
||||
#define CONFIG_BTDM_RESERVE_DRAM 0xe000 /* at least 0xdb5c, we use 56 kB */
|
||||
#define CONFIG_BTDM_SCAN_DUPL_CACHE_REFRESH_PERIOD 0
|
||||
#define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE 200
|
||||
#define CONFIG_BTDM_SCAN_DUPL_TYPE 0
|
||||
#define CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE 1
|
||||
|
||||
# define CONFIG_BT_ALARM_MAX_NUM 50
|
||||
# define CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
|
||||
# define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
|
||||
# define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
|
||||
# define CONFIG_BTDM_BLE_CHAN_ASS_EN 1
|
||||
# define CONFIG_BTDM_BLE_DEFAULT_SCA_250PPM 1
|
||||
# define CONFIG_BTDM_BLE_PING_EN 1
|
||||
# define CONFIG_BTDM_BLE_SCAN_DUPL 1
|
||||
# define CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF 1
|
||||
# define CONFIG_BTDM_CTRL_BLE_MAX_CONN 3
|
||||
# define CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF 3
|
||||
# define CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF 0
|
||||
# define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF 0
|
||||
# define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 0
|
||||
# define CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED 1
|
||||
# define CONFIG_BTDM_CTRL_HCI_MODE_VHCI 1
|
||||
# define CONFIG_BTDM_CTRL_HLI 0 /* ESP-IDF uses 1 by default */
|
||||
# define CONFIG_BTDM_CTRL_LPCLK_SEL_MAIN_XTAL 1
|
||||
# define CONFIG_BTDM_CTRL_MODE_BLE_ONLY 1
|
||||
# define CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG 1
|
||||
# define CONFIG_BTDM_CTRL_MODEM_SLEEP 1
|
||||
# define CONFIG_BTDM_CTRL_PCM_FSYNCSHP_EFF 1
|
||||
# define CONFIG_BTDM_CTRL_PCM_POLAR_EFF 0
|
||||
# define CONFIG_BTDM_CTRL_PCM_ROLE_EFF 0
|
||||
# define CONFIG_BTDM_CTRL_PINNED_TO_CORE 0
|
||||
# define CONFIG_BTDM_CTRL_PINNED_TO_CORE_0 1
|
||||
# define CONFIG_BTDM_RESERVE_DRAM 0xe000 /* at least 0xdb5c, we use 56 kB */
|
||||
# define CONFIG_BTDM_SCAN_DUPL_CACHE_REFRESH_PERIOD 0
|
||||
# define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE 200
|
||||
# define CONFIG_BTDM_SCAN_DUPL_TYPE 0
|
||||
# define CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE 1
|
||||
#else
|
||||
|
||||
#define CONFIG_BTDM_RESERVE_DRAM 0
|
||||
|
||||
# define CONFIG_BTDM_RESERVE_DRAM 0
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -34,26 +34,26 @@ extern "C" {
|
||||
|
||||
/* Mapping of Kconfig defines to the respective enumeration values */
|
||||
#if CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_2
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
|
||||
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_5
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
|
||||
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_10
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
|
||||
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_20
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
|
||||
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_40
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
|
||||
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_80
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_160
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Defines the CPU frequency [values = 2, 5, 10, 20, 40, 80, 160]
|
||||
*/
|
||||
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
@ -63,9 +63,6 @@ extern "C" {
|
||||
*/
|
||||
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
|
||||
|
||||
#ifdef MODULE_ESP_RTC_TIMER_32K
|
||||
#endif
|
||||
|
||||
/**
|
||||
* ESP32-C3 specific EFUSE configuration
|
||||
*/
|
||||
@ -108,50 +105,57 @@ extern "C" {
|
||||
/**
|
||||
* ESP32-C3 specific USB configuration
|
||||
*/
|
||||
#define CONFIG_ESP_PHY_ENABLE_USB 1
|
||||
#define CONFIG_ESP_PHY_ENABLE_USB 1
|
||||
|
||||
/**
|
||||
* ESP32-C3 BLE driver configuration (DO NOT CHANGE)
|
||||
*/
|
||||
#ifdef MODULE_ESP_BLE
|
||||
#define CONFIG_BT_ALARM_MAX_NUM 50
|
||||
#define CONFIG_BT_BLE_CCA_MODE 0
|
||||
#define CONFIG_BT_BLE_CCA_MODE_NONE 1
|
||||
#define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
|
||||
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
|
||||
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
|
||||
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
|
||||
#define CONFIG_BT_CTRL_BLE_MAX_ACT 10
|
||||
#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
|
||||
#define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
|
||||
#define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
|
||||
#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
|
||||
#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
|
||||
#define CONFIG_BT_CTRL_CHAN_ASS_EN 1
|
||||
#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
|
||||
#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
|
||||
#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 11
|
||||
#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P9 1
|
||||
#define CONFIG_BT_CTRL_DUPL_SCAN_CACHE_REFRESH_PERIOD 0
|
||||
#define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
|
||||
#define CONFIG_BT_CTRL_HCI_TL 1
|
||||
#define CONFIG_BT_CTRL_HCI_TL_EFF 1
|
||||
#define CONFIG_BT_CTRL_HW_CCA_EFF 0
|
||||
#define CONFIG_BT_CTRL_HW_CCA_VAL 20
|
||||
#define CONFIG_BT_CTRL_LE_PING_EN 1
|
||||
#define CONFIG_BT_CTRL_MODE_EFF 1
|
||||
#define CONFIG_BT_CTRL_PINNED_TO_CORE 0
|
||||
#define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1
|
||||
#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
|
||||
#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
|
||||
#define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
|
||||
#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
|
||||
#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
|
||||
#define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
|
||||
#define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
|
||||
#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
|
||||
#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
|
||||
#define CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
|
||||
# define CONFIG_BT_ALARM_MAX_NUM 50
|
||||
# define CONFIG_BT_BLE_CCA_MODE 0
|
||||
# define CONFIG_BT_BLE_CCA_MODE_NONE 1
|
||||
# define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
|
||||
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
|
||||
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
|
||||
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
|
||||
# define CONFIG_BT_CTRL_BLE_MAX_ACT 10
|
||||
# define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
|
||||
# define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
|
||||
# define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
|
||||
# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
|
||||
# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
|
||||
# define CONFIG_BT_CTRL_CHAN_ASS_EN 1
|
||||
# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
|
||||
# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
|
||||
# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 11
|
||||
# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P9 1
|
||||
# define CONFIG_BT_CTRL_DUPL_SCAN_CACHE_REFRESH_PERIOD 0
|
||||
# define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
|
||||
# define CONFIG_BT_CTRL_HCI_TL 1
|
||||
# define CONFIG_BT_CTRL_HCI_TL_EFF 1
|
||||
# define CONFIG_BT_CTRL_HW_CCA_EFF 0
|
||||
# define CONFIG_BT_CTRL_HW_CCA_VAL 20
|
||||
# define CONFIG_BT_CTRL_LE_PING_EN 1
|
||||
# define CONFIG_BT_CTRL_MODE_EFF 1
|
||||
# define CONFIG_BT_CTRL_PINNED_TO_CORE 0
|
||||
# define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1
|
||||
# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
|
||||
# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
|
||||
# define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
|
||||
# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
|
||||
# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
|
||||
# define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
|
||||
# define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
|
||||
# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
|
||||
# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
|
||||
# define CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
|
||||
#endif
|
||||
|
||||
/* According to the ESP32-C3 Errata Sheet ADC2 does not work correctly.
|
||||
* To use ADC2 and GPIO5 as ADC channel, CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
|
||||
* has to be set (default). */
|
||||
#ifndef CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
|
||||
# define CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 1
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -34,28 +34,28 @@ extern "C" {
|
||||
|
||||
/* Mapping of Kconfig defines to the respective enumeration values */
|
||||
#if CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_2
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
|
||||
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_5
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
|
||||
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_10
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
|
||||
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_20
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
|
||||
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_40
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
|
||||
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_80
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_160
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
|
||||
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_240
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Defines the CPU frequency [values = 2, 5, 10, 10, 40, 80, 160, 240]
|
||||
*/
|
||||
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
@ -66,7 +66,7 @@ extern "C" {
|
||||
#define CONFIG_RTC_CLK_CAL_CYCLES 576
|
||||
|
||||
#ifdef MODULE_ESP_RTC_TIMER_32K
|
||||
#define CONFIG_RTC_XTAL_CAL_RETRY 3
|
||||
# define CONFIG_RTC_XTAL_CAL_RETRY 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
@ -112,19 +112,19 @@ extern "C" {
|
||||
* ESP32-S2 specific USB configuration
|
||||
*/
|
||||
#ifdef MODULE_ESP_IDF_USB
|
||||
#define CONFIG_USB_OTG_SUPPORTED 1
|
||||
# define CONFIG_USB_OTG_SUPPORTED 1
|
||||
#endif
|
||||
/**
|
||||
* ESP32-S2 specific SPI RAM configuration
|
||||
*/
|
||||
#ifdef MODULE_ESP_SPI_RAM
|
||||
#ifdef MODULE_ESP_SPI_OCT
|
||||
#define CONFIG_SPIRAM_MODE_OCT 1
|
||||
#else
|
||||
#define CONFIG_SPIRAM_MODE_QUAD 1
|
||||
#endif
|
||||
#define CONFIG_SPIRAM_CLK_IO 30
|
||||
#define CONFIG_SPIRAM_CS_IO 26
|
||||
# ifdef MODULE_ESP_SPI_OCT
|
||||
# define CONFIG_SPIRAM_MODE_OCT 1
|
||||
# else
|
||||
# define CONFIG_SPIRAM_MODE_QUAD 1
|
||||
# endif
|
||||
# define CONFIG_SPIRAM_CLK_IO 30
|
||||
# define CONFIG_SPIRAM_CS_IO 26
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
||||
@ -34,28 +34,28 @@ extern "C" {
|
||||
|
||||
/* Mapping of Kconfig defines to the respective enumeration values */
|
||||
#if CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_2
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
|
||||
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_5
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
|
||||
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_10
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
|
||||
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_20
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
|
||||
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_40
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
|
||||
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_80
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_160
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
|
||||
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_240
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Defines the CPU frequency [values = 2, 5, 10, 10, 40, 80, 160, 240]
|
||||
*/
|
||||
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
|
||||
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
@ -63,10 +63,7 @@ extern "C" {
|
||||
/**
|
||||
* ESP32-S3 specific RTC clock configuration
|
||||
*/
|
||||
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
|
||||
|
||||
#ifdef MODULE_ESP_RTC_TIMER_32K
|
||||
#endif
|
||||
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
|
||||
|
||||
/**
|
||||
* ESP32-S3 specific EFUSE configuration
|
||||
@ -116,7 +113,7 @@ extern "C" {
|
||||
*/
|
||||
#define CONFIG_ESP_PHY_ENABLE_USB 1
|
||||
#ifdef MODULE_ESP_IDF_USB
|
||||
#define CONFIG_USB_OTG_SUPPORTED 1
|
||||
# define CONFIG_USB_OTG_SUPPORTED 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
@ -124,12 +121,12 @@ extern "C" {
|
||||
*/
|
||||
#ifdef MODULE_ESP_SPI_RAM
|
||||
#ifdef MODULE_ESP_SPI_OCT
|
||||
#define CONFIG_SPIRAM_MODE_OCT 1
|
||||
# define CONFIG_SPIRAM_MODE_OCT 1
|
||||
#else
|
||||
#define CONFIG_SPIRAM_MODE_QUAD 1
|
||||
# define CONFIG_SPIRAM_MODE_QUAD 1
|
||||
#endif
|
||||
#define CONFIG_SPIRAM_CLK_IO 30
|
||||
#define CONFIG_SPIRAM_CS_IO 26
|
||||
# define CONFIG_SPIRAM_CLK_IO 30
|
||||
# define CONFIG_SPIRAM_CS_IO 26
|
||||
#endif
|
||||
|
||||
/**
|
||||
@ -152,43 +149,43 @@ extern "C" {
|
||||
* ESP32-S3 BLE driver configuration (DO NOT CHANGE)
|
||||
*/
|
||||
#ifdef MODULE_ESP_BLE
|
||||
#define CONFIG_BT_ALARM_MAX_NUM 50
|
||||
#define CONFIG_BT_BLE_CCA_MODE 0
|
||||
#define CONFIG_BT_BLE_CCA_MODE_NONE 1
|
||||
#define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
|
||||
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
|
||||
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
|
||||
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
|
||||
#define CONFIG_BT_CTRL_BLE_MAX_ACT 10
|
||||
#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
|
||||
#define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
|
||||
#define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
|
||||
#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
|
||||
#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
|
||||
#define CONFIG_BT_CTRL_CHAN_ASS_EN 1
|
||||
#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
|
||||
#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
|
||||
#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 11
|
||||
#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P9 1
|
||||
#define CONFIG_BT_CTRL_DUPL_SCAN_CACHE_REFRESH_PERIOD 0
|
||||
#define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
|
||||
#define CONFIG_BT_CTRL_HCI_TL 1
|
||||
#define CONFIG_BT_CTRL_HCI_TL_EFF 1
|
||||
#define CONFIG_BT_CTRL_HW_CCA_EFF 0
|
||||
#define CONFIG_BT_CTRL_HW_CCA_VAL 20
|
||||
#define CONFIG_BT_CTRL_LE_PING_EN 1
|
||||
#define CONFIG_BT_CTRL_MODE_EFF 1
|
||||
#define CONFIG_BT_CTRL_PINNED_TO_CORE 0
|
||||
#define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1
|
||||
#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
|
||||
#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
|
||||
#define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
|
||||
#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
|
||||
#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
|
||||
#define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
|
||||
#define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
|
||||
#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
|
||||
#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
|
||||
# define CONFIG_BT_ALARM_MAX_NUM 50
|
||||
# define CONFIG_BT_BLE_CCA_MODE 0
|
||||
# define CONFIG_BT_BLE_CCA_MODE_NONE 1
|
||||
# define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
|
||||
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
|
||||
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
|
||||
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
|
||||
# define CONFIG_BT_CTRL_BLE_MAX_ACT 10
|
||||
# define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
|
||||
# define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
|
||||
# define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
|
||||
# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
|
||||
# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
|
||||
# define CONFIG_BT_CTRL_CHAN_ASS_EN 1
|
||||
# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
|
||||
# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
|
||||
# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 11
|
||||
# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P9 1
|
||||
# define CONFIG_BT_CTRL_DUPL_SCAN_CACHE_REFRESH_PERIOD 0
|
||||
# define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
|
||||
# define CONFIG_BT_CTRL_HCI_TL 1
|
||||
# define CONFIG_BT_CTRL_HCI_TL_EFF 1
|
||||
# define CONFIG_BT_CTRL_HW_CCA_EFF 0
|
||||
# define CONFIG_BT_CTRL_HW_CCA_VAL 20
|
||||
# define CONFIG_BT_CTRL_LE_PING_EN 1
|
||||
# define CONFIG_BT_CTRL_MODE_EFF 1
|
||||
# define CONFIG_BT_CTRL_PINNED_TO_CORE 0
|
||||
# define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1
|
||||
# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
|
||||
# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
|
||||
# define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
|
||||
# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
|
||||
# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
|
||||
# define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
|
||||
# define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
|
||||
# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
|
||||
# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user