diff --git a/cpu/stm32/include/periph/cpu_qdec.h b/cpu/stm32/include/periph/cpu_qdec.h
index 464219561b..cf5dbe3250 100644
--- a/cpu/stm32/include/periph/cpu_qdec.h
+++ b/cpu/stm32/include/periph/cpu_qdec.h
@@ -52,7 +52,10 @@ typedef struct {
     uint32_t rcc_mask;              /**< bit in clock enable register */
     qdec_chan_t chan[QDEC_CHAN];    /**< channel mapping, set to {GPIO_UNDEF, 0}
                                      *   if not used */
-#ifndef CPU_FAM_STM32F1
+#ifdef CPU_FAM_STM32F1
+    uint32_t remap;                 /**< AFIO remap mask to route periph to other
+                                         pins (or zero, if not needed) */
+#else
     gpio_af_t af;                   /**< alternate function used */
 #endif
     uint8_t bus;                    /**< APB bus */
diff --git a/cpu/stm32/periph/qdec.c b/cpu/stm32/periph/qdec.c
index 5deae8670e..69b2a91cf7 100644
--- a/cpu/stm32/periph/qdec.c
+++ b/cpu/stm32/periph/qdec.c
@@ -26,6 +26,9 @@
 #include "periph/qdec.h"
 #include "periph/gpio.h"
 
+#define ENABLE_DEBUG 0
+#include "debug.h"
+
 #ifdef QDEC_NUMOF
 
 /**
@@ -59,6 +62,15 @@ int32_t qdec_init(qdec_t qdec, qdec_mode_t mode, qdec_cb_t cb, void *arg)
     /* Power on the used timer */
     periph_clk_en(qdec_config[qdec].bus, qdec_config[qdec].rcc_mask);
 
+    /* Route peripheral to correct pins (STM32F1 only, other MCU families route
+     * pins to peripheral rather than peripheral to pins */
+#ifdef CPU_FAM_STM32F1
+    DEBUG("[qdec] AFIO->MAPR = 0x%" PRIx32 ", |= 0x%" PRIx32 "\n",
+          AFIO->MAPR, qdec_config[qdec].remap);
+    AFIO->MAPR |= qdec_config[qdec].remap;
+    DEBUG("[qdec] AFIO->MAPR = 0x%" PRIx32 "\n", AFIO->MAPR);
+#endif
+
     /* Reset configuration and CC channels */
     dev(qdec)->CR1 = 0;
     dev(qdec)->CR2 = 0;