diff --git a/cpu/stm32/Makefile.cmsis b/cpu/stm32/Makefile.cmsis
index 75a1db5a6d..d1cc6c8380 100644
--- a/cpu/stm32/Makefile.cmsis
+++ b/cpu/stm32/Makefile.cmsis
@@ -3,20 +3,20 @@ PKG_NAME=stm32cmsis
 # The package URL depends on the family of the target STM32
 PKG_URL=https://github.com/STMicroelectronics/cmsis_device_$(CPU_FAM)
 
-PKG_VERSION_f0=70d2069248b18e1cce13a035abc3230abe48754f  # v2.3.4
-PKG_VERSION_f1=2948138428461c0621fd53b269862c6e6bb043ce  # v4.3.1
-PKG_VERSION_f2=2415e69642f0d0afd256ec93fa4ba1ac010b348e  # v2.2.3
-PKG_VERSION_f3=aa2333a5313f65eb1a63bd876edb455197b38f91  # v2.3.4
-PKG_VERSION_f4=4cf505380bf123941fd485b1ae01c0747dca3792  # v2.6.4
-PKG_VERSION_f7=71be130bda6963d9d8ddbb71530477eadf0be740  # v1.2.5
-PKG_VERSION_g0=92ba98253dd6a748a04be14d3e436be3a35d6880  # v1.3.0
-PKG_VERSION_g4=7194c403cd5e4bd8bd4621a21d366d525e61b998  # v1.1.1
-PKG_VERSION_l0=78696f4f79cf51c8b32d0aa5c199a04f57ee4b27  # v1.9.0
-PKG_VERSION_l1=4a2f3cd6ea4bbc8e36daff0c7574b0fc1dfb7df7  # v2.3.0
-PKG_VERSION_l4=e442c72651e8d4757f6562acc14da949644944ce  # v1.6.1
-PKG_VERSION_l5=d922865fc0326a102c26211c44b8e42f52c1e53d  # v1.0.3
-PKG_VERSION_wb=44490652c88a513ec9a892c328db0246cf113987  # v1.4.0
-PKG_VERSION_wl=35631ff4d3a3cc361241af5f62190d0ea43bd65b  # v1.0.0
+PKG_VERSION_f0=8b86197c7ab77ad029c34dc73cf6d4a1e12327d8  # v2.3.6
+PKG_VERSION_f1=71ad5b3bf5cbb4d35cf8c8726c1b343871f0df0a  # v4.3.3
+PKG_VERSION_f2=694c49f696d359f57f23153ab7acf3ac1a43f663  # v2.2.5
+PKG_VERSION_f3=167eefd811de90a58c41e0a32071cdfecede389a  # v2.3.6
+PKG_VERSION_f4=6fe2c1f498feda34ee422720ff8b3bd1b4656145  # v2.6.7
+PKG_VERSION_f7=0abe04b1c85a848f1cec8dd4b2893dc8e3f07757  # v1.2.6
+PKG_VERSION_g0=051d85f2f5a9b5d67d2fbb4e97861b2e8ec1ef89  # v1.4.1
+PKG_VERSION_g4=3a3a8909720e37bece786f6011ba865951b369c8  # v1.2.1
+PKG_VERSION_l0=532d96973e7b2ae5546a2c88cb216429f74f5f5d  # v1.9.2
+PKG_VERSION_l1=1827333a7f7822282a6a46e4169596b5fb58cf61  # v2.3.2
+PKG_VERSION_l4=26ed4846f831f730d852507e178061053e522daf  # v1.7.1
+PKG_VERSION_l5=fcf61cd086e02c7a1cf7535ffe30622d1f5d36aa  # v1.0.4
+PKG_VERSION_wb=3a801574163338b562f56e7eb503a955818f1a56  # v1.9.0
+PKG_VERSION_wl=7bf548678b1132d829072ce86443c8036d538460  # v1.1.0
 
 PKG_VERSION=$(PKG_VERSION_$(CPU_FAM))
 PKG_LICENSE=Apache-2
diff --git a/cpu/stm32/dist/kconfig/gen_kconfig.py b/cpu/stm32/dist/kconfig/gen_kconfig.py
index c735baace6..34dcaf75bb 100755
--- a/cpu/stm32/dist/kconfig/gen_kconfig.py
+++ b/cpu/stm32/dist/kconfig/gen_kconfig.py
@@ -148,7 +148,7 @@ def main(args):
 
 
 PARSER = argparse.ArgumentParser()
-PARSER.add_argument("cpu_fam",
+PARSER.add_argument("cmsis_dir",
                     help="STM32 CMSIS directory")
 PARSER.add_argument("cpu_fam",
                     help="STM32 CPU Family")
diff --git a/cpu/stm32/kconfigs/g0/Kconfig.lines b/cpu/stm32/kconfigs/g0/Kconfig.lines
index d75559befe..ee8c570e99 100644
--- a/cpu/stm32/kconfigs/g0/Kconfig.lines
+++ b/cpu/stm32/kconfigs/g0/Kconfig.lines
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 Inria
+# Copyright (c) 2021 Inria
 #
 # This file is subject to the terms and conditions of the GNU Lesser
 # General Public License v2.1. See the file LICENSE in the top level
@@ -22,6 +22,18 @@ config CPU_LINE_STM32G041XX
     bool
     select CPU_FAM_G0
 
+config CPU_LINE_STM32G050XX
+    bool
+    select CPU_FAM_G0
+
+config CPU_LINE_STM32G051XX
+    bool
+    select CPU_FAM_G0
+
+config CPU_LINE_STM32G061XX
+    bool
+    select CPU_FAM_G0
+
 config CPU_LINE_STM32G070XX
     bool
     select CPU_FAM_G0
diff --git a/cpu/stm32/kconfigs/g0/Kconfig.models b/cpu/stm32/kconfigs/g0/Kconfig.models
index da7b8415e5..39a5cc45e0 100644
--- a/cpu/stm32/kconfigs/g0/Kconfig.models
+++ b/cpu/stm32/kconfigs/g0/Kconfig.models
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 Inria
+# Copyright (c) 2021 Inria
 #
 # This file is subject to the terms and conditions of the GNU Lesser
 # General Public License v2.1. See the file LICENSE in the top level
@@ -134,6 +134,90 @@ config CPU_MODEL_STM32G041Y8
     bool
     select CPU_LINE_STM32G041XX
 
+config CPU_MODEL_STM32G050C6
+    bool
+    select CPU_LINE_STM32G050XX
+
+config CPU_MODEL_STM32G050C8
+    bool
+    select CPU_LINE_STM32G050XX
+
+config CPU_MODEL_STM32G050F6
+    bool
+    select CPU_LINE_STM32G050XX
+
+config CPU_MODEL_STM32G050K6
+    bool
+    select CPU_LINE_STM32G050XX
+
+config CPU_MODEL_STM32G050K8
+    bool
+    select CPU_LINE_STM32G050XX
+
+config CPU_MODEL_STM32G051C6
+    bool
+    select CPU_LINE_STM32G051XX
+
+config CPU_MODEL_STM32G051C8
+    bool
+    select CPU_LINE_STM32G051XX
+
+config CPU_MODEL_STM32G051F6
+    bool
+    select CPU_LINE_STM32G051XX
+
+config CPU_MODEL_STM32G051F8
+    bool
+    select CPU_LINE_STM32G051XX
+
+config CPU_MODEL_STM32G051G6
+    bool
+    select CPU_LINE_STM32G051XX
+
+config CPU_MODEL_STM32G051G8
+    bool
+    select CPU_LINE_STM32G051XX
+
+config CPU_MODEL_STM32G051K6
+    bool
+    select CPU_LINE_STM32G051XX
+
+config CPU_MODEL_STM32G051K8
+    bool
+    select CPU_LINE_STM32G051XX
+
+config CPU_MODEL_STM32G061C6
+    bool
+    select CPU_LINE_STM32G061XX
+
+config CPU_MODEL_STM32G061C8
+    bool
+    select CPU_LINE_STM32G061XX
+
+config CPU_MODEL_STM32G061F6
+    bool
+    select CPU_LINE_STM32G061XX
+
+config CPU_MODEL_STM32G061F8
+    bool
+    select CPU_LINE_STM32G061XX
+
+config CPU_MODEL_STM32G061G6
+    bool
+    select CPU_LINE_STM32G061XX
+
+config CPU_MODEL_STM32G061G8
+    bool
+    select CPU_LINE_STM32G061XX
+
+config CPU_MODEL_STM32G061K6
+    bool
+    select CPU_LINE_STM32G061XX
+
+config CPU_MODEL_STM32G061K8
+    bool
+    select CPU_LINE_STM32G061XX
+
 config CPU_MODEL_STM32G070CB
     bool
     select CPU_LINE_STM32G070XX
@@ -202,6 +286,122 @@ config CPU_MODEL_STM32G081RB
     bool
     select CPU_LINE_STM32G081XX
 
+config CPU_MODEL_STM32G0B0CE
+    bool
+    select CPU_LINE_STM32G0B0XX
+
+config CPU_MODEL_STM32G0B0KE
+    bool
+    select CPU_LINE_STM32G0B0XX
+
+config CPU_MODEL_STM32G0B0RE
+    bool
+    select CPU_LINE_STM32G0B0XX
+
+config CPU_MODEL_STM32G0B0VE
+    bool
+    select CPU_LINE_STM32G0B0XX
+
+config CPU_MODEL_STM32G0B1CB
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1CC
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1CE
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1KB
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1KC
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1KE
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1MB
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1MC
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1ME
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1RB
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1RC
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1RE
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1VB
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1VC
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0B1VE
+    bool
+    select CPU_LINE_STM32G0B1XX
+
+config CPU_MODEL_STM32G0C1CC
+    bool
+    select CPU_LINE_STM32G0C1XX
+
+config CPU_MODEL_STM32G0C1CE
+    bool
+    select CPU_LINE_STM32G0C1XX
+
+config CPU_MODEL_STM32G0C1KC
+    bool
+    select CPU_LINE_STM32G0C1XX
+
+config CPU_MODEL_STM32G0C1KE
+    bool
+    select CPU_LINE_STM32G0C1XX
+
+config CPU_MODEL_STM32G0C1MC
+    bool
+    select CPU_LINE_STM32G0C1XX
+
+config CPU_MODEL_STM32G0C1ME
+    bool
+    select CPU_LINE_STM32G0C1XX
+
+config CPU_MODEL_STM32G0C1RC
+    bool
+    select CPU_LINE_STM32G0C1XX
+
+config CPU_MODEL_STM32G0C1RE
+    bool
+    select CPU_LINE_STM32G0C1XX
+
+config CPU_MODEL_STM32G0C1VC
+    bool
+    select CPU_LINE_STM32G0C1XX
+
+config CPU_MODEL_STM32G0C1VE
+    bool
+    select CPU_LINE_STM32G0C1XX
+
 
 # Configure CPU model
 config CPU_MODEL
@@ -236,6 +436,27 @@ config CPU_MODEL
     default "stm32g041k6" if CPU_MODEL_STM32G041K6
     default "stm32g041k8" if CPU_MODEL_STM32G041K8
     default "stm32g041y8" if CPU_MODEL_STM32G041Y8
+    default "stm32g050c6" if CPU_MODEL_STM32G050C6
+    default "stm32g050c8" if CPU_MODEL_STM32G050C8
+    default "stm32g050f6" if CPU_MODEL_STM32G050F6
+    default "stm32g050k6" if CPU_MODEL_STM32G050K6
+    default "stm32g050k8" if CPU_MODEL_STM32G050K8
+    default "stm32g051c6" if CPU_MODEL_STM32G051C6
+    default "stm32g051c8" if CPU_MODEL_STM32G051C8
+    default "stm32g051f6" if CPU_MODEL_STM32G051F6
+    default "stm32g051f8" if CPU_MODEL_STM32G051F8
+    default "stm32g051g6" if CPU_MODEL_STM32G051G6
+    default "stm32g051g8" if CPU_MODEL_STM32G051G8
+    default "stm32g051k6" if CPU_MODEL_STM32G051K6
+    default "stm32g051k8" if CPU_MODEL_STM32G051K8
+    default "stm32g061c6" if CPU_MODEL_STM32G061C6
+    default "stm32g061c8" if CPU_MODEL_STM32G061C8
+    default "stm32g061f6" if CPU_MODEL_STM32G061F6
+    default "stm32g061f8" if CPU_MODEL_STM32G061F8
+    default "stm32g061g6" if CPU_MODEL_STM32G061G6
+    default "stm32g061g8" if CPU_MODEL_STM32G061G8
+    default "stm32g061k6" if CPU_MODEL_STM32G061K6
+    default "stm32g061k8" if CPU_MODEL_STM32G061K8
     default "stm32g070cb" if CPU_MODEL_STM32G070CB
     default "stm32g070kb" if CPU_MODEL_STM32G070KB
     default "stm32g070rb" if CPU_MODEL_STM32G070RB
@@ -253,3 +474,32 @@ config CPU_MODEL
     default "stm32g081gb" if CPU_MODEL_STM32G081GB
     default "stm32g081kb" if CPU_MODEL_STM32G081KB
     default "stm32g081rb" if CPU_MODEL_STM32G081RB
+    default "stm32g0b0ce" if CPU_MODEL_STM32G0B0CE
+    default "stm32g0b0ke" if CPU_MODEL_STM32G0B0KE
+    default "stm32g0b0re" if CPU_MODEL_STM32G0B0RE
+    default "stm32g0b0ve" if CPU_MODEL_STM32G0B0VE
+    default "stm32g0b1cb" if CPU_MODEL_STM32G0B1CB
+    default "stm32g0b1cc" if CPU_MODEL_STM32G0B1CC
+    default "stm32g0b1ce" if CPU_MODEL_STM32G0B1CE
+    default "stm32g0b1kb" if CPU_MODEL_STM32G0B1KB
+    default "stm32g0b1kc" if CPU_MODEL_STM32G0B1KC
+    default "stm32g0b1ke" if CPU_MODEL_STM32G0B1KE
+    default "stm32g0b1mb" if CPU_MODEL_STM32G0B1MB
+    default "stm32g0b1mc" if CPU_MODEL_STM32G0B1MC
+    default "stm32g0b1me" if CPU_MODEL_STM32G0B1ME
+    default "stm32g0b1rb" if CPU_MODEL_STM32G0B1RB
+    default "stm32g0b1rc" if CPU_MODEL_STM32G0B1RC
+    default "stm32g0b1re" if CPU_MODEL_STM32G0B1RE
+    default "stm32g0b1vb" if CPU_MODEL_STM32G0B1VB
+    default "stm32g0b1vc" if CPU_MODEL_STM32G0B1VC
+    default "stm32g0b1ve" if CPU_MODEL_STM32G0B1VE
+    default "stm32g0c1cc" if CPU_MODEL_STM32G0C1CC
+    default "stm32g0c1ce" if CPU_MODEL_STM32G0C1CE
+    default "stm32g0c1kc" if CPU_MODEL_STM32G0C1KC
+    default "stm32g0c1ke" if CPU_MODEL_STM32G0C1KE
+    default "stm32g0c1mc" if CPU_MODEL_STM32G0C1MC
+    default "stm32g0c1me" if CPU_MODEL_STM32G0C1ME
+    default "stm32g0c1rc" if CPU_MODEL_STM32G0C1RC
+    default "stm32g0c1re" if CPU_MODEL_STM32G0C1RE
+    default "stm32g0c1vc" if CPU_MODEL_STM32G0C1VC
+    default "stm32g0c1ve" if CPU_MODEL_STM32G0C1VE
diff --git a/cpu/stm32/kconfigs/g4/Kconfig.lines b/cpu/stm32/kconfigs/g4/Kconfig.lines
index 48793383a5..8777b7b8a7 100644
--- a/cpu/stm32/kconfigs/g4/Kconfig.lines
+++ b/cpu/stm32/kconfigs/g4/Kconfig.lines
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 Inria
+# Copyright (c) 2021 Inria
 #
 # This file is subject to the terms and conditions of the GNU Lesser
 # General Public License v2.1. See the file LICENSE in the top level
@@ -38,6 +38,14 @@ config CPU_LINE_STM32G484XX
     bool
     select CPU_FAM_G4
 
+config CPU_LINE_STM32G491XX
+    bool
+    select CPU_FAM_G4
+
+config CPU_LINE_STM32G4A1XX
+    bool
+    select CPU_FAM_G4
+
 config CPU_LINE_STM32GBK1CB
     bool
     select CPU_FAM_G4
diff --git a/cpu/stm32/kconfigs/g4/Kconfig.models b/cpu/stm32/kconfigs/g4/Kconfig.models
index f771364b64..13d0837cd8 100644
--- a/cpu/stm32/kconfigs/g4/Kconfig.models
+++ b/cpu/stm32/kconfigs/g4/Kconfig.models
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 Inria
+# Copyright (c) 2021 Inria
 #
 # This file is subject to the terms and conditions of the GNU Lesser
 # General Public License v2.1. See the file LICENSE in the top level
@@ -114,6 +114,18 @@ config CPU_MODEL_STM32G473ME
     bool
     select CPU_LINE_STM32G473XX
 
+config CPU_MODEL_STM32G473PB
+    bool
+    select CPU_LINE_STM32G473XX
+
+config CPU_MODEL_STM32G473PC
+    bool
+    select CPU_LINE_STM32G473XX
+
+config CPU_MODEL_STM32G473PE
+    bool
+    select CPU_LINE_STM32G473XX
+
 config CPU_MODEL_STM32G473QB
     bool
     select CPU_LINE_STM32G473XX
@@ -174,6 +186,18 @@ config CPU_MODEL_STM32G474ME
     bool
     select CPU_LINE_STM32G474XX
 
+config CPU_MODEL_STM32G474PB
+    bool
+    select CPU_LINE_STM32G474XX
+
+config CPU_MODEL_STM32G474PC
+    bool
+    select CPU_LINE_STM32G474XX
+
+config CPU_MODEL_STM32G474PE
+    bool
+    select CPU_LINE_STM32G474XX
+
 config CPU_MODEL_STM32G474QB
     bool
     select CPU_LINE_STM32G474XX
@@ -218,6 +242,10 @@ config CPU_MODEL_STM32G483ME
     bool
     select CPU_LINE_STM32G483XX
 
+config CPU_MODEL_STM32G483PE
+    bool
+    select CPU_LINE_STM32G483XX
+
 config CPU_MODEL_STM32G483QE
     bool
     select CPU_LINE_STM32G483XX
@@ -238,6 +266,10 @@ config CPU_MODEL_STM32G484ME
     bool
     select CPU_LINE_STM32G484XX
 
+config CPU_MODEL_STM32G484PE
+    bool
+    select CPU_LINE_STM32G484XX
+
 config CPU_MODEL_STM32G484QE
     bool
     select CPU_LINE_STM32G484XX
@@ -250,6 +282,66 @@ config CPU_MODEL_STM32G484VE
     bool
     select CPU_LINE_STM32G484XX
 
+config CPU_MODEL_STM32G491CC
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G491CE
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G491KC
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G491KE
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G491MC
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G491ME
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G491RC
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G491RE
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G491VC
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G491VE
+    bool
+    select CPU_LINE_STM32G491XX
+
+config CPU_MODEL_STM32G4A1CE
+    bool
+    select CPU_LINE_STM32G4A1XX
+
+config CPU_MODEL_STM32G4A1KE
+    bool
+    select CPU_LINE_STM32G4A1XX
+
+config CPU_MODEL_STM32G4A1ME
+    bool
+    select CPU_LINE_STM32G4A1XX
+
+config CPU_MODEL_STM32G4A1RE
+    bool
+    select CPU_LINE_STM32G4A1XX
+
+config CPU_MODEL_STM32G4A1VE
+    bool
+    select CPU_LINE_STM32G4A1XX
+
 
 # Configure CPU model
 config CPU_MODEL
@@ -279,6 +371,9 @@ config CPU_MODEL
     default "stm32g473mb" if CPU_MODEL_STM32G473MB
     default "stm32g473mc" if CPU_MODEL_STM32G473MC
     default "stm32g473me" if CPU_MODEL_STM32G473ME
+    default "stm32g473pb" if CPU_MODEL_STM32G473PB
+    default "stm32g473pc" if CPU_MODEL_STM32G473PC
+    default "stm32g473pe" if CPU_MODEL_STM32G473PE
     default "stm32g473qb" if CPU_MODEL_STM32G473QB
     default "stm32g473qc" if CPU_MODEL_STM32G473QC
     default "stm32g473qe" if CPU_MODEL_STM32G473QE
@@ -294,6 +389,9 @@ config CPU_MODEL
     default "stm32g474mb" if CPU_MODEL_STM32G474MB
     default "stm32g474mc" if CPU_MODEL_STM32G474MC
     default "stm32g474me" if CPU_MODEL_STM32G474ME
+    default "stm32g474pb" if CPU_MODEL_STM32G474PB
+    default "stm32g474pc" if CPU_MODEL_STM32G474PC
+    default "stm32g474pe" if CPU_MODEL_STM32G474PE
     default "stm32g474qb" if CPU_MODEL_STM32G474QB
     default "stm32g474qc" if CPU_MODEL_STM32G474QC
     default "stm32g474qe" if CPU_MODEL_STM32G474QE
@@ -305,11 +403,28 @@ config CPU_MODEL
     default "stm32g474ve" if CPU_MODEL_STM32G474VE
     default "stm32g483ce" if CPU_MODEL_STM32G483CE
     default "stm32g483me" if CPU_MODEL_STM32G483ME
+    default "stm32g483pe" if CPU_MODEL_STM32G483PE
     default "stm32g483qe" if CPU_MODEL_STM32G483QE
     default "stm32g483re" if CPU_MODEL_STM32G483RE
     default "stm32g483ve" if CPU_MODEL_STM32G483VE
     default "stm32g484ce" if CPU_MODEL_STM32G484CE
     default "stm32g484me" if CPU_MODEL_STM32G484ME
+    default "stm32g484pe" if CPU_MODEL_STM32G484PE
     default "stm32g484qe" if CPU_MODEL_STM32G484QE
     default "stm32g484re" if CPU_MODEL_STM32G484RE
     default "stm32g484ve" if CPU_MODEL_STM32G484VE
+    default "stm32g491cc" if CPU_MODEL_STM32G491CC
+    default "stm32g491ce" if CPU_MODEL_STM32G491CE
+    default "stm32g491kc" if CPU_MODEL_STM32G491KC
+    default "stm32g491ke" if CPU_MODEL_STM32G491KE
+    default "stm32g491mc" if CPU_MODEL_STM32G491MC
+    default "stm32g491me" if CPU_MODEL_STM32G491ME
+    default "stm32g491rc" if CPU_MODEL_STM32G491RC
+    default "stm32g491re" if CPU_MODEL_STM32G491RE
+    default "stm32g491vc" if CPU_MODEL_STM32G491VC
+    default "stm32g491ve" if CPU_MODEL_STM32G491VE
+    default "stm32g4a1ce" if CPU_MODEL_STM32G4A1CE
+    default "stm32g4a1ke" if CPU_MODEL_STM32G4A1KE
+    default "stm32g4a1me" if CPU_MODEL_STM32G4A1ME
+    default "stm32g4a1re" if CPU_MODEL_STM32G4A1RE
+    default "stm32g4a1ve" if CPU_MODEL_STM32G4A1VE
diff --git a/cpu/stm32/kconfigs/l4/Kconfig.models b/cpu/stm32/kconfigs/l4/Kconfig.models
index 7461045cc7..f90014015c 100644
--- a/cpu/stm32/kconfigs/l4/Kconfig.models
+++ b/cpu/stm32/kconfigs/l4/Kconfig.models
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 Inria
+# Copyright (c) 2021 Inria
 #
 # This file is subject to the terms and conditions of the GNU Lesser
 # General Public License v2.1. See the file LICENSE in the top level
@@ -354,6 +354,10 @@ config CPU_MODEL_STM32L496VG
     bool
     select CPU_LINE_STM32L496XX
 
+config CPU_MODEL_STM32L496WG
+    bool
+    select CPU_LINE_STM32L496XX
+
 config CPU_MODEL_STM32L496ZE
     bool
     select CPU_LINE_STM32L496XX
@@ -651,6 +655,7 @@ config CPU_MODEL
     default "stm32l496rg" if CPU_MODEL_STM32L496RG
     default "stm32l496ve" if CPU_MODEL_STM32L496VE
     default "stm32l496vg" if CPU_MODEL_STM32L496VG
+    default "stm32l496wg" if CPU_MODEL_STM32L496WG
     default "stm32l496ze" if CPU_MODEL_STM32L496ZE
     default "stm32l496zg" if CPU_MODEL_STM32L496ZG
     default "stm32l4a6ag" if CPU_MODEL_STM32L4A6AG
diff --git a/cpu/stm32/kconfigs/wb/Kconfig.lines b/cpu/stm32/kconfigs/wb/Kconfig.lines
index b253d0db55..3d4c88de48 100644
--- a/cpu/stm32/kconfigs/wb/Kconfig.lines
+++ b/cpu/stm32/kconfigs/wb/Kconfig.lines
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 Inria
+# Copyright (c) 2021 Inria
 #
 # This file is subject to the terms and conditions of the GNU Lesser
 # General Public License v2.1. See the file LICENSE in the top level
@@ -10,6 +10,14 @@
 # See cpu/stm32/dist/kconfig/README.md for details
 
 # CPU lines
+config CPU_LINE_STM32WB10XX
+    bool
+    select CPU_FAM_WB
+
+config CPU_LINE_STM32WB15XX
+    bool
+    select CPU_FAM_WB
+
 config CPU_LINE_STM32WB30XX
     bool
     select CPU_FAM_WB
diff --git a/cpu/stm32/kconfigs/wb/Kconfig.models b/cpu/stm32/kconfigs/wb/Kconfig.models
index 651414ec3e..c48a2b7563 100644
--- a/cpu/stm32/kconfigs/wb/Kconfig.models
+++ b/cpu/stm32/kconfigs/wb/Kconfig.models
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 Inria
+# Copyright (c) 2021 Inria
 #
 # This file is subject to the terms and conditions of the GNU Lesser
 # General Public License v2.1. See the file LICENSE in the top level
@@ -10,6 +10,14 @@
 # See cpu/stm32/dist/kconfig/README.md for details
 
 # CPU models
+config CPU_MODEL_STM32WB10CC
+    bool
+    select CPU_LINE_STM32WB10XX
+
+config CPU_MODEL_STM32WB15CC
+    bool
+    select CPU_LINE_STM32WB15XX
+
 config CPU_MODEL_STM32WB30CE
     bool
     select CPU_LINE_STM32WB30XX
@@ -66,9 +74,15 @@ config CPU_MODEL_STM32WB55VY
     bool
     select CPU_LINE_STM32WB55XX
 
+config CPU_MODEL_STM32WB5MMG
+    bool
+    select CPU_LINE_STM32WB5MXX
+
 
 # Configure CPU model
 config CPU_MODEL
+    default "stm32wb10cc" if CPU_MODEL_STM32WB10CC
+    default "stm32wb15cc" if CPU_MODEL_STM32WB15CC
     default "stm32wb30ce" if CPU_MODEL_STM32WB30CE
     default "stm32wb35cc" if CPU_MODEL_STM32WB35CC
     default "stm32wb35ce" if CPU_MODEL_STM32WB35CE
@@ -83,3 +97,4 @@ config CPU_MODEL
     default "stm32wb55ve" if CPU_MODEL_STM32WB55VE
     default "stm32wb55vg" if CPU_MODEL_STM32WB55VG
     default "stm32wb55vy" if CPU_MODEL_STM32WB55VY
+    default "stm32wb5mmg" if CPU_MODEL_STM32WB5MMG
diff --git a/cpu/stm32/stmclk/stmclk_gx.c b/cpu/stm32/stmclk/stmclk_gx.c
index 72eed33fc2..ded9a44a0f 100644
--- a/cpu/stm32/stmclk/stmclk_gx.c
+++ b/cpu/stm32/stmclk/stmclk_gx.c
@@ -71,6 +71,10 @@
 #define RCC_CFGR_SW_HSE             (RCC_CFGR_SW_0)
 #define RCC_CFGR_SW_PLL             (RCC_CFGR_SW_1)
 
+#define RCC_CFGR_SWS_HSI            (0)
+#define RCC_CFGR_SWS_HSE            (RCC_CFGR_SWS_0)
+#define RCC_CFGR_SWS_PLL            (RCC_CFGR_SWS_1)
+
 #if CONFIG_CLOCK_HSISYS_DIV == 1
 #define CLOCK_HSI_DIV               (0)
 #elif CONFIG_CLOCK_HSISYS_DIV == 2