diff --git a/boards/nucleo-l4r5zi/Makefile b/boards/nucleo-l4r5zi/Makefile new file mode 100644 index 0000000000..4dd17b1d0c --- /dev/null +++ b/boards/nucleo-l4r5zi/Makefile @@ -0,0 +1,4 @@ +MODULE = board +DIRS = $(RIOTBOARD)/common/nucleo + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nucleo-l4r5zi/Makefile.dep b/boards/nucleo-l4r5zi/Makefile.dep new file mode 100644 index 0000000000..f41bf0f86b --- /dev/null +++ b/boards/nucleo-l4r5zi/Makefile.dep @@ -0,0 +1,3 @@ +FEATURES_REQUIRED += periph_lpuart + +include $(RIOTBOARD)/common/nucleo/Makefile.dep diff --git a/boards/nucleo-l4r5zi/Makefile.features b/boards/nucleo-l4r5zi/Makefile.features new file mode 100644 index 0000000000..7049d3fc2b --- /dev/null +++ b/boards/nucleo-l4r5zi/Makefile.features @@ -0,0 +1,16 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_lpuart +FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_rtt +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# Put other features for this board (in alphabetical order) +FEATURES_PROVIDED += riotboot + +# load the common Makefile.features for Nucleo boards +include $(RIOTBOARD)/common/nucleo144/Makefile.features + +-include $(RIOTCPU)/stm32l4/Makefile.features diff --git a/boards/nucleo-l4r5zi/Makefile.include b/boards/nucleo-l4r5zi/Makefile.include new file mode 100644 index 0000000000..97659f962a --- /dev/null +++ b/boards/nucleo-l4r5zi/Makefile.include @@ -0,0 +1,10 @@ +## the cpu to build for +export CPU = stm32l4 +export CPU_MODEL = stm32l4r5zi + +# stdio is available over st-link +PORT_LINUX ?= /dev/ttyACM0 +PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*))) + +# load the common Makefile.include for Nucleo boards +include $(RIOTBOARD)/common/nucleo144/Makefile.include diff --git a/boards/nucleo-l4r5zi/doc.txt b/boards/nucleo-l4r5zi/doc.txt new file mode 100644 index 0000000000..cf928feea7 --- /dev/null +++ b/boards/nucleo-l4r5zi/doc.txt @@ -0,0 +1,33 @@ +/** + * @defgroup boards_nucleo144-l4r5 STM32 Nucleo-L4R5ZI + * @ingroup boards_common_nucleo144 + * @brief Support for the STM32 Nucleo-L4R5ZI + +## Overview + +The Nucleo-L4R5ZI is a board from ST's Nucleo family supporting a ARM Cortex-M4 +STM32L4R5ZI microcontroller with 640Kb of RAM and 2Mb of ROM Flash. + +## Flashing the device + +The ST Nucleo-L4R5ZI board includes an on-board ST-LINK programmer and can be +flashed using OpenOCD. +@note The latest release of OpenOCD doesn't contain support for this board, +so a recent development version (including http://openocd.zylin.com/#/c/4777) +must be built from source to be able to flash this board. + +To flash this board, just use the following command: + +``` +make BOARD=nucleo-l4r5zi flash -C examples/hello-world +``` + +### STDIO + +STDIO is available via the ST-Link programmer. + +Use the `term` targed to open a terminal: + + make BOARD=nucleo-l4r5zi -C examples/hello-world term + + */ diff --git a/boards/nucleo-l4r5zi/include/periph_conf.h b/boards/nucleo-l4r5zi/include/periph_conf.h new file mode 100644 index 0000000000..093e5db5a2 --- /dev/null +++ b/boards/nucleo-l4r5zi/include/periph_conf.h @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2018 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo144-l4r5 + * @{ + * + * @file + * @brief Peripheral MCU configuration for the nucleo-l4r5zi board + * + * @author Alexandre Abadie + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "periph_cpu.h" +#include "cfg_i2c1_pb8_pb9.h" +#include "cfg_rtt_default.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock system configuration + * @{ + */ +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#define CLOCK_HSE (0) + +#ifndef CLOCK_LSE +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#define CLOCK_LSE (1) +#endif + +/* 0: enable MSI only if HSE isn't available + * 1: always enable MSI (e.g. if USB or RNG is used)*/ +#define CLOCK_MSI_ENABLE (1) + +#ifndef CLOCK_MSI_LSE_PLL +/* 0: disable Hardware auto calibration with LSE + * 1: enable Hardware auto calibration with LSE (PLL-mode) + * Same as with CLOCK_LSE above this defaults to 0 because LSE is + * mandatory for MSI/LSE-trimming to work */ +#define CLOCK_MSI_LSE_PLL (0) +#endif + +/* give the target core clock (HCLK) frequency [in Hz], maximum: 120MHz */ +#define CLOCK_CORECLOCK (120000000U) +/* PLL configuration: make sure your values are legit! */ +#define CLOCK_PLL_M (6) +#define CLOCK_PLL_N (30) +#define CLOCK_PLL_R (2) +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 +#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 +#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) +/** @} */ + +/** + * @name Timer configuration + * @{ + */ +static const timer_conf_t timer_config[] = { + { + .dev = TIM5, + .max = 0xffffffff, + .rcc_mask = RCC_APB1ENR1_TIM5EN, + .bus = APB1, + .irqn = TIM5_IRQn + } +}; + +#define TIMER_0_ISR isr_tim5 + +#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) +/** @} */ + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = LPUART1, + .rcc_mask = RCC_APB1ENR2_LPUART1EN, + .rx_pin = GPIO_PIN(PORT_G, 8), + .tx_pin = GPIO_PIN(PORT_G, 7), + .rx_af = GPIO_AF8, + .tx_af = GPIO_AF8, + .bus = APB12, + .irqn = LPUART1_IRQn, + .type = STM32_LPUART, + .clk_src = 0, + }, + { + .dev = USART3, + .rcc_mask = RCC_APB1ENR1_USART3EN, + .rx_pin = GPIO_PIN(PORT_D, 9), + .tx_pin = GPIO_PIN(PORT_D, 8), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART3_IRQn, + .type = STM32_USART, + .clk_src = 0, /* Use APB clock */ +#ifdef UART_USE_DMA + .dma_stream = 6, + .dma_chan = 4 +#endif + } +}; + +#define UART_0_ISR (isr_lpuart1) +#define UART_1_ISR (isr_usart3) + +#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) +/** @} */ + +/** + * @name SPI configuration + * + * @note The spi_divtable is auto-generated from + * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` + * @{ + */ +static const uint8_t spi_divtable[2][5] = { + { /* for APB1 @ 30000000Hz */ + 7, /* -> 117187Hz */ + 5, /* -> 468750Hz */ + 4, /* -> 937500Hz */ + 2, /* -> 3750000Hz */ + 1 /* -> 7500000Hz */ + }, + { /* for APB2 @ 60000000Hz */ + 7, /* -> 234375Hz */ + 6, /* -> 468750Hz */ + 5, /* -> 937500Hz */ + 3, /* -> 3750000Hz */ + 2 /* -> 7500000Hz */ + } +}; + +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_UNDEF, + .af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2 + } +}; + +#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */