diff --git a/cpu/msp430_common/vendor/README.md b/cpu/msp430_common/vendor/README.md new file mode 100644 index 0000000000..d66ea34327 --- /dev/null +++ b/cpu/msp430_common/vendor/README.md @@ -0,0 +1,9 @@ +The folder "msp430-gcc-support-files" has been imported from this URL: +https://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/exports/msp430-gcc-support-files-1.207.zip + +Then cleaned up to remove currently unused (by RIOT) files: + + $ _CPUS="$(git grep -o '^CPU_MODEL.=.*430.*$' | cut -d' ' -f 3 | sort -u)" + $ cd cpu/msp430_common/vendor/msp430-gcc-support-files/include + $ rm $(ls | grep -v -E '(msp430\.h|in430\.h|legacy\.h|iomacros\.h)' | \ + grep -v -F "${_CPUS}" ) diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/Revisions_Header.txt b/cpu/msp430_common/vendor/msp430-gcc-support-files/Revisions_Header.txt new file mode 100644 index 0000000000..f6b0903870 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/Revisions_Header.txt @@ -0,0 +1,660 @@ +Build 1.208 (GCC) +================= +08/29/2019 + +New device support: +------------------ +- None + +New features / changes: +----------------------- +- Added support for blinking LED example + +Bug fixes: +---------- +- Fixed GNU compiler build options +- Added missing ALIGN directives for .preinit/init/fini_array sections in GCC + linker command files + + +Build 1.207 (GCC) +================= +02/14/2019 + +New device support: +------------------ +- MSP430FR2676, MSP430FR2675, MSP430FR2476, MSP430FR2475 + +New features / changes: +----------------------- +- Updated definition of "__no_init" in in430.h + +Bug fixes: +---------- +- Corrected usage of NOPs in enable/disable interrupt macros in in430.h +- Removed invalid byte-access #defines (*_L/*_H) for DMA registers which only + allow word access from applicable device header files + + +Build 1.206 (GCC) +================= +07/26/2018 + +New device support: +------------------ +- None + +New features / changes: +----------------------- +- None + +Bug fixes: +---------- +- Added missing CPU errata compiler switches for MSP430FR2522, FR2512, FR2422 +- Removed invalid SYSRSTIV_FLLUL #define from MSP430F5/F6 device header files + + +Build 1.205 (GCC) +================= +04/23/2018 + +New device support: +------------------ +- MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153 + +New features / changes: +----------------------- +- None + +Bug fixes: +---------- +- Fixed another issue with .tinyram sections + + +Build 1.204 (GCC) +================= +12/21/2017 + +New device support: +------------------ +- MSP430FR6043, MSP430FR6041, MSP430FR5043, MSP430FR5041, + MSP430FR60431, MSP430FR50431 + +New features / changes: +----------------------- +- Separated release notes by toolchain (CCS, IAR, GCC) +- Added build version number to device XML and GNU compiler options file +- Minor update in legacy.h + +Bug fixes: +---------- +- Added missing .tinyram assignments in applicable linker command files + + +Build 1.203 +=========== +10/05/2017 + +New device support: +------------------ +- MSP430FR2522, MSP430FR2512, MSP430FR2422 + +New features / changes: +----------------------- +- Added -minrt option for GCC builds on devices with .5K of MAIN memory + +Bug fixes: +---------- +- Fixed name conflict in GCC linker files for FR2xx devices (INFO vs. INFOMEM) + + +Build 1.201 +=========== +06/28/2017 + +New device support: +------------------ +- MSP430FR2100, MSP430FR2000 + +New features / changes: +----------------------- +- Enabled MPU by default for FR57xx family devices +- Moved toolchain specific CCS device XML files to separate folder (targetdb/options) +- Changed GCC linker files to place .persistent section into lower FRAM +- Changed GCC linker files to properly split rodata, data, bss and text sections for + devices with large memory +- Added a workaround to enable GCC project builds for FR6047 family in CCS + +Bug fixes: +---------- +- Fixed offset definitions for port registers in header files for newer devices +- Fixed linker options in *_TI CCS device XML files using -D instead of --define +- Fixed CCS linker files using __LARGE_DATA_MODEL__ instead of __LARGE_CODE_MODEL__ +- Fixed inconsistencies in IAR SFR files for newer devices + + +Build 1.200 +=========== +05/31/2017 + +New device support: +------------------ +- MSP430FR6047, MSP430FR60471, MSP4306045, MSP430FR6037, MSP430FR60371, MSP430FR6035 + +New features / changes: +----------------------- +- Moved toolchain specific data from CCS device XMLs to separate _TI/_GNU XMLs +- Added list of memory boundary defines to header files for newer devices +- Changed CCS device XMLs to activate MPU by default for applicable devices + +Bug fixes: +---------- +- Removed invalid linker- and IDE integration files for "generic" devices +- Fixed RAM boundaries for MSP430F67641 and MSP430F67641A +- As of last support files release 7.2.4: Fixed wrong -mmcu flags in GCC specific device + XML files + +Known Limitations: +------------------ +- MPU is not enabled by default on FR57xx family devices + +========================================================================================== +Build 1.199 - 27.02.2017 +========================================================================================== +15.02.2017 Several updates in legacy.h +10.02.2017 Minor change for calculated interrupt vector definitions in IAR header files +07.02.2017 Added --near_data=none option for devices with RAM in memory > 0x10000 +06.02.2017 Fixed WDT base address and WDTCTL offset for FR4xx/FR2xx family devices +02.02.2017 Fixed an issue with INFO memory of FRAM devices being initialized on reset +02.02.2017 Fixed RAM boundaries for FR596x devices +02.02.2017 Changed I/O offset definitions to be relative to PORTx base for newer devices +13.12.2016 Enabled --gc-section compiler option for GCC builds +08.12.2016 Added mirrored RAM ranges to IAR menu files for applicable devices +========================================================================================== +Build 1.198 - 22.11.2016 +========================================================================================== +18.11.2016 Added missing ADCRES control bits for FR4xx/FR2xx devices +04.10.2016 Fixed offset definitions for certain registers in modules DIO and RTC +04.10.2016 Removed duplicate and invalid defines in header files for newer devices +04.10.2016 Fixed comment format in all header files for newer devices +26.09.2016 Moved CPU architecture define in header to account for in430.h dependencies +========================================================================================== +Build 1.194 - 27.09.2016 +========================================================================================== +26.09.2016 Updated in430.h for GCC and changed include order in GCC headers accordingly +========================================================================================== +release Package 19.09.2016 +========================================================================================== +06.09.2016 Removed invalid INFOMEM definitions in GCC linker files for fr2xx devices +06.09.2016 Updated legacy.h with old LEA_SC definitions +06.09.2016 Renamed LEA_SC module to LEA (including all registers and other definitions) +========================================================================================== +release Package 10.06.2016 +========================================================================================== +10.06.2016 Fixed typo in TI_COMPILER_VERSION check in CCS linker command files +01.06.2016 Corrected TLV address offsets in header files for G2xx/F2xx devices +========================================================================================== +release Package 20.05.2016 +========================================================================================== +19.05.2016 Added SIGNATURE sections in GCC linker command files +19.05.2016 Removed invalid code from generic GCC symbol files +18.05.2016 Added silicon errata switches to GCC compiler options in CCS device XMLs +02.05.2016 Added missing register separator comments in header files for newer MSP430s +28.04.2016 Changed format of multi-JSTATE bit modules in IAR menu files +12.04.2016 Added missing alternate register definitions (RTCCNT) for devices with RTC_C +========================================================================================== +release Package 11.04.2016 +========================================================================================== +11.04.2016 Added missing register definition macros to iomacros.h for GCC +08.04.2016 Added missing __MSP430_HAS_P*SEL__ definitions in F1xx/F2xx/F4xx headers +08.04.2016 Fixed typo in GCC linker files +05.04.2016 Fixed debug_line option in GCC linker files for smaller memory devices +========================================================================================== +release Package 31.03.2016 +========================================================================================== +31.03.2016 Fixed register definitions in GCC header files for FR5994 and FR2311 family +31.03.2016 Removed invalid header and support files for FR5994 family devices +========================================================================================== +release Package 30.03.2016 +========================================================================================== +30.03.2016 Changed 16bit access definitions for 32bit registers in GCC headers +29.03.2016 Enhanced DEFWL macro in IAR header files +29.03.2016 Corrected family definition for several FR2xx devices +29.03.2016 Removed unnecessary memory allocation in GCC linker files +29.03.2016 Added legacy definitions for FR413x BKMEM module +========================================================================================== +release Package 24.03.2016 +========================================================================================== +24.03.2016 Added ADC10PDIV_3 definition to resolve backwards compatibility issues +========================================================================================== +release Package 02.03.2016 +========================================================================================== +02.03.2016 Updated compiler workaround switches in CCS xml files +========================================================================================== +release Package 03.02.2016 +========================================================================================== +27.01.2016 Added: MSP430FR5994, MSP430FR5992, MSP430FR5964, MSP430FR5962, MSP430FR5894, + MSP430FR5892, MSP430FR5864, MSP430FR5862 + Added: MSP430FR2311, MSP430FR2310 +========================================================================================== +release Package 22.12.2015 +========================================================================================== +21.12.2015 Revised TAG_ADC10_1 values for applicable devices +16.12.2015 Added upper bss section in GCC linker files +15.12.2015 Removed invalid LCD definitions in CC430F514x header and support files +02.12.2015 Removed invalid ADC10PDIV_3 definitions for MSP430F5247 and related devices +02.12.2015 Added CAPTIVATE registers +16.11.2015 Added mhwmult option in the GNU Compiler option with the CCS device.xml files +09.11.2015 Fixed AESOP_2 and AESOP_3 comments mismatch and typo +09.11.2015 Added new GCC linker symbols files +09.11.2015 Added missing GCC linker option in CCS xml files +04.11.2015 CCS linker file memory regions split +========================================================================================== +release Package 29.10.2015 +========================================================================================== +28.10.2015 Added GCC linker heap memory support +========================================================================================== +release Package 27.10.2015 +========================================================================================== +20.10.2015 Updated CCS cmd file for IPE signature +14.10.2015 CCS linker file: fixed mapping of manual IPE configuration to right memory range +13.10.2015 updated a comment in the GCC linker file (.noinit) +13.10.2015 Restructured memory segment output for GCC linker files +13.10.2015 Added: MSP430FR2532, MSP430FR2533, MSP430FR2632, MSP430FR2633 +06.10.2015 Added INFO memory tag in IAR menu files +28.09.2015 Added BSL memory tag in IAR menu files +24.09.2015 Fixed mirrored RAM section for F6659 +15.09.2015 Changed IAR linker files to support MPU + IPE enabled together +15.09.2015 Corrected RAM memory range in lnk430f5359.xcl +14.09.2015 Removed 0x400 offset for IPEEND +14.09.2015 Add a .ipe_const section for constants in the IPE area in CCS linker files +14.09.2015 Added new IAR menu file features requested by IAR +14.09.2015 Added ram func feature for CCS +========================================================================================== +release Package 10.08.2015 +========================================================================================== +29.07.2015 Updated comments for USCI IV Bit definitions +========================================================================================== +release Package 17.07.2015 +========================================================================================== +17.07.2015 Fixed issue with BSL signature overlapping with interrupt vectors +16.07.2015 Fixed DMA issue in msp430frxx_6xxgeneric.h +14.07.2015 Add new definitions for Driverlib to differentiate SYSCFG2 bits +09.07.2015 F673xA: added missing 3rd SD24 Channel definition +29.06.2015 FR59xx and FR69xx: removed not available defines for SYSSNIV_SVS and SYSSNIV_ACCTEIFG +09.06.2015 F677x: fixed wrong define DMAxTSEL__USCIB3TX to DMAxTSEL__USCIA3TX +16.04.2015 added: RF430F5175 RF430F5155 RF430F5144 + added: MSP430FR5922 MSP430FR59221 +02.04.2015 Updated Segment size and calculation for FR57xx devices +========================================================================================== +release Package 25.03.2015 +========================================================================================== +13.03.2015 updated IAR xcl file format +18.02.2015 added Port 7 for MSP430F5239 +========================================================================================== +release Package 04.02.2015 +========================================================================================== +31.07.2014 LCD_B and LCD_C: added missing LCDBLKPRE_x and LCDDIV_x definitions +25.07.2014 G2xx1,G2xx2,G2xx3: added dummy TRAPINT_VECTOR interrupt vector as bugfix for USCI29 +16.07.2014 FR5xx/FR6xx: added define SYSRSTIV_ACCTEIFG +04.07.2014 ESI: Renamed bit ESIVCC2 to ESIVMIDEN, renamed bit ESIVSS to ESISHTSM +========================================================================================== +release Package 29.06.2014 +========================================================================================== +25.06.2014 Updated MPU inplementation into CCS Linker Command files +========================================================================================== +release Package 29.04.2014 +========================================================================================== +========================================================================================== +release Package 21.01.2014 +========================================================================================== +20.01.2014 Added Version Tag to Linker command files (identical to header files) + updated Signature defintion for CCS in linker command files + replaced MirrowRAMEnd with MirrowedRAMEnd + added MSP430F677xA devices +21.11.2013 MSP430F665x: Added USCI_A2 and USCI_B2 to DMA Trigger Table +20.11.2013 CCS: updated path for mathlib (4xx/5xx version) +11.11.2013 MSP430i20xx: fixed TAxIV_TAIFG definition +31.10.2013 MSP430G25xx: updated tags for TLV data +24.07.2013 MSP430FR59xx: Replaced NACCESSx with NWAITSx +23.07.2013 Module LDOPWR: fixed wrong define of LDOEN (from LDOOEN) +========================================================================================== +release Package 18.07.2013 +========================================================================================== +18.07.2013 CCS: added code template support +11.07.2013 removed not available PxDS Register definitions +========================================================================================== +release Package 09.07.2013 +========================================================================================== +09.07.2013 fixed identifier for debugger for MSP430i devices + added base address define for MSP430i devices +========================================================================================== +release Package 28.06.2013 +========================================================================================== +28.06.2013 added P7 to MSP430F5237 +10.06.2013 updated CCS linker command file for devices with MPU +10.06.2013 added MSP430I20xx and MSP430F525x devices +10.05.2013 MSP430F51x2 Fixed Typo PM_UCB0SOMO -> PM_UCB0SOMI +========================================================================================== +release Package 08.05.2013 +========================================================================================== +25.04.2013 fixed RAM size for MSP430G2102 and MSP430G2132 +========================================================================================== +release Package 19.03.2013 +========================================================================================== +15.03.2013 added RTCAE bits to RTC Module +11.03.2013 added DCOR to MSP430G2x55 devices + added 5xx style defintions for 2xx/4xx devices for TA0IV Register + fixed some typos in 5xx/6xx device with TimerA/B Interrupt vector definitions +10.02.2013 fixed size of Signature in FRAM Devices +========================================================================================== +release Package 31.01.2013 +========================================================================================== +31.01.2013 added MSP430G2755, MSP430G2855, MSP430G2955 +15.01.2013 changed defines to CapTouchIO from CapSenseIO to align with Users Guide +13.12.2012 Module name changed from RTC_CE to RTC_C +13.12.2012 CCS: Removed Legacy CCE V2 defines for Interrupt Vectors +14.11.2012 fixed missing UCA1 in FR57x3/7 +14.11.2012 FR56xx: fixed typo in SYSRSTIV_MPUSEG defintions + replaced COMP_B with COMP_E +========================================================================================== +release Package 13.11.2012 +========================================================================================== +24.10.2012 replaced define TBSSEL__TACLK with TBSSEL__TBCLK + ADC12B: fixed some Typos in ADC12 definitions (ADC10 was used before) +28.09.2012 USB devices: removed UPCS0 definition +========================================================================================== +release Package 25.09.2012 +========================================================================================== +25.09.2012 F677x: added Comp B to Interrupt Vector Table +21.09.2012 CCS: fixed issue with Board files under Linux +18.09.2012 added Signature Memory Segments to linker command file +12.09.2012 CCS: added USB RAM segment to linker command file +16.08.2012 added MSP430F6x5x and MSP430F5x5x devices + added MSP430F677x devices +17.07.2012 Updated PxSELC register address to offset 0x16 (instead of 0x10) + MSP430FR58xx/MSP430FR59xx replaced Comperator B with Comperator E +28.06.2012 Added TimerD Cal Tag for TLV Table (Devices with TimerD only) +13.06.2012 Fixed definitions for LCD: VLCD_13, VLCD_14, VLCD_3_26, VLCD_3_32 +13.06.2012 F67xx: Removed not available Bits SD24BINCHx +========================================================================================== +release Package 12.06.2012 +========================================================================================== +31.05.2012 added MSP430SL5438A +31.05.2012 CC430: removed not available Definitions: RF1AIFIV_RFRXIFG and RF1AIFIV_TFRXIFG +29.05.2012 FR596x devices +03.05.2012 MSP430FR57xx: removed not available PxDS Registers +========================================================================================== +release Package 30.03.2012 +========================================================================================== +30.03.2012 MSP430F53xx, MSP430F52xx and MSP430F67xx: removed RCRS7OFF +29.03.2012 MSP430F66xx: Added for defines for SYSSNIV_SVMLVLRIFG and SYSSNIV_SVMHVLRIFG +========================================================================================== +release Package 19.03.2012 +========================================================================================== +13.03.2012 added MSP430FR5969 +22.02.2012 CCS: removed --advice:power=all and --advice:power_severity=remark from XML file + changed default output format from coff to elf + added addtional data segments to linker command file +17.02.2012 Fixed UCBxSTAT display size in Debugger +15.02.2012 CCS: Moved Modules to msp430 sub folder +08.02.2012 CCS: updated MPU section:__mpusam = 0x7513; + updated MPU section:__mpuseg incremented by one if MemSize = x.5; +18.01.2012 CCS: added .data Section (required for SYSBIOS) +18.01.2012 CCS: changed pathes to use / instead of \ within XML files + CCS: package with unix style linefeeds added +13.01.2012 ADC12B removed ADC12DIF for odd Registers + added defines for TimerA Interrrupt vectors to Timer0_A +11.01.2012 Updated Comment for UC7BIT + Fixed Typo for MC__CONTINOUS (legacy definition for old define added) +========================================================================================== +release Package 14.12.2011 +========================================================================================== +13.12.2011 Updated all FR57xx device to have 1k RAM +28.11.2011 Fixed the G2230 and G2210 Menu file, leading to the device being reported as incorrect. +28.11.2011 Changed format of Interrupt Table in CCS V5 for ULP Advisor check + added Tag to CCS V5 XML files to enalbe ULP Advisor + removed -o0 option in CCS V4 +02.11.2011 updated FRAM error flag names for FR57xx + removed MPULOCK bit +20.10.2011 added More memory information (RAM2/ USB RAM / Mirrowed RAM) +14.10.2011 added TLV do MSP430XGenergic +========================================================================================== +release Package 01.10.2011 +========================================================================================== +29.09.2011 fixed Typo in comment of TASSEL0/1 +========================================================================================== +release Package 30.09.2011 +========================================================================================== +29.09.2011 added G2230 and the G2210 +========================================================================================== +15.09.2011 CCS: added Board Files +15.09.2011 IAR: added Tag if INFOA can be locked +========================================================================================== +release Package 10.08.2011 +========================================================================================== +03.08.2011 CCS: changed Stack and BSS location for FRAM devices to RAM +02.08.2011 added Devices: F522x, F643x. F533x, FR57xx; F67xx, CC430F614x, CC430F51xx +02.08.2011 added Devices: GenericX Device +03.08.2011 Fixed definition of RTCTEV__0000 and RTCTEV__1200 +========================================================================================== +release Package 24.06.2011 +========================================================================================== +09.06.2011 F663x: fixed wrong definitions in DMA Trigger 7 and 8 +========================================================================================== +release Package 09.06.2011 +========================================================================================== +09.06.2011 CPU BUG30 added for IAR + fixed comment of Peripheral section in IAR XCL files (5xx devices only) + added bit defintions for PAIN, PBIN,.. in XML and sfr files +25.05.2011 F663x and FR573: Fixed definition of RTCTEV__0000 and RTCTEV__1200 + Removed not availabe bits RTCMODE and RTCSSELx +12.05.2011 Fixed SD24 Tag for AFE253 (3 SD) devices +19.04.2011 Added base address of 5xx modules + added PxSELC registers for FRAM devices +07.04.2011 Fixed typo LCD_C (VLCD) definitions +29.03.2011 Fixed Memory (RAM) for Fg477 and F477 +16.03.2011 Fixed typo in comment of AFE devices + Removed SD24CONF0 in AFE devices + Removed caldata for 1MHZ and 16MHZ in AFE devices +========================================================================================== +release Package 08.03.2011 +========================================================================================== +07.03.2011 Set some FR57xx devices and all AFE device to released +07.03.2011 Updated FR57xx devices +04.03.2011 Added P3SEL for G2x53 +28.02.2011 IAR: added LPM5 Tag +09.12.2010 F530x: added PU (USB LDO) +08.12.2010 CCS: SD16: removed wrong entries in SD16 xml file +06.12.2010 USB: added alternate define USBIV - USBVECINT +16.11.2010 F51x2: Fixed PortMapper Definitons +========================================================================================== +release Package 11.11.2010 +========================================================================================== +11.11.2010 Removed Port4 in CC430F51xx devices +09.11.2010 Added Devices to release package: Kryton, AFE253, F532x, F532x, F534x, BT5xxx + updated PortU and USB defintions according to UG + changed access type to Timer A/B/D to word only +15.10.2010 Added FW428/FW429 +15.10.2010 A-Pool: added LCMP : A-POOL Latch comparator +========================================================================================== +release Package 23.09.2010 +========================================================================================== +14.09.2010 Fixed ADC12 (2xx/4xx) sfr file for ADC12MCTL + Removed DCOR bit in 5xx devices according UG +========================================================================================== +release Package 09.08.2010 +========================================================================================== +========================================================================================== +release Package 06.08.2010 +========================================================================================== +03.08.2010 Replaced PSSKEY with PMMKEY on some older 5xx devices + removed archiving of old Modules + added Device Prefix for Modules on non-released devices +========================================================================================== +release Package 28.07.2010 +========================================================================================== +27.07.2010 CCS-XML: added FilterString +26.07.2010 removed P7/P8/PA from F24x +26.07.2010 removed USCI 2/3 from 5418/5435/5437 + released device for Aug 2010 update +10.07.2010 set L092 to normal CPU instead of CPUX +05.07.2010 F471x3 Fixed Definition SD16MEMx, SD16IV +05.07.2010 F5xx: added missing & for ADC12MEM +05.07.2010 F663x removed EDI +========================================================================================== +release Package 17.06.2010 +========================================================================================== +16.06.2010 CCS: removed for inbetween release: Family Tag to XML files +11.06.2010 added support for GCC +10.06.2010 Updated some OSCCAP settings for the F47xx devices +09.06.2010 CCS: added Family Tag to XML files +07.06.2010 Updated F47126/F47127 source files (fixed missing DMA and RTC) +========================================================================================== +release Package 27.05.2010 +========================================================================================== +17.05.2010 CCS: added support Large/Small Memory Model in CCS cmd files +17.05.2010 added support for F438/F438 spins +========================================================================================== +release Package 17.05.2010 +========================================================================================== +17.05.2010 Removed L092EMU device +04.05.2010 released L092 devices +27.04.2010 added missing CG461x devices +15.03.2010 FE42x2: Fixed swapped IRMS and IRMS_2 definitions +========================================================================================== +release Package 16.03.2010 +========================================================================================== +15.03.2010 changed FETSTRING for F20x1 and F20x2 due to Argon Devices + added F6638 and F5510 to release package + updated EEM info for 5xx +09.03.2010 updated EEM info for many devices (F5xx with 3 BKPT , F4719x) +08.03.2010 IAR: replaced with "in430.h" as requested by A.Dannenberg /SDO +05.03.2010 5xx: Changed access type of DMAxSZ registers to word only +26.02.2010 removed XT2 from F5172 (int) +26.02.2010 updated PM on F5510 (int) +16.02.2010 updated comment in F41x2 +09.02.2010 CCS: replaced with "in430.h" as requested by A.Dannenberg /SDO +========================================================================================== +release Package 25.01.2010 (new update and with label applied) +========================================================================================== +25.01.2010 released F51x2 +25.01.2010 CCS: fixed bug in generation of XML files +========================================================================================== +release Package 16.12.2009 (new update and with label applied) +========================================================================================== +16.12.2009 updated defintions for KEY and PW (Password) as requested by system + PW register will cause PUC on wrong access / Key just ignores +08.12.2009 CCS: added support of ENUM generation in XML files +08.12.2009 Fixed typo in ADC10: SREF3 -> SREF2 +02.12.2009 CCS: fixed definitin of RESET_VECTOR for ASM +01.12.2009 added u-type castings for #defines into IAR header file +01.12.2009 some comment cleanup in ADC12/ADC10 done +26.11.2009 fixed typo WDTSSEL__SCMLK -> WDTSSEL__SMCLK +20.11.2009 Removed support for old TI ASM +16.11.2009 CC430: removed XT2DRIVE_x definitions +========================================================================================== +release Package 11.11.2009 (new update and with label applied) +========================================================================================== +10.11.2009 activated description field for CCS +========================================================================================== +release Package 10.11.2009 (new update and with label applied) +========================================================================================== +10.11.2009 F23x0: added dummy TRAPINT_VECTOR interrupt vector as bugfix for USCI29 +10.11.2009 implemented description field for CCS +10.11.2009 fixed type enalbe in several modules +========================================================================================== +release Package 04.11.2009 (new update and with label applied) +========================================================================================== +05.11.2009 changed grouping of Port Mapping +04.11.2009 updated TAG_ADC12_1 and TAG_ADC10_1 to 0x08 +03.11.2009 Fixed error in Port Mapping +29.10.2009 Added several new device spins +26.10.2009 MSP430FE42x2: Fixed swapped IRMS_2 definitions +30.09.2009 L092/C092: set CPU type to CPUX (pre request from Team) +29.09.2009 PMM: updated LOCKBAK to LOCKIO as shown in the UG LOCKBAK is used by RTC, added LOCKLPM5 +27.08.2009 IAR: added CPU Tag for menu files (BTT556) +24.08.2009 CCS: fixed error in ASM int generation for numbers below 10 +19.08.2009 fixed wrong Ram size for F5527 -> 0x3BFF +19.08.2009 removed Port D on F55xx devcie with 64 pin package +12.08.2009 added 51x1 to internal devices +========================================================================================== +release Package 20.07.2009 +========================================================================================== +10.08.2009 updated RAM sizes of CC430F6137/CC430F5137 +07.08.2009 updated header of CCS cmd files according to Andreas D. recommendations +05.08.2009 F55xx fixed type in DMA Trigger Defs +04.08.2009 implemented generation of dedicated header files +16.06.2009 implemented splitt of USCI modules +06.06.2009 made TAxIV and TBxIV registers for 5xx devices writeable + removed SYSARB register in 5xx SYS module +========================================================================================== +release Package 03.06.2009 / 07.06.2009 +========================================================================================== +03.06.2009 added CHECKSUM to IAR xcl files +23.06.2009 F5xx: xml files: USCI - I2C added missing bits +23.06.2009 F5xx: sfr files: MPY - added missing bits for MPYCTL and SUMEXT +05.05.2009 F5xx: Flash - removed some bits according to UG (EEI / EEIEX) +05.05.2009 CC430 devices: changed RTC_A_VECTOR to RTC_VECTOR +05.05.2009 CCS4: implemented ISR definition for ASM header files +05.05.2009 CCS4: split of CMD files implemented +04.05.2009 updated USB related header files +04.05.2009 updated MSP430.h files + special file for IAR +04.05.2009 IAR: replaced __IAR_SYSTEMS_ICC with __IAR_SYSTEMS_ICC__ +17.04.2009 IAR: replace 20 Bit register access with short access (only allowed in small memory model) +16.04.2009 Updated Comments for Comp.B (Ref Resitor divider and COMP_B_ISR Vector) + Removed XT1OFIFG from F552x and F551x +14.04.2009 added Target VCC to menu and xml files +========================================================================================== +release Package 25.03.2009 +========================================================================================== +23.03.2009 fixed error in Imagecraft files for 5xx devices +23.03.2009 replaced label for RSTWU/PORTWU to LPM5WU +23.03.2009 F41x2 removed LFXT1DIG +23.03.2009 Added TLV and DMA definitions for 5xx devices +16.03.2009 fixed wrong LCDMEM usage +26.02.2009 updated MSP430L092 +24.02.2009 removed SD16CONFx registers from SFR files +========================================================================================== +release Package 11.02.2009 +========================================================================================== +11.02.2009 released CC430 devices +09.02.2009 removed some XT2 bits from F41x2, + added comment to new release files F41x2, F471x6, F471x7, F47x, FG47x +04.02.2009 released F41x2 +30.01.2009 released F471x6, F471x7, F47x, FG47x +29.01.2009 fixed error in LCDB +20.01.2009 added byte alarm Register definitions for RTC in 5xx family +20.01.2009 F41x2 replaced LCD with LCDA +15.01.2009 5xx LCD_B fixed wrong alignment in #define LCDDIV__1 +18.12.2008 Added PMMLPM5xxx def to PMM +20.11.2008 Added and Tags +17.11.2008 Added msp430x241x.h +14.11.2008 Added RTxPS to F5xx devices + Added missing USCI registers F5xx devices + removed wrong byte definitions on *.cmd files (5xx) +06.11.2008 FE42x2 do not have HWMPY +05.11.2008 reduce RAM for CC430 by 2 to avoid bug with Stackpointer +30.10.2008 added additional FLL bits for F42x2 + moved INTVEC legacy defs of TB0 to module + added LFXT1DIG to some devices + +27.10.2008 changed name for TB to TB0 in F5xx/F6xx devices +23.10.2008 removed LCDB size bits + changed VLCDx bits from 8 to 9 + changed CCE printf default to minimal +15.10.2008 added CCS 4.0 package +13.10.2008 updated RAM config for F552x/F551x +10.10.2008 change style for V2 style interrupts defintion in CCE + removed unused defintions in PMM + updated RF defintions for CC1101 +04.09.2008 increased Stack/Heap size for large Ram Devices +03.09.2008 removed P10 from TC0701 + added USBPLL definitions +26.08.2008 stopped support for IAR_V1 and CCE V1, CCE V2 (files now longer will be updated) +26.08.2008 fixed wrong bit in UCS UCSUNLOCKHIST1 + added SD16XDIV2 to sfr files +25.08.2008 added Missing FCTL2 bits in sfr files. Updated FX47x files added Missing FCTL2 bits in sfr files. Updated FX47x files +20.08.2008 updated FG47x files with some OA bits updated FG47x files with some OA bits +19.08.2008 added F471x6 added F471x6 +31.07.2008 updated FG47x and F47x with SD16BUF updated FG47x and F47x with SD16BUF diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/cc430f6137.h b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/cc430f6137.h new file mode 100644 index 0000000000..718b3ab082 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/cc430f6137.h @@ -0,0 +1,4761 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* CC430x613x devices. +* +* Texas Instruments, Version 1.9 +* +* Rev. 1.0, First Release +* Rev. 1.1, added TLV definitions +* Rev. 1.2, added some more DMA Trigger definitions +* Rev. 1.3, fixed LCDMEM access +* Rev. 1.4, changed RTC_A_VECTOR to RTC_VECTOR +* Rev. 1.5, clean up of Flash section +* Rev. 1.6, Changed access type of DMAxSZ registers to word only +* Rev. 1.7 Changed access type of TimerA/B registers to word only +* Rev. 1.8 Removed not available Definitions: RF1AIFIV_RFRXIFG and RF1AIFIV_TFRXIFG +* Rev. 1.9 Removed not available Definitions: CRCDIRB and CRCRESR +* +* +********************************************************************/ + +#ifndef __cc430x613x +#define __cc430x613x + +#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */ +#define __MSP430F5XX_6XX_FAMILY__ + +#define __MSP430_HEADER_VERSION__ 1208 + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------*/ +/* PERIPHERAL FILE MAP */ +/*----------------------------------------------------------------------------*/ + +#define __MSP430_TI_HEADERS__ + +#include + + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __STDC__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" + +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif /* End #defines for C */ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + +/************************************************************ +* ADC12 PLUS +************************************************************/ +#define __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_ADC12_PLUS__ 0x0700 +#define ADC12_A_BASE __MSP430_BASEADDRESS_ADC12_PLUS__ + +sfr_w(ADC12CTL0); /* ADC12+ Control 0 */ +sfr_b(ADC12CTL0_L); /* ADC12+ Control 0 */ +sfr_b(ADC12CTL0_H); /* ADC12+ Control 0 */ +sfr_w(ADC12CTL1); /* ADC12+ Control 1 */ +sfr_b(ADC12CTL1_L); /* ADC12+ Control 1 */ +sfr_b(ADC12CTL1_H); /* ADC12+ Control 1 */ +sfr_w(ADC12CTL2); /* ADC12+ Control 2 */ +sfr_b(ADC12CTL2_L); /* ADC12+ Control 2 */ +sfr_b(ADC12CTL2_H); /* ADC12+ Control 2 */ +sfr_w(ADC12IFG); /* ADC12+ Interrupt Flag */ +sfr_b(ADC12IFG_L); /* ADC12+ Interrupt Flag */ +sfr_b(ADC12IFG_H); /* ADC12+ Interrupt Flag */ +sfr_w(ADC12IE); /* ADC12+ Interrupt Enable */ +sfr_b(ADC12IE_L); /* ADC12+ Interrupt Enable */ +sfr_b(ADC12IE_H); /* ADC12+ Interrupt Enable */ +sfr_w(ADC12IV); /* ADC12+ Interrupt Vector Word */ +sfr_b(ADC12IV_L); /* ADC12+ Interrupt Vector Word */ +sfr_b(ADC12IV_H); /* ADC12+ Interrupt Vector Word */ + +sfr_w(ADC12MEM0); /* ADC12 Conversion Memory 0 */ +sfr_b(ADC12MEM0_L); /* ADC12 Conversion Memory 0 */ +sfr_b(ADC12MEM0_H); /* ADC12 Conversion Memory 0 */ +sfr_w(ADC12MEM1); /* ADC12 Conversion Memory 1 */ +sfr_b(ADC12MEM1_L); /* ADC12 Conversion Memory 1 */ +sfr_b(ADC12MEM1_H); /* ADC12 Conversion Memory 1 */ +sfr_w(ADC12MEM2); /* ADC12 Conversion Memory 2 */ +sfr_b(ADC12MEM2_L); /* ADC12 Conversion Memory 2 */ +sfr_b(ADC12MEM2_H); /* ADC12 Conversion Memory 2 */ +sfr_w(ADC12MEM3); /* ADC12 Conversion Memory 3 */ +sfr_b(ADC12MEM3_L); /* ADC12 Conversion Memory 3 */ +sfr_b(ADC12MEM3_H); /* ADC12 Conversion Memory 3 */ +sfr_w(ADC12MEM4); /* ADC12 Conversion Memory 4 */ +sfr_b(ADC12MEM4_L); /* ADC12 Conversion Memory 4 */ +sfr_b(ADC12MEM4_H); /* ADC12 Conversion Memory 4 */ +sfr_w(ADC12MEM5); /* ADC12 Conversion Memory 5 */ +sfr_b(ADC12MEM5_L); /* ADC12 Conversion Memory 5 */ +sfr_b(ADC12MEM5_H); /* ADC12 Conversion Memory 5 */ +sfr_w(ADC12MEM6); /* ADC12 Conversion Memory 6 */ +sfr_b(ADC12MEM6_L); /* ADC12 Conversion Memory 6 */ +sfr_b(ADC12MEM6_H); /* ADC12 Conversion Memory 6 */ +sfr_w(ADC12MEM7); /* ADC12 Conversion Memory 7 */ +sfr_b(ADC12MEM7_L); /* ADC12 Conversion Memory 7 */ +sfr_b(ADC12MEM7_H); /* ADC12 Conversion Memory 7 */ +sfr_w(ADC12MEM8); /* ADC12 Conversion Memory 8 */ +sfr_b(ADC12MEM8_L); /* ADC12 Conversion Memory 8 */ +sfr_b(ADC12MEM8_H); /* ADC12 Conversion Memory 8 */ +sfr_w(ADC12MEM9); /* ADC12 Conversion Memory 9 */ +sfr_b(ADC12MEM9_L); /* ADC12 Conversion Memory 9 */ +sfr_b(ADC12MEM9_H); /* ADC12 Conversion Memory 9 */ +sfr_w(ADC12MEM10); /* ADC12 Conversion Memory 10 */ +sfr_b(ADC12MEM10_L); /* ADC12 Conversion Memory 10 */ +sfr_b(ADC12MEM10_H); /* ADC12 Conversion Memory 10 */ +sfr_w(ADC12MEM11); /* ADC12 Conversion Memory 11 */ +sfr_b(ADC12MEM11_L); /* ADC12 Conversion Memory 11 */ +sfr_b(ADC12MEM11_H); /* ADC12 Conversion Memory 11 */ +sfr_w(ADC12MEM12); /* ADC12 Conversion Memory 12 */ +sfr_b(ADC12MEM12_L); /* ADC12 Conversion Memory 12 */ +sfr_b(ADC12MEM12_H); /* ADC12 Conversion Memory 12 */ +sfr_w(ADC12MEM13); /* ADC12 Conversion Memory 13 */ +sfr_b(ADC12MEM13_L); /* ADC12 Conversion Memory 13 */ +sfr_b(ADC12MEM13_H); /* ADC12 Conversion Memory 13 */ +sfr_w(ADC12MEM14); /* ADC12 Conversion Memory 14 */ +sfr_b(ADC12MEM14_L); /* ADC12 Conversion Memory 14 */ +sfr_b(ADC12MEM14_H); /* ADC12 Conversion Memory 14 */ +sfr_w(ADC12MEM15); /* ADC12 Conversion Memory 15 */ +sfr_b(ADC12MEM15_L); /* ADC12 Conversion Memory 15 */ +sfr_b(ADC12MEM15_H); /* ADC12 Conversion Memory 15 */ +#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */ +#ifndef __STDC__ +#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ +#else +#define ADC12MEM ((volatile int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */ +#endif + +sfr_b(ADC12MCTL0); /* ADC12 Memory Control 0 */ +sfr_b(ADC12MCTL1); /* ADC12 Memory Control 1 */ +sfr_b(ADC12MCTL2); /* ADC12 Memory Control 2 */ +sfr_b(ADC12MCTL3); /* ADC12 Memory Control 3 */ +sfr_b(ADC12MCTL4); /* ADC12 Memory Control 4 */ +sfr_b(ADC12MCTL5); /* ADC12 Memory Control 5 */ +sfr_b(ADC12MCTL6); /* ADC12 Memory Control 6 */ +sfr_b(ADC12MCTL7); /* ADC12 Memory Control 7 */ +sfr_b(ADC12MCTL8); /* ADC12 Memory Control 8 */ +sfr_b(ADC12MCTL9); /* ADC12 Memory Control 9 */ +sfr_b(ADC12MCTL10); /* ADC12 Memory Control 10 */ +sfr_b(ADC12MCTL11); /* ADC12 Memory Control 11 */ +sfr_b(ADC12MCTL12); /* ADC12 Memory Control 12 */ +sfr_b(ADC12MCTL13); /* ADC12 Memory Control 13 */ +sfr_b(ADC12MCTL14); /* ADC12 Memory Control 14 */ +sfr_b(ADC12MCTL15); /* ADC12 Memory Control 15 */ +#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */ +#ifndef __STDC__ +#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ +#else +#define ADC12MCTL ((volatile char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */ +#endif + +/* ADC12CTL0 Control Bits */ +#define ADC12SC (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE (0x0004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE (0x0008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON (0x0010) /* ADC12 On/enable */ +#define ADC12REFON (0x0020) /* ADC12 Reference on */ +#define ADC12REF2_5V (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */ +#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON_L (0x0010) /* ADC12 On/enable */ +#define ADC12REFON_L (0x0020) /* ADC12 Reference on */ +#define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ +#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address Bit: 3 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY_L (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address Bit: 3 */ + +#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */ +#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */ +#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */ +#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */ + +#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */ + +#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */ + +#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */ +#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */ +#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */ +#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */ + +#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */ +#define ADC12CSTARTADD_1 (0x1000) /* ADC12 Conversion Start Address: 1 */ +#define ADC12CSTARTADD_2 (0x2000) /* ADC12 Conversion Start Address: 2 */ +#define ADC12CSTARTADD_3 (0x3000) /* ADC12 Conversion Start Address: 3 */ +#define ADC12CSTARTADD_4 (0x4000) /* ADC12 Conversion Start Address: 4 */ +#define ADC12CSTARTADD_5 (0x5000) /* ADC12 Conversion Start Address: 5 */ +#define ADC12CSTARTADD_6 (0x6000) /* ADC12 Conversion Start Address: 6 */ +#define ADC12CSTARTADD_7 (0x7000) /* ADC12 Conversion Start Address: 7 */ +#define ADC12CSTARTADD_8 (0x8000) /* ADC12 Conversion Start Address: 8 */ +#define ADC12CSTARTADD_9 (0x9000) /* ADC12 Conversion Start Address: 9 */ +#define ADC12CSTARTADD_10 (0xA000) /* ADC12 Conversion Start Address: 10 */ +#define ADC12CSTARTADD_11 (0xB000) /* ADC12 Conversion Start Address: 11 */ +#define ADC12CSTARTADD_12 (0xC000) /* ADC12 Conversion Start Address: 12 */ +#define ADC12CSTARTADD_13 (0xD000) /* ADC12 Conversion Start Address: 13 */ +#define ADC12CSTARTADD_14 (0xE000) /* ADC12 Conversion Start Address: 14 */ +#define ADC12CSTARTADD_15 (0xF000) /* ADC12 Conversion Start Address: 15 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */ +#define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */ +#define ADC12SR (0x0004) /* ADC12+ Sampling Rate */ +#define ADC12DF (0x0008) /* ADC12+ Data Format */ +#define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */ +#define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */ +#define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */ +#define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */ +#define ADC12DF_L (0x0008) /* ADC12+ Data Format */ +#define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */ + +#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */ +#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ +#define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ +#define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ +#define ADC12EOS (0x0080) /* ADC12 End of Sequence */ + +#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */ +#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */ +#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */ +#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */ +#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */ +#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */ +#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */ +#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */ +#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */ +#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */ +#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */ +#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */ +#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */ +#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */ +#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */ +#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */ + +#define ADC12SREF_0 (0x0000) /* ADC12 Select Reference 0 */ +#define ADC12SREF_1 (0x0010) /* ADC12 Select Reference 1 */ +#define ADC12SREF_2 (0x0020) /* ADC12 Select Reference 2 */ +#define ADC12SREF_3 (0x0030) /* ADC12 Select Reference 3 */ +#define ADC12SREF_4 (0x0040) /* ADC12 Select Reference 4 */ +#define ADC12SREF_5 (0x0050) /* ADC12 Select Reference 5 */ +#define ADC12SREF_6 (0x0060) /* ADC12 Select Reference 6 */ +#define ADC12SREF_7 (0x0070) /* ADC12 Select Reference 7 */ + +#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */ +#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */ + +#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */ +#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */ + +#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */ + +#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ +#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */ + +/************************************************************ +* AES Accelerator +************************************************************/ +#define __MSP430_HAS_AES__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_AES__ 0x09C0 +#define AES_BASE __MSP430_BASEADDRESS_AES__ + +sfr_w(AESACTL0); /* AES accelerator control register 0 */ +sfr_b(AESACTL0_L); /* AES accelerator control register 0 */ +sfr_b(AESACTL0_H); /* AES accelerator control register 0 */ +sfr_w(AESASTAT); /* AES accelerator status register */ +sfr_b(AESASTAT_L); /* AES accelerator status register */ +sfr_b(AESASTAT_H); /* AES accelerator status register */ +sfr_w(AESAKEY); /* AES accelerator key register */ +sfr_b(AESAKEY_L); /* AES accelerator key register */ +sfr_b(AESAKEY_H); /* AES accelerator key register */ +sfr_w(AESADIN); /* AES accelerator data in register */ +sfr_b(AESADIN_L); /* AES accelerator data in register */ +sfr_b(AESADIN_H); /* AES accelerator data in register */ +sfr_w(AESADOUT); /* AES accelerator data out register */ +sfr_b(AESADOUT_L); /* AES accelerator data out register */ +sfr_b(AESADOUT_H); /* AES accelerator data out register */ + +/* AESACTL0 Control Bits */ +#define AESOP0 (0x0001) /* AES Operation Bit: 0 */ +#define AESOP1 (0x0002) /* AES Operation Bit: 1 */ +#define AESSWRST (0x0080) /* AES Software Reset */ +#define AESRDYIFG (0x0100) /* AES ready interrupt flag */ +#define AESERRFG (0x0800) /* AES Error Flag */ +#define AESRDYIE (0x1000) /* AES ready interrupt enable*/ + +/* AESACTL0 Control Bits */ +#define AESOP0_L (0x0001) /* AES Operation Bit: 0 */ +#define AESOP1_L (0x0002) /* AES Operation Bit: 1 */ +#define AESSWRST_L (0x0080) /* AES Software Reset */ + +/* AESACTL0 Control Bits */ +#define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */ +#define AESERRFG_H (0x0008) /* AES Error Flag */ +#define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/ + +#define AESOP_0 (0x0000) /* AES Operation: Encrypt */ +#define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */ +#define AESOP_2 (0x0002) /* AES Operation: Generate first round Key */ +#define AESOP_3 (0x0003) /* AES Operation: Decrypt (first round Key) */ + +/* AESASTAT Control Bits */ +#define AESBUSY (0x0001) /* AES Busy */ +#define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */ +#define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESBUSY_L (0x0001) /* AES Busy */ +#define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */ + +/************************************************************ +* Comparator B +************************************************************/ +#define __MSP430_HAS_COMPB__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_COMPB__ 0x08C0 +#define COMP_B_BASE __MSP430_BASEADDRESS_COMPB__ + +sfr_w(CBCTL0); /* Comparator B Control Register 0 */ +sfr_b(CBCTL0_L); /* Comparator B Control Register 0 */ +sfr_b(CBCTL0_H); /* Comparator B Control Register 0 */ +sfr_w(CBCTL1); /* Comparator B Control Register 1 */ +sfr_b(CBCTL1_L); /* Comparator B Control Register 1 */ +sfr_b(CBCTL1_H); /* Comparator B Control Register 1 */ +sfr_w(CBCTL2); /* Comparator B Control Register 2 */ +sfr_b(CBCTL2_L); /* Comparator B Control Register 2 */ +sfr_b(CBCTL2_H); /* Comparator B Control Register 2 */ +sfr_w(CBCTL3); /* Comparator B Control Register 3 */ +sfr_b(CBCTL3_L); /* Comparator B Control Register 3 */ +sfr_b(CBCTL3_H); /* Comparator B Control Register 3 */ +sfr_w(CBINT); /* Comparator B Interrupt Register */ +sfr_b(CBINT_L); /* Comparator B Interrupt Register */ +sfr_b(CBINT_H); /* Comparator B Interrupt Register */ +sfr_w(CBIV); /* Comparator B Interrupt Vector Word */ + +/* CBCTL0 Control Bits */ +#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */ +#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */ + +/* CBCTL0 Control Bits */ +#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ + +/* CBCTL0 Control Bits */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */ + +#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */ +#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */ +#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */ +#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */ +#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */ +#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */ +#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */ +#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */ +#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */ +#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */ +#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */ +#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */ +#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */ +#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */ +#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */ +#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */ + +#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */ +#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */ +#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */ +#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */ +#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */ +#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */ +#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */ +#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */ +#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */ +#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */ +#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */ +#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */ +#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */ +#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */ +#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */ +#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */ + +/* CBCTL1 Control Bits */ +#define CBOUT (0x0001) /* Comp. B Output */ +#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */ +#define CBF (0x0004) /* Comp. B Enable Output Filter */ +#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */ +#define CBSHORT (0x0010) /* Comp. B Input Short */ +#define CBEX (0x0020) /* Comp. B Exchange Inputs */ +#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */ +#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */ +#define CBON (0x0400) /* Comp. B enable */ +#define CBMRVL (0x0800) /* Comp. B CBMRV Level */ +#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBOUT_L (0x0001) /* Comp. B Output */ +#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */ +#define CBF_L (0x0004) /* Comp. B Enable Output Filter */ +#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */ +#define CBSHORT_L (0x0010) /* Comp. B Input Short */ +#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */ +#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */ +#define CBON_H (0x0004) /* Comp. B enable */ +#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */ +#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */ +#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */ +#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */ +#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */ + +#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */ +#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */ +#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/ +#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */ + +/* CBCTL2 Control Bits */ +#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL (0x0020) /* Comp. B Reference select */ +#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */ +#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */ + +/* CBCTL2 Control Bits */ +#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL_L (0x0020) /* Comp. B Reference select */ +#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */ + +/* CBCTL2 Control Bits */ +#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */ + +#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */ +#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */ +#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */ +#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */ +#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */ +#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */ +#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */ +#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */ +#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */ +#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */ +#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */ +#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */ +#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */ +#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */ +#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */ +#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */ +#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */ +#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */ +#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */ +#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */ +#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */ +#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */ +#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */ +#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */ +#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */ +#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */ +#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */ +#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */ +#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */ +#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */ +#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */ +#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */ + +#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */ +#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */ +#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */ +#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */ + +#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */ +#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */ +#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */ +#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */ +#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */ +#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */ +#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */ +#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */ +#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */ +#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */ +#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */ +#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */ +#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */ +#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */ +#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */ +#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */ +#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */ +#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */ +#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */ +#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */ +#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */ +#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */ +#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */ +#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */ +#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */ +#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */ +#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */ +#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */ +#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */ +#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */ +#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */ +#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */ + +#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */ +#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */ +#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */ +#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */ + +#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ +#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */ + +#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ + +#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */ + +/* CBINT Control Bits */ +#define CBIFG (0x0001) /* Comp. B Interrupt Flag */ +#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +#define CBIE (0x0100) /* Comp. B Interrupt Enable */ +#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBINT Control Bits */ +#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */ +#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBINT Control Bits */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */ +#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBIV Definitions */ +#define CBIV_NONE (0x0000) /* No Interrupt pending */ +#define CBIV_CBIFG (0x0002) /* CBIFG */ +#define CBIV_CBIIFG (0x0004) /* CBIIFG */ + +/************************************************************ +* CC1101 Radio Interface +************************************************************/ +#define __MSP430_HAS_CC1101__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_CC1101__ 0x0F00 +#define RF1A_BASE __MSP430_BASEADDRESS_CC1101__ + +sfr_w(RF1AIFCTL0); /* Radio interface control register 0 */ +sfr_b(RF1AIFCTL0_L); /* Radio interface control register 0 */ +sfr_b(RF1AIFCTL0_H); /* Radio interface control register 0 */ +sfr_w(RF1AIFCTL1); /* Radio interface control register 1 */ +sfr_b(RF1AIFCTL1_L); /* Radio interface control register 1 */ +sfr_b(RF1AIFCTL1_H); /* Radio interface control register 1 */ +#define RF1AIFIFG RF1AIFCTL1_L /* Radio interface interrupt flag register */ +#define RF1AIFIE RF1AIFCTL1_H /* Radio interface interrupt enable register */ +sfr_w(RF1AIFCTL2); /* (Radio interface control register 2) */ +sfr_b(RF1AIFCTL2_L); /* (Radio interface control register 2) */ +sfr_b(RF1AIFCTL2_H); /* (Radio interface control register 2) */ +sfr_w(RF1AIFERR); /* Radio interface error flag register */ +sfr_b(RF1AIFERR_L); /* Radio interface error flag register */ +sfr_b(RF1AIFERR_H); /* Radio interface error flag register */ +sfr_w(RF1AIFERRV); /* Radio interface error vector word register */ +sfr_b(RF1AIFERRV_L); /* Radio interface error vector word register */ +sfr_b(RF1AIFERRV_H); /* Radio interface error vector word register */ +sfr_w(RF1AIFIV); /* Radio interface interrupt vector word register */ +sfr_b(RF1AIFIV_L); /* Radio interface interrupt vector word register */ +sfr_b(RF1AIFIV_H); /* Radio interface interrupt vector word register */ +sfr_w(RF1AINSTRW); /* Radio instruction word register */ +sfr_b(RF1AINSTRW_L); /* Radio instruction word register */ +sfr_b(RF1AINSTRW_H); /* Radio instruction word register */ +#define RF1ADINB RF1AINSTRW_L /* Radio instruction byte register */ +#define RF1AINSTRB RF1AINSTRW_H /* Radio byte data in register */ +sfr_w(RF1AINSTR1W); /* Radio instruction 1-byte register with autoread */ +sfr_b(RF1AINSTR1W_L); /* Radio instruction 1-byte register with autoread */ +sfr_b(RF1AINSTR1W_H); /* Radio instruction 1-byte register with autoread */ +#define RF1AINSTR1B RF1AINSTR1W_H /* Radio instruction 1-byte register with autoread */ +sfr_w(RF1AINSTR2W); /* Radio instruction 2-byte register with autoread */ +sfr_b(RF1AINSTR2W_L); /* Radio instruction 2-byte register with autoread */ +sfr_b(RF1AINSTR2W_H); /* Radio instruction 2-byte register with autoread */ +#define RF1AINSTR2B RF1AINSTR1W_H /* Radio instruction 2-byte register with autoread */ +sfr_w(RF1ADINW); /* Radio word data in register */ +sfr_b(RF1ADINW_L); /* Radio word data in register */ +sfr_b(RF1ADINW_H); /* Radio word data in register */ + +sfr_w(RF1ASTAT0W); /* Radio status word register without auto-read */ +sfr_b(RF1ASTAT0W_L); /* Radio status word register without auto-read */ +sfr_b(RF1ASTAT0W_H); /* Radio status word register without auto-read */ +#define RF1ADOUT0B RF1ASTAT0W_L /* Radio byte data out register without auto-read */ +#define RF1ASTAT0B RF1ASTAT0W_H /* Radio status byte register without auto-read */ +#define RF1ASTATW RF1ASTAT0W /* Radio status word register without auto-read */ +#define RF1ADOUTB RF1ASTAT0W_L /* Radio byte data out register without auto-read */ +#define RF1ASTATB RF1ASTAT0W_H /* Radio status byte register without auto-read */ +sfr_w(RF1ASTAT1W); /* Radio status word register with 1-byte auto-read */ +sfr_b(RF1ASTAT1W_L); /* Radio status word register with 1-byte auto-read */ +sfr_b(RF1ASTAT1W_H); /* Radio status word register with 1-byte auto-read */ +#define RF1ADOUT1B RF1ASTAT1W_L /* Radio byte data out register with 1-byte auto-read */ +#define RF1ASTAT1B RF1ASTAT1W_H /* Radio status byte register with 1-byte auto-read */ +sfr_w(RF1ASTAT2W); /* Radio status word register with 2-byte auto-read */ +sfr_b(RF1ASTAT2W_L); /* Radio status word register with 2-byte auto-read */ +sfr_b(RF1ASTAT2W_H); /* Radio status word register with 2-byte auto-read */ +#define RF1ADOUT2B RF1ASTAT2W_L /* Radio byte data out register with 2-byte auto-read */ +#define RF1ASTAT2B RF1ASTAT2W_H /* Radio status byte register with 2-byte auto-read */ +sfr_w(RF1ADOUT0W); /* Radio core word data out register without auto-read */ +sfr_b(RF1ADOUT0W_L); /* Radio core word data out register without auto-read */ +sfr_b(RF1ADOUT0W_H); /* Radio core word data out register without auto-read */ +#define RF1ADOUTW RF1ADOUT0W /* Radio core word data out register without auto-read */ +#define RF1ADOUTW_L RF1ADOUT0W_L /* Radio core word data out register without auto-read */ +#define RF1ADOUTW_H RF1ADOUT0W_H /* Radio core word data out register without auto-read */ +sfr_w(RF1ADOUT1W); /* Radio core word data out register with 1-byte auto-read */ +sfr_b(RF1ADOUT1W_L); /* Radio core word data out register with 1-byte auto-read */ +sfr_b(RF1ADOUT1W_H); /* Radio core word data out register with 1-byte auto-read */ +sfr_w(RF1ADOUT2W); /* Radio core word data out register with 2-byte auto-read */ +sfr_b(RF1ADOUT2W_L); /* Radio core word data out register with 2-byte auto-read */ +sfr_b(RF1ADOUT2W_H); /* Radio core word data out register with 2-byte auto-read */ +sfr_w(RF1AIN); /* Radio core signal input register */ +sfr_b(RF1AIN_L); /* Radio core signal input register */ +sfr_b(RF1AIN_H); /* Radio core signal input register */ +sfr_w(RF1AIFG); /* Radio core interrupt flag register */ +sfr_b(RF1AIFG_L); /* Radio core interrupt flag register */ +sfr_b(RF1AIFG_H); /* Radio core interrupt flag register */ +sfr_w(RF1AIES); /* Radio core interrupt edge select register */ +sfr_b(RF1AIES_L); /* Radio core interrupt edge select register */ +sfr_b(RF1AIES_H); /* Radio core interrupt edge select register */ +sfr_w(RF1AIE); /* Radio core interrupt enable register */ +sfr_b(RF1AIE_L); /* Radio core interrupt enable register */ +sfr_b(RF1AIE_H); /* Radio core interrupt enable register */ +sfr_w(RF1AIV); /* Radio core interrupt vector word register */ +sfr_b(RF1AIV_L); /* Radio core interrupt vector word register */ +sfr_b(RF1AIV_H); /* Radio core interrupt vector word register */ +sfr_w(RF1ARXFIFO); /* Direct receive FIFO access register */ +sfr_b(RF1ARXFIFO_L); /* Direct receive FIFO access register */ +sfr_b(RF1ARXFIFO_H); /* Direct receive FIFO access register */ +sfr_w(RF1ATXFIFO); /* Direct transmit FIFO access register */ +sfr_b(RF1ATXFIFO_L); /* Direct transmit FIFO access register */ +sfr_b(RF1ATXFIFO_H); /* Direct transmit FIFO access register */ + +/* RF1AIFCTL0 Control Bits */ +#define RFFIFOEN (0x0001) /* CC1101 Direct FIFO access enable */ +#define RFENDIAN (0x0002) /* CC1101 Disable endianness conversion */ + +/* RF1AIFCTL0 Control Bits */ +#define RFFIFOEN_L (0x0001) /* CC1101 Direct FIFO access enable */ +#define RFENDIAN_L (0x0002) /* CC1101 Disable endianness conversion */ + +/* RF1AIFCTL1 Control Bits */ +#define RFRXIFG (0x0001) /* Radio interface direct FIFO access receive interrupt flag */ +#define RFTXIFG (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */ +#define RFERRIFG (0x0004) /* Radio interface error interrupt flag */ +#define RFINSTRIFG (0x0010) /* Radio interface instruction interrupt flag */ +#define RFDINIFG (0x0020) /* Radio interface data in interrupt flag */ +#define RFSTATIFG (0x0040) /* Radio interface status interrupt flag */ +#define RFDOUTIFG (0x0080) /* Radio interface data out interrupt flag */ +#define RFRXIE (0x0100) /* Radio interface direct FIFO access receive interrupt enable */ +#define RFTXIE (0x0200) /* Radio interface direct FIFO access transmit interrupt enable */ +#define RFERRIE (0x0400) /* Radio interface error interrupt enable */ +#define RFINSTRIE (0x1000) /* Radio interface instruction interrupt enable */ +#define RFDINIE (0x2000) /* Radio interface data in interrupt enable */ +#define RFSTATIE (0x4000) /* Radio interface status interrupt enable */ +#define RFDOUTIE (0x8000) /* Radio interface data out interrupt enable */ + +/* RF1AIFCTL1 Control Bits */ +#define RFRXIFG_L (0x0001) /* Radio interface direct FIFO access receive interrupt flag */ +#define RFTXIFG_L (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */ +#define RFERRIFG_L (0x0004) /* Radio interface error interrupt flag */ +#define RFINSTRIFG_L (0x0010) /* Radio interface instruction interrupt flag */ +#define RFDINIFG_L (0x0020) /* Radio interface data in interrupt flag */ +#define RFSTATIFG_L (0x0040) /* Radio interface status interrupt flag */ +#define RFDOUTIFG_L (0x0080) /* Radio interface data out interrupt flag */ + +/* RF1AIFCTL1 Control Bits */ +#define RFRXIE_H (0x0001) /* Radio interface direct FIFO access receive interrupt enable */ +#define RFTXIE_H (0x0002) /* Radio interface direct FIFO access transmit interrupt enable */ +#define RFERRIE_H (0x0004) /* Radio interface error interrupt enable */ +#define RFINSTRIE_H (0x0010) /* Radio interface instruction interrupt enable */ +#define RFDINIE_H (0x0020) /* Radio interface data in interrupt enable */ +#define RFSTATIE_H (0x0040) /* Radio interface status interrupt enable */ +#define RFDOUTIE_H (0x0080) /* Radio interface data out interrupt enable */ + +/* RF1AIFERR Control Bits */ +#define LVERR (0x0001) /* Low Core Voltage Error Flag */ +#define OPERR (0x0002) /* Operand Error Flag */ +#define OUTERR (0x0004) /* Output data not available Error Flag */ +#define OPOVERR (0x0008) /* Operand Overwrite Error Flag */ + +/* RF1AIFERR Control Bits */ +#define LVERR_L (0x0001) /* Low Core Voltage Error Flag */ +#define OPERR_L (0x0002) /* Operand Error Flag */ +#define OUTERR_L (0x0004) /* Output data not available Error Flag */ +#define OPOVERR_L (0x0008) /* Operand Overwrite Error Flag */ + +/* RF1AIFERRV Definitions */ +#define RF1AIFERRV_NONE (0x0000) /* No Error pending */ +#define RF1AIFERRV_LVERR (0x0002) /* Low core voltage error */ +#define RF1AIFERRV_OPERR (0x0004) /* Operand Error */ +#define RF1AIFERRV_OUTERR (0x0006) /* Output data not available Error */ +#define RF1AIFERRV_OPOVERR (0x0008) /* Operand Overwrite Error */ + +/* RF1AIFIV Definitions */ +#define RF1AIFIV_NONE (0x0000) /* No Interrupt pending */ +#define RF1AIFIV_RFERRIFG (0x0002) /* Radio interface error */ +#define RF1AIFIV_RFDOUTIFG (0x0004) /* Radio i/f data out */ +#define RF1AIFIV_RFSTATIFG (0x0006) /* Radio i/f status out */ +#define RF1AIFIV_RFDINIFG (0x0008) /* Radio i/f data in */ +#define RF1AIFIV_RFINSTRIFG (0x000A) /* Radio i/f instruction in */ + +/* RF1AIV Definitions */ +#define RF1AIV_NONE (0x0000) /* No Interrupt pending */ +#define RF1AIV_RFIFG0 (0x0002) /* RFIFG0 */ +#define RF1AIV_RFIFG1 (0x0004) /* RFIFG1 */ +#define RF1AIV_RFIFG2 (0x0006) /* RFIFG2 */ +#define RF1AIV_RFIFG3 (0x0008) /* RFIFG3 */ +#define RF1AIV_RFIFG4 (0x000A) /* RFIFG4 */ +#define RF1AIV_RFIFG5 (0x000C) /* RFIFG5 */ +#define RF1AIV_RFIFG6 (0x000E) /* RFIFG6 */ +#define RF1AIV_RFIFG7 (0x0010) /* RFIFG7 */ +#define RF1AIV_RFIFG8 (0x0012) /* RFIFG8 */ +#define RF1AIV_RFIFG9 (0x0014) /* RFIFG9 */ +#define RF1AIV_RFIFG10 (0x0016) /* RFIFG10 */ +#define RF1AIV_RFIFG11 (0x0018) /* RFIFG11 */ +#define RF1AIV_RFIFG12 (0x001A) /* RFIFG12 */ +#define RF1AIV_RFIFG13 (0x001C) /* RFIFG13 */ +#define RF1AIV_RFIFG14 (0x001E) /* RFIFG14 */ +#define RF1AIV_RFIFG15 (0x0020) /* RFIFG15 */ + +// Radio Core Registers +#define IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */ +#define IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */ +#define IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */ +#define FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */ +#define SYNC1 0x04 /* SYNC1 - Sync word, high byte */ +#define SYNC0 0x05 /* SYNC0 - Sync word, low byte */ +#define PKTLEN 0x06 /* PKTLEN - Packet length */ +#define PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */ +#define PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */ +#define ADDR 0x09 /* ADDR - Device address */ +#define CHANNR 0x0A /* CHANNR - Channel number */ +#define FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */ +#define FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */ +#define FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */ +#define FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */ +#define FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */ +#define MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */ +#define MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */ +#define MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */ +#define MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */ +#define MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */ +#define DEVIATN 0x15 /* DEVIATN - Modem deviation setting */ +#define MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */ +#define MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */ +#define MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */ +#define FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */ +#define BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */ +#define AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */ +#define AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */ +#define AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */ +#define WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */ +#define WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */ +#define WORCTRL 0x20 /* WORCTRL - Wake On Radio control */ +#define FREND1 0x21 /* FREND1 - Front end RX configuration */ +#define FREND0 0x22 /* FREDN0 - Front end TX configuration */ +#define FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */ +#define FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */ +#define FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */ +#define FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */ +//#define RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */ +//#define RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */ +#define FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */ +#define PTEST 0x2A /* PTEST - Production test */ +#define AGCTEST 0x2B /* AGCTEST - AGC test */ +#define TEST2 0x2C /* TEST2 - Various test settings */ +#define TEST1 0x2D /* TEST1 - Various test settings */ +#define TEST0 0x2E /* TEST0 - Various test settings */ + +/* status registers */ +#define PARTNUM 0x30 /* PARTNUM - Chip ID */ +#define VERSION 0x31 /* VERSION - Chip ID */ +#define FREQEST 0x32 /* FREQEST – Frequency Offset Estimate from demodulator */ +#define LQI 0x33 /* LQI – Demodulator estimate for Link Quality */ +#define RSSI 0x34 /* RSSI – Received signal strength indication */ +#define MARCSTATE 0x35 /* MARCSTATE – Main Radio Control State Machine state */ +#define WORTIME1 0x36 /* WORTIME1 – High byte of WOR time */ +#define WORTIME0 0x37 /* WORTIME0 – Low byte of WOR time */ +#define PKTSTATUS 0x38 /* PKTSTATUS – Current GDOx status and packet status */ +#define VCO_VC_DAC 0x39 /* VCO_VC_DAC – Current setting from PLL calibration module */ +#define TXBYTES 0x3A /* TXBYTES – Underflow and number of bytes */ +#define RXBYTES 0x3B /* RXBYTES – Overflow and number of bytes */ + +/* burst write registers */ +#define PATABLE 0x3E /* PATABLE - PA control settings table */ +#define TXFIFO 0x3F /* TXFIFO - Transmit FIFO */ +#define RXFIFO 0x3F /* RXFIFO - Receive FIFO */ + +/* Radio Core Instructions */ +/* command strobes */ +#define RF_SRES 0x30 /* SRES - Reset chip. */ +#define RF_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */ +#define RF_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */ +#define RF_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */ +#define RF_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */ +#define RF_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */ +#define RF_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */ +//#define RF_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */ +#define RF_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */ +#define RF_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */ +#define RF_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */ +#define RF_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */ +#define RF_SWORRST 0x3C /* SWORRST - Reset real time clock. */ +#define RF_SNOP 0x3D /* SNOP - No operation. Returns status byte. */ + +#define RF_RXSTAT 0x80 /* Used in combination with strobe commands delivers number of availabe bytes in RX FIFO with return status */ +#define RF_TXSTAT 0x00 /* Used in combination with strobe commands delivers number of availabe bytes in TX FIFO with return status */ + +/* other radio instr */ +#define RF_SNGLREGRD 0x80 +#define RF_SNGLREGWR 0x00 +#define RF_REGRD 0xC0 +#define RF_REGWR 0x40 +#define RF_STATREGRD 0xC0 /* Read single radio core status register */ +#define RF_SNGLPATABRD (RF_SNGLREGRD+PATABLE) +#define RF_SNGLPATABWR (RF_SNGLREGWR+PATABLE) +#define RF_PATABRD (RF_REGRD+PATABLE) +#define RF_PATABWR (RF_REGWR+PATABLE) +#define RF_SNGLRXRD (RF_SNGLREGRD+RXFIFO) +#define RF_SNGLTXWR (RF_SNGLREGWR+TXFIFO) +#define RF_RXFIFORD (RF_REGRD+RXFIFO) +#define RF_TXFIFOWR (RF_REGWR+TXFIFO) + +/************************************************************* +* CRC Module +*************************************************************/ +#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_CRC__ 0x0150 +#define CRC_BASE __MSP430_BASEADDRESS_CRC__ + +sfr_w(CRCDI); /* CRC Data In Register */ +sfr_b(CRCDI_L); /* CRC Data In Register */ +sfr_b(CRCDI_H); /* CRC Data In Register */ +sfr_w(CRCINIRES); /* CRC Initialisation Register and Result Register*/ +sfr_b(CRCINIRES_L); /* CRC Initialisation Register and Result Register*/ +sfr_b(CRCINIRES_H); /* CRC Initialisation Register and Result Register*/ + +/************************************************************ +* DMA_X +************************************************************/ +#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500 +#define DMA_BASE __MSP430_BASEADDRESS_DMAX_3__ + +sfr_w(DMACTL0); /* DMA Module Control 0 */ +sfr_w(DMACTL1); /* DMA Module Control 1 */ +sfr_w(DMACTL2); /* DMA Module Control 2 */ +sfr_w(DMACTL3); /* DMA Module Control 3 */ +sfr_w(DMACTL4); /* DMA Module Control 4 */ +sfr_w(DMAIV); /* DMA Interrupt Vector Word */ + +sfr_w(DMA0CTL); /* DMA Channel 0 Control */ +sfr_l(DMA0SA); /* DMA Channel 0 Source Address */ +sfr_w(DMA0SAL); /* DMA Channel 0 Source Address */ +sfr_w(DMA0SAH); /* DMA Channel 0 Source Address */ +sfr_l(DMA0DA); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0DAL); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0DAH); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0SZ); /* DMA Channel 0 Transfer Size */ + +sfr_w(DMA1CTL); /* DMA Channel 1 Control */ +sfr_l(DMA1SA); /* DMA Channel 1 Source Address */ +sfr_w(DMA1SAL); /* DMA Channel 1 Source Address */ +sfr_w(DMA1SAH); /* DMA Channel 1 Source Address */ +sfr_l(DMA1DA); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1DAL); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1DAH); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1SZ); /* DMA Channel 1 Transfer Size */ + +sfr_w(DMA2CTL); /* DMA Channel 2 Control */ +sfr_l(DMA2SA); /* DMA Channel 2 Source Address */ +sfr_w(DMA2SAL); /* DMA Channel 2 Source Address */ +sfr_w(DMA2SAH); /* DMA Channel 2 Source Address */ +sfr_l(DMA2DA); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2DAL); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2DAH); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2SZ); /* DMA Channel 2 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */ +#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */ +#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */ +#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/ + +#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ +#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG) */ +#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG) */ +#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: Reserved */ +#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: Reserved */ +#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ +#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ +#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ +#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ +#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ +#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: RFRXIFG */ +#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: RFTXIFG */ +#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ +#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ +#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ +#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ +#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: Reserved */ +#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: Reserved */ +#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: Reserved */ +#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: Reserved */ +#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ +#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ +#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ +#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: Reserved */ +#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: Reserved */ +#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ +#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ +#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG) */ +#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG) */ +#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: Reserved */ +#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: Reserved */ +#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ +#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ +#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ +#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ +#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ +#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: RFRXIFG */ +#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: RFTXIFG */ +#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ +#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ +#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ +#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ +#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: Reserved */ +#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: Reserved */ +#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: Reserved */ +#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: Reserved */ +#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ +#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ +#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ +#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: Reserved */ +#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: Reserved */ +#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ +#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ +#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ +#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG) */ +#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG) */ +#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: Reserved */ +#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: Reserved */ +#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ +#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ +#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ +#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ +#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ +#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: RFRXIFG */ +#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: RFTXIFG */ +#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ +#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ +#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ +#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ +#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: Reserved */ +#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: Reserved */ +#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: Reserved */ +#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: Reserved */ +#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ +#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ +#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ +#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: Reserved */ +#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: Reserved */ +#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ +#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ +#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA0TSEL__DMA_REQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ +#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA0TSEL__TB0CCR0 (0x0005) /* DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG) */ +#define DMA0TSEL__TB0CCR2 (0x0006) /* DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG) */ +#define DMA0TSEL__RES7 (0x0007) /* DMA channel 0 transfer select 7: Reserved */ +#define DMA0TSEL__RES8 (0x0008) /* DMA channel 0 transfer select 8: Reserved */ +#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ +#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ +#define DMA0TSEL__RES11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ +#define DMA0TSEL__RES12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ +#define DMA0TSEL__RES13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ +#define DMA0TSEL__RFRXIFG (0x000E) /* DMA channel 0 transfer select 14: RFRXIFG */ +#define DMA0TSEL__RFTXIFG (0x000F) /* DMA channel 0 transfer select 15: RFTXIFG */ +#define DMA0TSEL__USCIA0RX (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ +#define DMA0TSEL__USCIA0TX (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ +#define DMA0TSEL__USCIB0RX (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ +#define DMA0TSEL__USCIB0TX (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ +#define DMA0TSEL__RES20 (0x0014) /* DMA channel 0 transfer select 20: Reserved */ +#define DMA0TSEL__RES21 (0x0015) /* DMA channel 0 transfer select 21: Reserved */ +#define DMA0TSEL__RES22 (0x0016) /* DMA channel 0 transfer select 22: Reserved */ +#define DMA0TSEL__RES23 (0x0017) /* DMA channel 0 transfer select 23: Reserved */ +#define DMA0TSEL__ADC12IFG (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ +#define DMA0TSEL__RES25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ +#define DMA0TSEL__RES26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ +#define DMA0TSEL__RES27 (0x001B) /* DMA channel 0 transfer select 27: Reserved */ +#define DMA0TSEL__RES28 (0x001C) /* DMA channel 0 transfer select 28: Reserved */ +#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ +#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA1TSEL__DMA_REQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ +#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA1TSEL__TB0CCR0 (0x0500) /* DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG) */ +#define DMA1TSEL__TB0CCR2 (0x0600) /* DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG) */ +#define DMA1TSEL__RES7 (0x0700) /* DMA channel 1 transfer select 7: Reserved */ +#define DMA1TSEL__RES8 (0x0800) /* DMA channel 1 transfer select 8: Reserved */ +#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ +#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ +#define DMA1TSEL__RES11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ +#define DMA1TSEL__RES12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ +#define DMA1TSEL__RES13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ +#define DMA1TSEL__RFRXIFG (0x0E00) /* DMA channel 1 transfer select 14: RFRXIFG */ +#define DMA1TSEL__RFTXIFG (0x0F00) /* DMA channel 1 transfer select 15: RFTXIFG */ +#define DMA1TSEL__USCIA0RX (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ +#define DMA1TSEL__USCIA0TX (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ +#define DMA1TSEL__USCIB0RX (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ +#define DMA1TSEL__USCIB0TX (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ +#define DMA1TSEL__RES20 (0x1400) /* DMA channel 1 transfer select 20: Reserved */ +#define DMA1TSEL__RES21 (0x1500) /* DMA channel 1 transfer select 21: Reserved */ +#define DMA1TSEL__RES22 (0x1600) /* DMA channel 1 transfer select 22: Reserved */ +#define DMA1TSEL__RES23 (0x1700) /* DMA channel 1 transfer select 23: Reserved */ +#define DMA1TSEL__ADC12IFG (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ +#define DMA1TSEL__RES25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ +#define DMA1TSEL__RES26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ +#define DMA1TSEL__RES27 (0x1B00) /* DMA channel 1 transfer select 27: Reserved */ +#define DMA1TSEL__RES28 (0x1C00) /* DMA channel 1 transfer select 28: Reserved */ +#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ +#define DMA1TSEL__DMA0IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ +#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA2TSEL__DMA_REQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ +#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA2TSEL__TB0CCR0 (0x0005) /* DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG) */ +#define DMA2TSEL__TB0CCR2 (0x0006) /* DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG) */ +#define DMA2TSEL__RES7 (0x0007) /* DMA channel 2 transfer select 7: Reserved */ +#define DMA2TSEL__RES8 (0x0008) /* DMA channel 2 transfer select 8: Reserved */ +#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ +#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ +#define DMA2TSEL__RES11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ +#define DMA2TSEL__RES12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ +#define DMA2TSEL__RES13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ +#define DMA2TSEL__RFRXIFG (0x000E) /* DMA channel 2 transfer select 14: RFRXIFG */ +#define DMA2TSEL__RFTXIFG (0x000F) /* DMA channel 2 transfer select 15: RFTXIFG */ +#define DMA2TSEL__USCIA0RX (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ +#define DMA2TSEL__USCIA0TX (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ +#define DMA2TSEL__USCIB0RX (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ +#define DMA2TSEL__USCIB0TX (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ +#define DMA2TSEL__RES20 (0x0014) /* DMA channel 2 transfer select 20: Reserved */ +#define DMA2TSEL__RES21 (0x0015) /* DMA channel 2 transfer select 21: Reserved */ +#define DMA2TSEL__RES22 (0x0016) /* DMA channel 2 transfer select 22: Reserved */ +#define DMA2TSEL__RES23 (0x0017) /* DMA channel 2 transfer select 23: Reserved */ +#define DMA2TSEL__ADC12IFG (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ +#define DMA2TSEL__RES25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ +#define DMA2TSEL__RES26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ +#define DMA2TSEL__RES27 (0x001B) /* DMA channel 2 transfer select 27: Reserved */ +#define DMA2TSEL__RES28 (0x001C) /* DMA channel 2 transfer select 28: Reserved */ +#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ +#define DMA2TSEL__DMA1IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ +#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ + +/************************************************************* +* Flash Memory +*************************************************************/ +#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_FLASH__ 0x0140 +#define FLASH_BASE __MSP430_BASEADDRESS_FLASH__ + +sfr_w(FCTL1); /* FLASH Control 1 */ +sfr_b(FCTL1_L); /* FLASH Control 1 */ +sfr_b(FCTL1_H); /* FLASH Control 1 */ +//sfrbw FCTL2 (0x0142) /* FLASH Control 2 */ +sfr_w(FCTL3); /* FLASH Control 3 */ +sfr_b(FCTL3_L); /* FLASH Control 3 */ +sfr_b(FCTL3_H); /* FLASH Control 3 */ +sfr_w(FCTL4); /* FLASH Control 4 */ +sfr_b(FCTL4_L); /* FLASH Control 4 */ +sfr_b(FCTL4_H); /* FLASH Control 4 */ + +#define FRPW (0x9600) /* Flash password returned by read */ +#define FWPW (0xA500) /* Flash password for write */ +#define FXPW (0x3300) /* for use with XOR instruction */ +#define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */ +#define FWKEY (0xA500) /* (legacy definition) Flash key for write */ +#define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001) /* Reserved */ +#define ERASE (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008) /* Reserved */ +//#define RESERVED (0x0010) /* Reserved */ +#define SWRT (0x0020) /* Smart Write enable */ +#define WRT (0x0040) /* Enable bit for Flash write */ +#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001) /* Reserved */ +#define ERASE_L (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS_L (0x0004) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008) /* Reserved */ +//#define RESERVED (0x0010) /* Reserved */ +#define SWRT_L (0x0020) /* Smart Write enable */ +#define WRT_L (0x0040) /* Enable bit for Flash write */ +#define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */ + +/* FCTL3 Control Bits */ +#define BUSY (0x0001) /* Flash busy: 1 */ +#define KEYV (0x0002) /* Flash Key violation flag */ +#define ACCVIFG (0x0004) /* Flash Access violation flag */ +#define WAIT (0x0008) /* Wait flag for segment write */ +#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020) /* Flash Emergency Exit */ +#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080) /* Reserved */ + +/* FCTL3 Control Bits */ +#define BUSY_L (0x0001) /* Flash busy: 1 */ +#define KEYV_L (0x0002) /* Flash Key violation flag */ +#define ACCVIFG_L (0x0004) /* Flash Access violation flag */ +#define WAIT_L (0x0008) /* Wait flag for segment write */ +#define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX_L (0x0020) /* Flash Emergency Exit */ +#define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080) /* Reserved */ + +/* FCTL4 Control Bits */ +#define VPE (0x0001) /* Voltage Changed during Program Error Flag */ +#define MGR0 (0x0010) /* Marginal read 0 mode. */ +#define MGR1 (0x0020) /* Marginal read 1 mode. */ +#define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + +/* FCTL4 Control Bits */ +#define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */ +#define MGR0_L (0x0010) /* Marginal read 0 mode. */ +#define MGR1_L (0x0020) /* Marginal read 1 mode. */ +#define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + +/************************************************************ +* LCD_B +************************************************************/ +#define __MSP430_HAS_LCD_B__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_LCD_B__ 0x0A00 +#define LCD_B_BASE __MSP430_BASEADDRESS_LCD_B__ + +sfr_w(LCDBCTL0); /* LCD_B Control Register 0 */ +sfr_b(LCDBCTL0_L); /* LCD_B Control Register 0 */ +sfr_b(LCDBCTL0_H); /* LCD_B Control Register 0 */ +sfr_w(LCDBCTL1); /* LCD_B Control Register 1 */ +sfr_b(LCDBCTL1_L); /* LCD_B Control Register 1 */ +sfr_b(LCDBCTL1_H); /* LCD_B Control Register 1 */ +sfr_w(LCDBBLKCTL); /* LCD_B blinking control register */ +sfr_b(LCDBBLKCTL_L); /* LCD_B blinking control register */ +sfr_b(LCDBBLKCTL_H); /* LCD_B blinking control register */ +sfr_w(LCDBMEMCTL); /* LCD_B memory control register */ +sfr_b(LCDBMEMCTL_L); /* LCD_B memory control register */ +sfr_b(LCDBMEMCTL_H); /* LCD_B memory control register */ +sfr_w(LCDBVCTL); /* LCD_B Voltage Control Register */ +sfr_b(LCDBVCTL_L); /* LCD_B Voltage Control Register */ +sfr_b(LCDBVCTL_H); /* LCD_B Voltage Control Register */ +sfr_w(LCDBPCTL0); /* LCD_B Port Control Register 0 */ +sfr_b(LCDBPCTL0_L); /* LCD_B Port Control Register 0 */ +sfr_b(LCDBPCTL0_H); /* LCD_B Port Control Register 0 */ +sfr_w(LCDBPCTL1); /* LCD_B Port Control Register 1 */ +sfr_b(LCDBPCTL1_L); /* LCD_B Port Control Register 1 */ +sfr_b(LCDBPCTL1_H); /* LCD_B Port Control Register 1 */ +sfr_w(LCDBPCTL2); /* LCD_B Port Control Register 2 */ +sfr_b(LCDBPCTL2_L); /* LCD_B Port Control Register 2 */ +sfr_b(LCDBPCTL2_H); /* LCD_B Port Control Register 2 */ +sfr_w(LCDBPCTL3); /* LCD_B Port Control Register 3 */ +sfr_b(LCDBPCTL3_L); /* LCD_B Port Control Register 3 */ +sfr_b(LCDBPCTL3_H); /* LCD_B Port Control Register 3 */ +sfr_w(LCDBCPCTL); /* LCD_B Charge Pump Control Register 3 */ +sfr_b(LCDBCPCTL_L); /* LCD_B Charge Pump Control Register 3 */ +sfr_b(LCDBCPCTL_H); /* LCD_B Charge Pump Control Register 3 */ +sfr_w(LCDBIV); /* LCD_B Interrupt Vector Register */ + +// LCDBCTL0 +#define LCDON (0x0001) /* LCD_B LCD On */ +#define LCDSON (0x0004) /* LCD_B LCD Segments On */ +#define LCDMX0 (0x0008) /* LCD_B Mux Rate Bit: 0 */ +#define LCDMX1 (0x0010) /* LCD_B Mux Rate Bit: 1 */ +//#define RESERVED (0x0020) /* LCD_B RESERVED */ +//#define RESERVED (0x0040) /* LCD_B RESERVED */ +#define LCDSSEL (0x0080) /* LCD_B Clock Select */ +#define LCDPRE0 (0x0100) /* LCD_B LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1 (0x0200) /* LCD_B LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2 (0x0400) /* LCD_B LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0 (0x0800) /* LCD_B LCD frequency divider Bit: 0 */ +#define LCDDIV1 (0x1000) /* LCD_B LCD frequency divider Bit: 1 */ +#define LCDDIV2 (0x2000) /* LCD_B LCD frequency divider Bit: 2 */ +#define LCDDIV3 (0x4000) /* LCD_B LCD frequency divider Bit: 3 */ +#define LCDDIV4 (0x8000) /* LCD_B LCD frequency divider Bit: 4 */ + +// LCDBCTL0 +#define LCDON_L (0x0001) /* LCD_B LCD On */ +#define LCDSON_L (0x0004) /* LCD_B LCD Segments On */ +#define LCDMX0_L (0x0008) /* LCD_B Mux Rate Bit: 0 */ +#define LCDMX1_L (0x0010) /* LCD_B Mux Rate Bit: 1 */ +//#define RESERVED (0x0020) /* LCD_B RESERVED */ +//#define RESERVED (0x0040) /* LCD_B RESERVED */ +#define LCDSSEL_L (0x0080) /* LCD_B Clock Select */ + +// LCDBCTL0 +//#define RESERVED (0x0020) /* LCD_B RESERVED */ +//#define RESERVED (0x0040) /* LCD_B RESERVED */ +#define LCDPRE0_H (0x0001) /* LCD_B LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1_H (0x0002) /* LCD_B LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2_H (0x0004) /* LCD_B LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0_H (0x0008) /* LCD_B LCD frequency divider Bit: 0 */ +#define LCDDIV1_H (0x0010) /* LCD_B LCD frequency divider Bit: 1 */ +#define LCDDIV2_H (0x0020) /* LCD_B LCD frequency divider Bit: 2 */ +#define LCDDIV3_H (0x0040) /* LCD_B LCD frequency divider Bit: 3 */ +#define LCDDIV4_H (0x0080) /* LCD_B LCD frequency divider Bit: 4 */ + +#define LCDPRE_0 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */ +#define LCDPRE_1 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */ +#define LCDPRE_2 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */ +#define LCDPRE_3 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */ +#define LCDPRE_4 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */ +#define LCDPRE_5 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */ +#define LCDPRE__1 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */ +#define LCDPRE__2 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */ +#define LCDPRE__4 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */ +#define LCDPRE__8 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */ +#define LCDPRE__16 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */ +#define LCDPRE__32 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */ + +#define LCDDIV_0 (0x0000) /* LCD_B LCD frequency divider: /1 */ +#define LCDDIV_1 (0x0800) /* LCD_B LCD frequency divider: /2 */ +#define LCDDIV_2 (0x1000) /* LCD_B LCD frequency divider: /3 */ +#define LCDDIV_3 (0x1800) /* LCD_B LCD frequency divider: /4 */ +#define LCDDIV_4 (0x2000) /* LCD_B LCD frequency divider: /5 */ +#define LCDDIV_5 (0x2800) /* LCD_B LCD frequency divider: /6 */ +#define LCDDIV_6 (0x3000) /* LCD_B LCD frequency divider: /7 */ +#define LCDDIV_7 (0x3800) /* LCD_B LCD frequency divider: /8 */ +#define LCDDIV_8 (0x4000) /* LCD_B LCD frequency divider: /9 */ +#define LCDDIV_9 (0x4800) /* LCD_B LCD frequency divider: /10 */ +#define LCDDIV_10 (0x5000) /* LCD_B LCD frequency divider: /11 */ +#define LCDDIV_11 (0x5800) /* LCD_B LCD frequency divider: /12 */ +#define LCDDIV_12 (0x6000) /* LCD_B LCD frequency divider: /13 */ +#define LCDDIV_13 (0x6800) /* LCD_B LCD frequency divider: /14 */ +#define LCDDIV_14 (0x7000) /* LCD_B LCD frequency divider: /15 */ +#define LCDDIV_15 (0x7800) /* LCD_B LCD frequency divider: /16 */ +#define LCDDIV_16 (0x8000) /* LCD_B LCD frequency divider: /17 */ +#define LCDDIV_17 (0x8800) /* LCD_B LCD frequency divider: /18 */ +#define LCDDIV_18 (0x9000) /* LCD_B LCD frequency divider: /19 */ +#define LCDDIV_19 (0x9800) /* LCD_B LCD frequency divider: /20 */ +#define LCDDIV_20 (0xA000) /* LCD_B LCD frequency divider: /21 */ +#define LCDDIV_21 (0xA800) /* LCD_B LCD frequency divider: /22 */ +#define LCDDIV_22 (0xB000) /* LCD_B LCD frequency divider: /23 */ +#define LCDDIV_23 (0xB800) /* LCD_B LCD frequency divider: /24 */ +#define LCDDIV_24 (0xC000) /* LCD_B LCD frequency divider: /25 */ +#define LCDDIV_25 (0xC800) /* LCD_B LCD frequency divider: /26 */ +#define LCDDIV_26 (0xD000) /* LCD_B LCD frequency divider: /27 */ +#define LCDDIV_27 (0xD800) /* LCD_B LCD frequency divider: /28 */ +#define LCDDIV_28 (0xE000) /* LCD_B LCD frequency divider: /29 */ +#define LCDDIV_29 (0xE800) /* LCD_B LCD frequency divider: /30 */ +#define LCDDIV_30 (0xF000) /* LCD_B LCD frequency divider: /31 */ +#define LCDDIV_31 (0xF800) /* LCD_B LCD frequency divider: /32 */ +#define LCDDIV__1 (0x0000) /* LCD_B LCD frequency divider: /1 */ +#define LCDDIV__2 (0x0800) /* LCD_B LCD frequency divider: /2 */ +#define LCDDIV__3 (0x1000) /* LCD_B LCD frequency divider: /3 */ +#define LCDDIV__4 (0x1800) /* LCD_B LCD frequency divider: /4 */ +#define LCDDIV__5 (0x2000) /* LCD_B LCD frequency divider: /5 */ +#define LCDDIV__6 (0x2800) /* LCD_B LCD frequency divider: /6 */ +#define LCDDIV__7 (0x3000) /* LCD_B LCD frequency divider: /7 */ +#define LCDDIV__8 (0x3800) /* LCD_B LCD frequency divider: /8 */ +#define LCDDIV__9 (0x4000) /* LCD_B LCD frequency divider: /9 */ +#define LCDDIV__10 (0x4800) /* LCD_B LCD frequency divider: /10 */ +#define LCDDIV__11 (0x5000) /* LCD_B LCD frequency divider: /11 */ +#define LCDDIV__12 (0x5800) /* LCD_B LCD frequency divider: /12 */ +#define LCDDIV__13 (0x6000) /* LCD_B LCD frequency divider: /13 */ +#define LCDDIV__14 (0x6800) /* LCD_B LCD frequency divider: /14 */ +#define LCDDIV__15 (0x7000) /* LCD_B LCD frequency divider: /15 */ +#define LCDDIV__16 (0x7800) /* LCD_B LCD frequency divider: /16 */ +#define LCDDIV__17 (0x8000) /* LCD_B LCD frequency divider: /17 */ +#define LCDDIV__18 (0x8800) /* LCD_B LCD frequency divider: /18 */ +#define LCDDIV__19 (0x9000) /* LCD_B LCD frequency divider: /19 */ +#define LCDDIV__20 (0x9800) /* LCD_B LCD frequency divider: /20 */ +#define LCDDIV__21 (0xA000) /* LCD_B LCD frequency divider: /21 */ +#define LCDDIV__22 (0xA800) /* LCD_B LCD frequency divider: /22 */ +#define LCDDIV__23 (0xB000) /* LCD_B LCD frequency divider: /23 */ +#define LCDDIV__24 (0xB800) /* LCD_B LCD frequency divider: /24 */ +#define LCDDIV__25 (0xC000) /* LCD_B LCD frequency divider: /25 */ +#define LCDDIV__26 (0xC800) /* LCD_B LCD frequency divider: /26 */ +#define LCDDIV__27 (0xD000) /* LCD_B LCD frequency divider: /27 */ +#define LCDDIV__28 (0xD800) /* LCD_B LCD frequency divider: /28 */ +#define LCDDIV__29 (0xE000) /* LCD_B LCD frequency divider: /29 */ +#define LCDDIV__30 (0xE800) /* LCD_B LCD frequency divider: /30 */ +#define LCDDIV__31 (0xF000) /* LCD_B LCD frequency divider: /31 */ +#define LCDDIV__32 (0xF800) /* LCD_B LCD frequency divider: /32 */ + +/* Display modes coded with Bits 2-4 */ +#define LCDSTATIC (LCDSON) +#define LCD2MUX (LCDMX0+LCDSON) +#define LCD3MUX (LCDMX1+LCDSON) +#define LCD4MUX (LCDMX1+LCDMX0+LCDSON) + +// LCDBCTL1 +#define LCDFRMIFG (0x0001) /* LCD_B LCD frame interrupt flag */ +#define LCDBLKOFFIFG (0x0002) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIFG (0x0004) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG (0x0008) /* LCD_B No cpacitance connected interrupt flag */ +#define LCDFRMIE (0x0100) /* LCD_B LCD frame interrupt enable */ +#define LCDBLKOFFIE (0x0200) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIE (0x0400) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIE (0x0800) /* LCD_B No cpacitance connected interrupt enable */ + +// LCDBCTL1 +#define LCDFRMIFG_L (0x0001) /* LCD_B LCD frame interrupt flag */ +#define LCDBLKOFFIFG_L (0x0002) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIFG_L (0x0004) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG_L (0x0008) /* LCD_B No cpacitance connected interrupt flag */ + +// LCDBCTL1 +#define LCDFRMIE_H (0x0001) /* LCD_B LCD frame interrupt enable */ +#define LCDBLKOFFIE_H (0x0002) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIE_H (0x0004) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIE_H (0x0008) /* LCD_B No cpacitance connected interrupt enable */ + +// LCDBBLKCTL +#define LCDBLKMOD0 (0x0001) /* LCD_B Blinking mode Bit: 0 */ +#define LCDBLKMOD1 (0x0002) /* LCD_B Blinking mode Bit: 1 */ +#define LCDBLKPRE0 (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1 (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2 (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0 (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1 (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2 (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */ + +// LCDBBLKCTL +#define LCDBLKMOD0_L (0x0001) /* LCD_B Blinking mode Bit: 0 */ +#define LCDBLKMOD1_L (0x0002) /* LCD_B Blinking mode Bit: 1 */ +#define LCDBLKPRE0_L (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1_L (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2_L (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0_L (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1_L (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2_L (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */ + +#define LCDBLKMOD_0 (0x0000) /* LCD_B Blinking mode: Off */ +#define LCDBLKMOD_1 (0x0001) /* LCD_B Blinking mode: Individual */ +#define LCDBLKMOD_2 (0x0002) /* LCD_B Blinking mode: All */ +#define LCDBLKMOD_3 (0x0003) /* LCD_B Blinking mode: Switching */ + +#define LCDBLKPRE_0 (0x0000) /* LCD_B Clock pre-scaler for blinking frequency: 0 */ +#define LCDBLKPRE_1 (0x0004) /* LCD_B Clock pre-scaler for blinking frequency: 1 */ +#define LCDBLKPRE_2 (0x0008) /* LCD_B Clock pre-scaler for blinking frequency: 2 */ +#define LCDBLKPRE_3 (0x000C) /* LCD_B Clock pre-scaler for blinking frequency: 3 */ +#define LCDBLKPRE_4 (0x0010) /* LCD_B Clock pre-scaler for blinking frequency: 4 */ +#define LCDBLKPRE_5 (0x0014) /* LCD_B Clock pre-scaler for blinking frequency: 5 */ +#define LCDBLKPRE_6 (0x0018) /* LCD_B Clock pre-scaler for blinking frequency: 6 */ +#define LCDBLKPRE_7 (0x001C) /* LCD_B Clock pre-scaler for blinking frequency: 7 */ + +#define LCDBLKPRE__512 (0x0000) /* LCD_B Clock pre-scaler for blinking frequency: 512 */ +#define LCDBLKPRE__1024 (0x0004) /* LCD_B Clock pre-scaler for blinking frequency: 1024 */ +#define LCDBLKPRE__2048 (0x0008) /* LCD_B Clock pre-scaler for blinking frequency: 2048 */ +#define LCDBLKPRE__4096 (0x000C) /* LCD_B Clock pre-scaler for blinking frequency: 4096 */ +#define LCDBLKPRE__8192 (0x0010) /* LCD_B Clock pre-scaler for blinking frequency: 8192 */ +#define LCDBLKPRE__16384 (0x0014) /* LCD_B Clock pre-scaler for blinking frequency: 16384 */ +#define LCDBLKPRE__32768 (0x0018) /* LCD_B Clock pre-scaler for blinking frequency: 32768 */ +#define LCDBLKPRE__65536 (0x001C) /* LCD_B Clock pre-scaler for blinking frequency: 65536 */ + +#define LCDBLKDIV_0 (0x0000) /* LCD_B Clock divider for blinking frequency: 0 */ +#define LCDBLKDIV_1 (0x0020) /* LCD_B Clock divider for blinking frequency: 1 */ +#define LCDBLKDIV_2 (0x0040) /* LCD_B Clock divider for blinking frequency: 2 */ +#define LCDBLKDIV_3 (0x0060) /* LCD_B Clock divider for blinking frequency: 3 */ +#define LCDBLKDIV_4 (0x0080) /* LCD_B Clock divider for blinking frequency: 4 */ +#define LCDBLKDIV_5 (0x00A0) /* LCD_B Clock divider for blinking frequency: 5 */ +#define LCDBLKDIV_6 (0x00C0) /* LCD_B Clock divider for blinking frequency: 6 */ +#define LCDBLKDIV_7 (0x00E0) /* LCD_B Clock divider for blinking frequency: 7 */ + +#define LCDBLKDIV__1 (0x0000) /* LCD_B Clock divider for blinking frequency: /1 */ +#define LCDBLKDIV__2 (0x0020) /* LCD_B Clock divider for blinking frequency: /2 */ +#define LCDBLKDIV__3 (0x0040) /* LCD_B Clock divider for blinking frequency: /3 */ +#define LCDBLKDIV__4 (0x0060) /* LCD_B Clock divider for blinking frequency: /4 */ +#define LCDBLKDIV__5 (0x0080) /* LCD_B Clock divider for blinking frequency: /5 */ +#define LCDBLKDIV__6 (0x00A0) /* LCD_B Clock divider for blinking frequency: /6 */ +#define LCDBLKDIV__7 (0x00C0) /* LCD_B Clock divider for blinking frequency: /7 */ +#define LCDBLKDIV__8 (0x00E0) /* LCD_B Clock divider for blinking frequency: /8 */ + +// LCDBMEMCTL +#define LCDDISP (0x0001) /* LCD_B LCD memory registers for display */ +#define LCDCLRM (0x0002) /* LCD_B Clear LCD memory */ +#define LCDCLRBM (0x0004) /* LCD_B Clear LCD blinking memory */ + +// LCDBMEMCTL +#define LCDDISP_L (0x0001) /* LCD_B LCD memory registers for display */ +#define LCDCLRM_L (0x0002) /* LCD_B Clear LCD memory */ +#define LCDCLRBM_L (0x0004) /* LCD_B Clear LCD blinking memory */ + +// LCDBVCTL +#define LCD2B (0x0001) /* Selects 1/2 bias. */ +#define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT (0x0010) /* Select external source for VLCD. */ +#define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */ +#define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */ +#define VLCD0 (0x0200) /* VLCD select: 0 */ +#define VLCD1 (0x0400) /* VLCD select: 1 */ +#define VLCD2 (0x0800) /* VLCD select: 2 */ +#define VLCD3 (0x1000) /* VLCD select: 3 */ + +// LCDBVCTL +#define LCD2B_L (0x0001) /* Selects 1/2 bias. */ +#define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT_L (0x0010) /* Select external source for VLCD. */ +#define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */ +#define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */ + +// LCDBVCTL +#define VLCD0_H (0x0002) /* VLCD select: 0 */ +#define VLCD1_H (0x0004) /* VLCD select: 1 */ +#define VLCD2_H (0x0008) /* VLCD select: 2 */ +#define VLCD3_H (0x0010) /* VLCD select: 3 */ + +/* Reference voltage source select for the regulated charge pump */ +#define VLCDREF_0 (0<<1) /* Internal */ +#define VLCDREF_1 (1<<1) /* External */ +#define VLCDREF_2 (2<<1) /* Reserved */ +#define VLCDREF_3 (3<<1) /* Reserved */ + +/* Charge pump voltage selections */ +#define VLCD_0 (0<<9) /* Charge pump disabled */ +#define VLCD_1 (1<<9) /* VLCD = 2.60V */ +#define VLCD_2 (2<<9) /* VLCD = 2.66V */ +#define VLCD_3 (3<<9) /* VLCD = 2.72V */ +#define VLCD_4 (4<<9) /* VLCD = 2.78V */ +#define VLCD_5 (5<<9) /* VLCD = 2.84V */ +#define VLCD_6 (6<<9) /* VLCD = 2.90V */ +#define VLCD_7 (7<<9) /* VLCD = 2.96V */ +#define VLCD_8 (8<<9) /* VLCD = 3.02V */ +#define VLCD_9 (9<<9) /* VLCD = 3.08V */ +#define VLCD_10 (10<<9) /* VLCD = 3.14V */ +#define VLCD_11 (11<<9) /* VLCD = 3.20V */ +#define VLCD_12 (12<<9) /* VLCD = 3.26V */ +#define VLCD_13 (13<<9) /* VLCD = 3.32V */ +#define VLCD_14 (14<<9) /* VLCD = 3.38V */ +#define VLCD_15 (15<<9) /* VLCD = 3.44V */ + +#define VLCD_DISABLED (0<<9) /* Charge pump disabled */ +#define VLCD_2_60 (1<<9) /* VLCD = 2.60V */ +#define VLCD_2_66 (2<<9) /* VLCD = 2.66V */ +#define VLCD_2_72 (3<<9) /* VLCD = 2.72V */ +#define VLCD_2_78 (4<<9) /* VLCD = 2.78V */ +#define VLCD_2_84 (5<<9) /* VLCD = 2.84V */ +#define VLCD_2_90 (6<<9) /* VLCD = 2.90V */ +#define VLCD_2_96 (7<<9) /* VLCD = 2.96V */ +#define VLCD_3_02 (8<<9) /* VLCD = 3.02V */ +#define VLCD_3_08 (9<<9) /* VLCD = 3.08V */ +#define VLCD_3_14 (10<<9) /* VLCD = 3.14V */ +#define VLCD_3_20 (11<<9) /* VLCD = 3.20V */ +#define VLCD_3_26 (12<<9) /* VLCD = 3.26V */ +#define VLCD_3_32 (13<<9) /* VLCD = 3.32V */ +#define VLCD_3_38 (14<<9) /* VLCD = 3.38V */ +#define VLCD_3_44 (15<<9) /* VLCD = 3.44V */ + +// LCDBPCTL0 +#define LCDS0 (0x0001) /* LCD Segment 0 enable. */ +#define LCDS1 (0x0002) /* LCD Segment 1 enable. */ +#define LCDS2 (0x0004) /* LCD Segment 2 enable. */ +#define LCDS3 (0x0008) /* LCD Segment 3 enable. */ +#define LCDS4 (0x0010) /* LCD Segment 4 enable. */ +#define LCDS5 (0x0020) /* LCD Segment 5 enable. */ +#define LCDS6 (0x0040) /* LCD Segment 6 enable. */ +#define LCDS7 (0x0080) /* LCD Segment 7 enable. */ +#define LCDS8 (0x0100) /* LCD Segment 8 enable. */ +#define LCDS9 (0x0200) /* LCD Segment 9 enable. */ +#define LCDS10 (0x0400) /* LCD Segment 10 enable. */ +#define LCDS11 (0x0800) /* LCD Segment 11 enable. */ +#define LCDS12 (0x1000) /* LCD Segment 12 enable. */ +#define LCDS13 (0x2000) /* LCD Segment 13 enable. */ +#define LCDS14 (0x4000) /* LCD Segment 14 enable. */ +#define LCDS15 (0x8000) /* LCD Segment 15 enable. */ + +// LCDBPCTL0 +#define LCDS0_L (0x0001) /* LCD Segment 0 enable. */ +#define LCDS1_L (0x0002) /* LCD Segment 1 enable. */ +#define LCDS2_L (0x0004) /* LCD Segment 2 enable. */ +#define LCDS3_L (0x0008) /* LCD Segment 3 enable. */ +#define LCDS4_L (0x0010) /* LCD Segment 4 enable. */ +#define LCDS5_L (0x0020) /* LCD Segment 5 enable. */ +#define LCDS6_L (0x0040) /* LCD Segment 6 enable. */ +#define LCDS7_L (0x0080) /* LCD Segment 7 enable. */ + +// LCDBPCTL0 +#define LCDS8_H (0x0001) /* LCD Segment 8 enable. */ +#define LCDS9_H (0x0002) /* LCD Segment 9 enable. */ +#define LCDS10_H (0x0004) /* LCD Segment 10 enable. */ +#define LCDS11_H (0x0008) /* LCD Segment 11 enable. */ +#define LCDS12_H (0x0010) /* LCD Segment 12 enable. */ +#define LCDS13_H (0x0020) /* LCD Segment 13 enable. */ +#define LCDS14_H (0x0040) /* LCD Segment 14 enable. */ +#define LCDS15_H (0x0080) /* LCD Segment 15 enable. */ + +// LCDBPCTL1 +#define LCDS16 (0x0001) /* LCD Segment 16 enable. */ +#define LCDS17 (0x0002) /* LCD Segment 17 enable. */ +#define LCDS18 (0x0004) /* LCD Segment 18 enable. */ +#define LCDS19 (0x0008) /* LCD Segment 19 enable. */ +#define LCDS20 (0x0010) /* LCD Segment 20 enable. */ +#define LCDS21 (0x0020) /* LCD Segment 21 enable. */ +#define LCDS22 (0x0040) /* LCD Segment 22 enable. */ +#define LCDS23 (0x0080) /* LCD Segment 23 enable. */ +#define LCDS24 (0x0100) /* LCD Segment 24 enable. */ +#define LCDS25 (0x0200) /* LCD Segment 25 enable. */ +#define LCDS26 (0x0400) /* LCD Segment 26 enable. */ +#define LCDS27 (0x0800) /* LCD Segment 27 enable. */ +#define LCDS28 (0x1000) /* LCD Segment 28 enable. */ +#define LCDS29 (0x2000) /* LCD Segment 29 enable. */ +#define LCDS30 (0x4000) /* LCD Segment 30 enable. */ +#define LCDS31 (0x8000) /* LCD Segment 31 enable. */ + +// LCDBPCTL1 +#define LCDS16_L (0x0001) /* LCD Segment 16 enable. */ +#define LCDS17_L (0x0002) /* LCD Segment 17 enable. */ +#define LCDS18_L (0x0004) /* LCD Segment 18 enable. */ +#define LCDS19_L (0x0008) /* LCD Segment 19 enable. */ +#define LCDS20_L (0x0010) /* LCD Segment 20 enable. */ +#define LCDS21_L (0x0020) /* LCD Segment 21 enable. */ +#define LCDS22_L (0x0040) /* LCD Segment 22 enable. */ +#define LCDS23_L (0x0080) /* LCD Segment 23 enable. */ + +// LCDBPCTL1 +#define LCDS24_H (0x0001) /* LCD Segment 24 enable. */ +#define LCDS25_H (0x0002) /* LCD Segment 25 enable. */ +#define LCDS26_H (0x0004) /* LCD Segment 26 enable. */ +#define LCDS27_H (0x0008) /* LCD Segment 27 enable. */ +#define LCDS28_H (0x0010) /* LCD Segment 28 enable. */ +#define LCDS29_H (0x0020) /* LCD Segment 29 enable. */ +#define LCDS30_H (0x0040) /* LCD Segment 30 enable. */ +#define LCDS31_H (0x0080) /* LCD Segment 31 enable. */ + +// LCDBPCTL2 +#define LCDS32 (0x0001) /* LCD Segment 32 enable. */ +#define LCDS33 (0x0002) /* LCD Segment 33 enable. */ +#define LCDS34 (0x0004) /* LCD Segment 34 enable. */ +#define LCDS35 (0x0008) /* LCD Segment 35 enable. */ +#define LCDS36 (0x0010) /* LCD Segment 36 enable. */ +#define LCDS37 (0x0020) /* LCD Segment 37 enable. */ +#define LCDS38 (0x0040) /* LCD Segment 38 enable. */ +#define LCDS39 (0x0080) /* LCD Segment 39 enable. */ +#define LCDS40 (0x0100) /* LCD Segment 40 enable. */ +#define LCDS41 (0x0200) /* LCD Segment 41 enable. */ +#define LCDS42 (0x0400) /* LCD Segment 42 enable. */ +#define LCDS43 (0x0800) /* LCD Segment 43 enable. */ +#define LCDS44 (0x1000) /* LCD Segment 44 enable. */ +#define LCDS45 (0x2000) /* LCD Segment 45 enable. */ +#define LCDS46 (0x4000) /* LCD Segment 46 enable. */ +#define LCDS47 (0x8000) /* LCD Segment 47 enable. */ + +// LCDBPCTL2 +#define LCDS32_L (0x0001) /* LCD Segment 32 enable. */ +#define LCDS33_L (0x0002) /* LCD Segment 33 enable. */ +#define LCDS34_L (0x0004) /* LCD Segment 34 enable. */ +#define LCDS35_L (0x0008) /* LCD Segment 35 enable. */ +#define LCDS36_L (0x0010) /* LCD Segment 36 enable. */ +#define LCDS37_L (0x0020) /* LCD Segment 37 enable. */ +#define LCDS38_L (0x0040) /* LCD Segment 38 enable. */ +#define LCDS39_L (0x0080) /* LCD Segment 39 enable. */ + +// LCDBPCTL2 +#define LCDS40_H (0x0001) /* LCD Segment 40 enable. */ +#define LCDS41_H (0x0002) /* LCD Segment 41 enable. */ +#define LCDS42_H (0x0004) /* LCD Segment 42 enable. */ +#define LCDS43_H (0x0008) /* LCD Segment 43 enable. */ +#define LCDS44_H (0x0010) /* LCD Segment 44 enable. */ +#define LCDS45_H (0x0020) /* LCD Segment 45 enable. */ +#define LCDS46_H (0x0040) /* LCD Segment 46 enable. */ +#define LCDS47_H (0x0080) /* LCD Segment 47 enable. */ + +// LCDBPCTL3 +#define LCDS48 (0x0001) /* LCD Segment 48 enable. */ +#define LCDS49 (0x0002) /* LCD Segment 49 enable. */ +#define LCDS50 (0x0004) /* LCD Segment 50 enable. */ + +// LCDBPCTL3 +#define LCDS48_L (0x0001) /* LCD Segment 48 enable. */ +#define LCDS49_L (0x0002) /* LCD Segment 49 enable. */ +#define LCDS50_L (0x0004) /* LCD Segment 50 enable. */ + +// LCDBCPCTL +#define LCDCPDIS0 (0x0001) /* LCD charge pump disable */ +#define LCDCPDIS1 (0x0002) /* LCD charge pump disable */ +#define LCDCPDIS2 (0x0004) /* LCD charge pump disable */ +#define LCDCPDIS3 (0x0008) /* LCD charge pump disable */ +#define LCDCPDIS4 (0x0010) /* LCD charge pump disable */ +#define LCDCPDIS5 (0x0020) /* LCD charge pump disable */ +#define LCDCPDIS6 (0x0040) /* LCD charge pump disable */ +#define LCDCPDIS7 (0x0080) /* LCD charge pump disable */ +#define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */ + +// LCDBCPCTL +#define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */ +#define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */ +#define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */ +#define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */ +#define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */ +#define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */ +#define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */ +#define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */ + +// LCDBCPCTL +#define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */ + +sfr_b(LCDM1); /* LCD Memory 1 */ +#define LCDMEM_ LCDM1 /* LCD Memory */ +#ifndef __STDC__ +#define LCDMEM LCDM1 /* LCD Memory (for assembler) */ +#else +#define LCDMEM ((volatile char*) &LCDM1) /* LCD Memory (for C) */ +#endif +sfr_b(LCDM2); /* LCD Memory 2 */ +sfr_b(LCDM3); /* LCD Memory 3 */ +sfr_b(LCDM4); /* LCD Memory 4 */ +sfr_b(LCDM5); /* LCD Memory 5 */ +sfr_b(LCDM6); /* LCD Memory 6 */ +sfr_b(LCDM7); /* LCD Memory 7 */ +sfr_b(LCDM8); /* LCD Memory 8 */ +sfr_b(LCDM9); /* LCD Memory 9 */ +sfr_b(LCDM10); /* LCD Memory 10 */ +sfr_b(LCDM11); /* LCD Memory 11 */ +sfr_b(LCDM12); /* LCD Memory 12 */ +sfr_b(LCDM13); /* LCD Memory 13 */ +sfr_b(LCDM14); /* LCD Memory 14 */ +sfr_b(LCDM15); /* LCD Memory 15 */ +sfr_b(LCDM16); /* LCD Memory 16 */ +sfr_b(LCDM17); /* LCD Memory 17 */ +sfr_b(LCDM18); /* LCD Memory 18 */ +sfr_b(LCDM19); /* LCD Memory 19 */ +sfr_b(LCDM20); /* LCD Memory 20 */ +sfr_b(LCDM21); /* LCD Memory 21 */ +sfr_b(LCDM22); /* LCD Memory 22 */ +sfr_b(LCDM23); /* LCD Memory 23 */ +sfr_b(LCDM24); /* LCD Memory 24 */ + +sfr_b(LCDBM1); /* LCD Blinking Memory 1 */ +#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */ +#ifndef __STDC__ +#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */ +#else +#define LCDBMEM ((volatile char*) &LCDBM1) /* LCD Blinking Memory (for C) */ +#endif +sfr_b(LCDBM2); /* LCD Blinking Memory 2 */ +sfr_b(LCDBM3); /* LCD Blinking Memory 3 */ +sfr_b(LCDBM4); /* LCD Blinking Memory 4 */ +sfr_b(LCDBM5); /* LCD Blinking Memory 5 */ +sfr_b(LCDBM6); /* LCD Blinking Memory 6 */ +sfr_b(LCDBM7); /* LCD Blinking Memory 7 */ +sfr_b(LCDBM8); /* LCD Blinking Memory 8 */ +sfr_b(LCDBM9); /* LCD Blinking Memory 9 */ +sfr_b(LCDBM10); /* LCD Blinking Memory 10 */ +sfr_b(LCDBM11); /* LCD Blinking Memory 11 */ +sfr_b(LCDBM12); /* LCD Blinking Memory 12 */ +sfr_b(LCDBM13); /* LCD Blinking Memory 13 */ +sfr_b(LCDBM14); /* LCD Blinking Memory 14 */ +sfr_b(LCDBM15); /* LCD Blinking Memory 15 */ +sfr_b(LCDBM16); /* LCD Blinking Memory 16 */ +sfr_b(LCDBM17); /* LCD Blinking Memory 17 */ +sfr_b(LCDBM18); /* LCD Blinking Memory 18 */ +sfr_b(LCDBM19); /* LCD Blinking Memory 19 */ +sfr_b(LCDBM20); /* LCD Blinking Memory 20 */ +sfr_b(LCDBM21); /* LCD Blinking Memory 21 */ +sfr_b(LCDBM22); /* LCD Blinking Memory 22 */ +sfr_b(LCDBM23); /* LCD Blinking Memory 23 */ +sfr_b(LCDBM24); /* LCD Blinking Memory 24 */ + +/* LCDBIV Definitions */ +#define LCDBIV_NONE (0x0000) /* No Interrupt pending */ +#define LCDBIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */ +#define LCDBIV_LCDBLKOFFIFG (0x0004) /* Blink, segments off */ +#define LCDBIV_LCDBLKONIFG (0x0006) /* Blink, segments on */ +#define LCDBIV_LCDFRMIFG (0x0008) /* Frame interrupt */ + +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ +#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_MPY32__ 0x04C0 +#define MPY32_BASE __MSP430_BASEADDRESS_MPY32__ + +sfr_w(MPY); /* Multiply Unsigned/Operand 1 */ +sfr_b(MPY_L); /* Multiply Unsigned/Operand 1 */ +sfr_b(MPY_H); /* Multiply Unsigned/Operand 1 */ +sfr_w(MPYS); /* Multiply Signed/Operand 1 */ +sfr_b(MPYS_L); /* Multiply Signed/Operand 1 */ +sfr_b(MPYS_H); /* Multiply Signed/Operand 1 */ +sfr_w(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */ +sfr_b(MAC_L); /* Multiply Unsigned and Accumulate/Operand 1 */ +sfr_b(MAC_H); /* Multiply Unsigned and Accumulate/Operand 1 */ +sfr_w(MACS); /* Multiply Signed and Accumulate/Operand 1 */ +sfr_b(MACS_L); /* Multiply Signed and Accumulate/Operand 1 */ +sfr_b(MACS_H); /* Multiply Signed and Accumulate/Operand 1 */ +sfr_w(OP2); /* Operand 2 */ +sfr_b(OP2_L); /* Operand 2 */ +sfr_b(OP2_H); /* Operand 2 */ +sfr_w(RESLO); /* Result Low Word */ +sfr_b(RESLO_L); /* Result Low Word */ +sfr_b(RESLO_H); /* Result Low Word */ +sfr_w(RESHI); /* Result High Word */ +sfr_b(RESHI_L); /* Result High Word */ +sfr_b(RESHI_H); /* Result High Word */ +sfr_w(SUMEXT); /* Sum Extend */ +sfr_b(SUMEXT_L); /* Sum Extend */ +sfr_b(SUMEXT_H); /* Sum Extend */ + +sfr_w(MPY32L); /* 32-bit operand 1 - multiply - low word */ +sfr_b(MPY32L_L); /* 32-bit operand 1 - multiply - low word */ +sfr_b(MPY32L_H); /* 32-bit operand 1 - multiply - low word */ +sfr_w(MPY32H); /* 32-bit operand 1 - multiply - high word */ +sfr_b(MPY32H_L); /* 32-bit operand 1 - multiply - high word */ +sfr_b(MPY32H_H); /* 32-bit operand 1 - multiply - high word */ +sfr_w(MPYS32L); /* 32-bit operand 1 - signed multiply - low word */ +sfr_b(MPYS32L_L); /* 32-bit operand 1 - signed multiply - low word */ +sfr_b(MPYS32L_H); /* 32-bit operand 1 - signed multiply - low word */ +sfr_w(MPYS32H); /* 32-bit operand 1 - signed multiply - high word */ +sfr_b(MPYS32H_L); /* 32-bit operand 1 - signed multiply - high word */ +sfr_b(MPYS32H_H); /* 32-bit operand 1 - signed multiply - high word */ +sfr_w(MAC32L); /* 32-bit operand 1 - multiply accumulate - low word */ +sfr_b(MAC32L_L); /* 32-bit operand 1 - multiply accumulate - low word */ +sfr_b(MAC32L_H); /* 32-bit operand 1 - multiply accumulate - low word */ +sfr_w(MAC32H); /* 32-bit operand 1 - multiply accumulate - high word */ +sfr_b(MAC32H_L); /* 32-bit operand 1 - multiply accumulate - high word */ +sfr_b(MAC32H_H); /* 32-bit operand 1 - multiply accumulate - high word */ +sfr_w(MACS32L); /* 32-bit operand 1 - signed multiply accumulate - low word */ +sfr_b(MACS32L_L); /* 32-bit operand 1 - signed multiply accumulate - low word */ +sfr_b(MACS32L_H); /* 32-bit operand 1 - signed multiply accumulate - low word */ +sfr_w(MACS32H); /* 32-bit operand 1 - signed multiply accumulate - high word */ +sfr_b(MACS32H_L); /* 32-bit operand 1 - signed multiply accumulate - high word */ +sfr_b(MACS32H_H); /* 32-bit operand 1 - signed multiply accumulate - high word */ +sfr_w(OP2L); /* 32-bit operand 2 - low word */ +sfr_b(OP2L_L); /* 32-bit operand 2 - low word */ +sfr_b(OP2L_H); /* 32-bit operand 2 - low word */ +sfr_w(OP2H); /* 32-bit operand 2 - high word */ +sfr_b(OP2H_L); /* 32-bit operand 2 - high word */ +sfr_b(OP2H_H); /* 32-bit operand 2 - high word */ +sfr_w(RES0); /* 32x32-bit result 0 - least significant word */ +sfr_b(RES0_L); /* 32x32-bit result 0 - least significant word */ +sfr_b(RES0_H); /* 32x32-bit result 0 - least significant word */ +sfr_w(RES1); /* 32x32-bit result 1 */ +sfr_b(RES1_L); /* 32x32-bit result 1 */ +sfr_b(RES1_H); /* 32x32-bit result 1 */ +sfr_w(RES2); /* 32x32-bit result 2 */ +sfr_b(RES2_L); /* 32x32-bit result 2 */ +sfr_b(RES2_H); /* 32x32-bit result 2 */ +sfr_w(RES3); /* 32x32-bit result 3 - most significant word */ +sfr_b(RES3_L); /* 32x32-bit result 3 - most significant word */ +sfr_b(RES3_H); /* 32x32-bit result 3 - most significant word */ +sfr_w(MPY32CTL0); /* MPY32 Control Register 0 */ +sfr_b(MPY32CTL0_L); /* MPY32 Control Register 0 */ +sfr_b(MPY32CTL0_H); /* MPY32 Control Register 0 */ + +#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ +#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ +#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ +#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ +#define OP2_B OP2_L /* Operand 2 (Byte Access) */ +#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ +#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ +#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ +#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ +#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ +#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ +#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ +#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ +#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ +#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ + +/* MPY32CTL0 Control Bits */ +#define MPYC (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC (0x0004) /* Fractional mode */ +#define MPYSAT (0x0008) /* Saturation mode */ +#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ +#define MPYDLYWRTEN (0x0100) /* Delayed write enable */ +#define MPYDLY32 (0x0200) /* Delayed write mode */ + +/* MPY32CTL0 Control Bits */ +#define MPYC_L (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC_L (0x0004) /* Fractional mode */ +#define MPYSAT_L (0x0008) /* Saturation mode */ +#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ + +/* MPY32CTL0 Control Bits */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */ +#define MPYDLY32_H (0x0002) /* Delayed write mode */ + +#define MPYM_0 (0x0000) /* Multiplier mode: MPY */ +#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */ +#define MPYM_2 (0x0020) /* Multiplier mode: MAC */ +#define MPYM_3 (0x0030) /* Multiplier mode: MACS */ +#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */ +#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */ +#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */ +#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */ + +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200 +#define P1_BASE __MSP430_BASEADDRESS_PORT1_R__ +#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200 +#define P2_BASE __MSP430_BASEADDRESS_PORT2_R__ +#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200 +#define PA_BASE __MSP430_BASEADDRESS_PORTA_R__ +#define __MSP430_HAS_P1SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P2SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_PASEL__ /* Define for DriverLib */ + +sfr_w(PAIN); /* Port A Input */ +sfr_b(PAIN_L); /* Port A Input */ +sfr_b(PAIN_H); /* Port A Input */ +sfr_w(PAOUT); /* Port A Output */ +sfr_b(PAOUT_L); /* Port A Output */ +sfr_b(PAOUT_H); /* Port A Output */ +sfr_w(PADIR); /* Port A Direction */ +sfr_b(PADIR_L); /* Port A Direction */ +sfr_b(PADIR_H); /* Port A Direction */ +sfr_w(PAREN); /* Port A Resistor Enable */ +sfr_b(PAREN_L); /* Port A Resistor Enable */ +sfr_b(PAREN_H); /* Port A Resistor Enable */ +sfr_w(PADS); /* Port A Drive Strenght */ +sfr_b(PADS_L); /* Port A Drive Strenght */ +sfr_b(PADS_H); /* Port A Drive Strenght */ +sfr_w(PASEL); /* Port A Selection */ +sfr_b(PASEL_L); /* Port A Selection */ +sfr_b(PASEL_H); /* Port A Selection */ +sfr_w(PAIES); /* Port A Interrupt Edge Select */ +sfr_b(PAIES_L); /* Port A Interrupt Edge Select */ +sfr_b(PAIES_H); /* Port A Interrupt Edge Select */ +sfr_w(PAIE); /* Port A Interrupt Enable */ +sfr_b(PAIE_L); /* Port A Interrupt Enable */ +sfr_b(PAIE_H); /* Port A Interrupt Enable */ +sfr_w(PAIFG); /* Port A Interrupt Flag */ +sfr_b(PAIFG_L); /* Port A Interrupt Flag */ +sfr_b(PAIFG_H); /* Port A Interrupt Flag */ + + +sfr_w(P1IV); /* Port 1 Interrupt Vector Word */ +sfr_w(P2IV); /* Port 2 Interrupt Vector Word */ +#define P1IN (PAIN_L) /* Port 1 Input */ +#define P1OUT (PAOUT_L) /* Port 1 Output */ +#define P1DIR (PADIR_L) /* Port 1 Direction */ +#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ +#define P1DS (PADS_L) /* Port 1 Drive Strenght */ +#define P1SEL (PASEL_L) /* Port 1 Selection */ +#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ +#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ +#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ + +//Definitions for P1IV +#define P1IV_NONE (0x0000) /* No Interrupt pending */ +#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */ +#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */ +#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */ +#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */ +#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */ +#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */ +#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */ +#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */ + +#define P2IN (PAIN_H) /* Port 2 Input */ +#define P2OUT (PAOUT_H) /* Port 2 Output */ +#define P2DIR (PADIR_H) /* Port 2 Direction */ +#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ +#define P2DS (PADS_H) /* Port 2 Drive Strenght */ +#define P2SEL (PASEL_H) /* Port 2 Selection */ +#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ +#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ +#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ + +//Definitions for P2IV +#define P2IV_NONE (0x0000) /* No Interrupt pending */ +#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */ +#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */ +#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */ +#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */ +#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */ +#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */ +#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */ +#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */ + + +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220 +#define P3_BASE __MSP430_BASEADDRESS_PORT3_R__ +#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220 +#define P4_BASE __MSP430_BASEADDRESS_PORT4_R__ +#define __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220 +#define PB_BASE __MSP430_BASEADDRESS_PORTB_R__ +#define __MSP430_HAS_P3SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P4SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_PBSEL__ /* Define for DriverLib */ + +sfr_w(PBIN); /* Port B Input */ +sfr_b(PBIN_L); /* Port B Input */ +sfr_b(PBIN_H); /* Port B Input */ +sfr_w(PBOUT); /* Port B Output */ +sfr_b(PBOUT_L); /* Port B Output */ +sfr_b(PBOUT_H); /* Port B Output */ +sfr_w(PBDIR); /* Port B Direction */ +sfr_b(PBDIR_L); /* Port B Direction */ +sfr_b(PBDIR_H); /* Port B Direction */ +sfr_w(PBREN); /* Port B Resistor Enable */ +sfr_b(PBREN_L); /* Port B Resistor Enable */ +sfr_b(PBREN_H); /* Port B Resistor Enable */ +sfr_w(PBDS); /* Port B Drive Strenght */ +sfr_b(PBDS_L); /* Port B Drive Strenght */ +sfr_b(PBDS_H); /* Port B Drive Strenght */ +sfr_w(PBSEL); /* Port B Selection */ +sfr_b(PBSEL_L); /* Port B Selection */ +sfr_b(PBSEL_H); /* Port B Selection */ + + +#define P3IN (PBIN_L) /* Port 3 Input */ +#define P3OUT (PBOUT_L) /* Port 3 Output */ +#define P3DIR (PBDIR_L) /* Port 3 Direction */ +#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ +#define P3DS (PBDS_L) /* Port 3 Drive Strenght */ +#define P3SEL (PBSEL_L) /* Port 3 Selection */ + +#define P4IN (PBIN_H) /* Port 4 Input */ +#define P4OUT (PBOUT_H) /* Port 4 Output */ +#define P4DIR (PBDIR_H) /* Port 4 Direction */ +#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ +#define P4DS (PBDS_H) /* Port 4 Drive Strenght */ +#define P4SEL (PBSEL_H) /* Port 4 Selection */ + + +/************************************************************ +* DIGITAL I/O Port5 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240 +#define P5_BASE __MSP430_BASEADDRESS_PORT5_R__ +#define __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240 +#define PC_BASE __MSP430_BASEADDRESS_PORTC_R__ +#define __MSP430_HAS_P5SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_PCSEL__ /* Define for DriverLib */ + +sfr_w(PCIN); /* Port C Input */ +sfr_b(PCIN_L); /* Port C Input */ +sfr_b(PCIN_H); /* Port C Input */ +sfr_w(PCOUT); /* Port C Output */ +sfr_b(PCOUT_L); /* Port C Output */ +sfr_b(PCOUT_H); /* Port C Output */ +sfr_w(PCDIR); /* Port C Direction */ +sfr_b(PCDIR_L); /* Port C Direction */ +sfr_b(PCDIR_H); /* Port C Direction */ +sfr_w(PCREN); /* Port C Resistor Enable */ +sfr_b(PCREN_L); /* Port C Resistor Enable */ +sfr_b(PCREN_H); /* Port C Resistor Enable */ +sfr_w(PCDS); /* Port C Drive Strenght */ +sfr_b(PCDS_L); /* Port C Drive Strenght */ +sfr_b(PCDS_H); /* Port C Drive Strenght */ +sfr_w(PCSEL); /* Port C Selection */ +sfr_b(PCSEL_L); /* Port C Selection */ +sfr_b(PCSEL_H); /* Port C Selection */ + + +#define P5IN (PCIN_L) /* Port 5 Input */ +#define P5OUT (PCOUT_L) /* Port 5 Output */ +#define P5DIR (PCDIR_L) /* Port 5 Direction */ +#define P5REN (PCREN_L) /* Port 5 Resistor Enable */ +#define P5DS (PCDS_L) /* Port 5 Drive Strenght */ +#define P5SEL (PCSEL_L) /* Port 5 Selection */ + + +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320 +#define PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__ + +sfr_w(PJIN); /* Port J Input */ +sfr_b(PJIN_L); /* Port J Input */ +sfr_b(PJIN_H); /* Port J Input */ +sfr_w(PJOUT); /* Port J Output */ +sfr_b(PJOUT_L); /* Port J Output */ +sfr_b(PJOUT_H); /* Port J Output */ +sfr_w(PJDIR); /* Port J Direction */ +sfr_b(PJDIR_L); /* Port J Direction */ +sfr_b(PJDIR_H); /* Port J Direction */ +sfr_w(PJREN); /* Port J Resistor Enable */ +sfr_b(PJREN_L); /* Port J Resistor Enable */ +sfr_b(PJREN_H); /* Port J Resistor Enable */ +sfr_w(PJDS); /* Port J Drive Strenght */ +sfr_b(PJDS_L); /* Port J Drive Strenght */ +sfr_b(PJDS_H); /* Port J Drive Strenght */ + +/************************************************************ +* PORT MAPPING CONTROLLER +************************************************************/ +#define __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT_MAPPING__ 0x01C0 +#define PMAP_CTRL_BASE __MSP430_BASEADDRESS_PORT_MAPPING__ + +sfr_w(PMAPKEYID); /* Port Mapping Key register */ +sfr_b(PMAPKEYID_L); /* Port Mapping Key register */ +sfr_b(PMAPKEYID_H); /* Port Mapping Key register */ +sfr_w(PMAPCTL); /* Port Mapping control register */ +sfr_b(PMAPCTL_L); /* Port Mapping control register */ +sfr_b(PMAPCTL_H); /* Port Mapping control register */ + +#define PMAPKEY (0x2D52) /* Port Mapping Key */ +#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */ +#define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */ + +/************************************************************ +* PORT 1 MAPPING CONTROLLER +************************************************************/ +#define __MSP430_HAS_PORT1_MAPPING__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT1_MAPPING__ 0x01C8 +#define P1MAP_BASE __MSP430_BASEADDRESS_PORT1_MAPPING__ + +sfr_w(P1MAP01); /* Port P1.0/1 mapping register */ +sfr_b(P1MAP01_L); /* Port P1.0/1 mapping register */ +sfr_b(P1MAP01_H); /* Port P1.0/1 mapping register */ +sfr_w(P1MAP23); /* Port P1.2/3 mapping register */ +sfr_b(P1MAP23_L); /* Port P1.2/3 mapping register */ +sfr_b(P1MAP23_H); /* Port P1.2/3 mapping register */ +sfr_w(P1MAP45); /* Port P1.4/5 mapping register */ +sfr_b(P1MAP45_L); /* Port P1.4/5 mapping register */ +sfr_b(P1MAP45_H); /* Port P1.4/5 mapping register */ +sfr_w(P1MAP67); /* Port P1.6/7 mapping register */ +sfr_b(P1MAP67_L); /* Port P1.6/7 mapping register */ +sfr_b(P1MAP67_H); /* Port P1.6/7 mapping register */ + +#define P1MAP0 P1MAP01_L /* Port P1.0 mapping register */ +#define P1MAP1 P1MAP01_H /* Port P1.1 mapping register */ +#define P1MAP2 P1MAP23_L /* Port P1.2 mapping register */ +#define P1MAP3 P1MAP23_H /* Port P1.3 mapping register */ +#define P1MAP4 P1MAP45_L /* Port P1.4 mapping register */ +#define P1MAP5 P1MAP45_H /* Port P1.5 mapping register */ +#define P1MAP6 P1MAP67_L /* Port P1.6 mapping register */ +#define P1MAP7 P1MAP67_H /* Port P1.7 mapping register */ + +/************************************************************ +* PORT 2 MAPPING CONTROLLER +************************************************************/ +#define __MSP430_HAS_PORT2_MAPPING__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT2_MAPPING__ 0x01D0 +#define P2MAP_BASE __MSP430_BASEADDRESS_PORT2_MAPPING__ + +sfr_w(P2MAP01); /* Port P2.0/1 mapping register */ +sfr_b(P2MAP01_L); /* Port P2.0/1 mapping register */ +sfr_b(P2MAP01_H); /* Port P2.0/1 mapping register */ +sfr_w(P2MAP23); /* Port P2.2/3 mapping register */ +sfr_b(P2MAP23_L); /* Port P2.2/3 mapping register */ +sfr_b(P2MAP23_H); /* Port P2.2/3 mapping register */ +sfr_w(P2MAP45); /* Port P2.4/5 mapping register */ +sfr_b(P2MAP45_L); /* Port P2.4/5 mapping register */ +sfr_b(P2MAP45_H); /* Port P2.4/5 mapping register */ +sfr_w(P2MAP67); /* Port P2.6/7 mapping register */ +sfr_b(P2MAP67_L); /* Port P2.6/7 mapping register */ +sfr_b(P2MAP67_H); /* Port P2.6/7 mapping register */ + +#define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */ +#define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */ +#define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */ +#define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */ +#define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */ +#define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */ +#define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */ +#define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */ + +/************************************************************ +* PORT 3 MAPPING CONTROLLER +************************************************************/ +#define __MSP430_HAS_PORT3_MAPPING__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT3_MAPPING__ 0x01D8 +#define P3MAP_BASE __MSP430_BASEADDRESS_PORT3_MAPPING__ + +sfr_w(P3MAP01); /* Port P3.0/1 mapping register */ +sfr_b(P3MAP01_L); /* Port P3.0/1 mapping register */ +sfr_b(P3MAP01_H); /* Port P3.0/1 mapping register */ +sfr_w(P3MAP23); /* Port P3.2/3 mapping register */ +sfr_b(P3MAP23_L); /* Port P3.2/3 mapping register */ +sfr_b(P3MAP23_H); /* Port P3.2/3 mapping register */ +sfr_w(P3MAP45); /* Port P3.4/5 mapping register */ +sfr_b(P3MAP45_L); /* Port P3.4/5 mapping register */ +sfr_b(P3MAP45_H); /* Port P3.4/5 mapping register */ +sfr_w(P3MAP67); /* Port P3.6/7 mapping register */ +sfr_b(P3MAP67_L); /* Port P3.6/7 mapping register */ +sfr_b(P3MAP67_H); /* Port P3.6/7 mapping register */ + +#define P3MAP0 P3MAP01_L /* Port P3.0 mapping register */ +#define P3MAP1 P3MAP01_H /* Port P3.1 mapping register */ +#define P3MAP2 P3MAP23_L /* Port P3.2 mapping register */ +#define P3MAP3 P3MAP23_H /* Port P3.3 mapping register */ +#define P3MAP4 P3MAP45_L /* Port P3.4 mapping register */ +#define P3MAP5 P3MAP45_H /* Port P3.5 mapping register */ +#define P3MAP6 P3MAP67_L /* Port P3.6 mapping register */ +#define P3MAP7 P3MAP67_H /* Port P3.7 mapping register */ + +#define PM_NONE 0 +#define PM_CBOUT0 1 +#define PM_TA0CLK 1 +#define PM_CBOUT1 2 +#define PM_TA1CLK 2 +#define PM_ACLK 3 +#define PM_MCLK 4 +#define PM_SMCLK 5 +#define PM_RTCCLK 6 +#define PM_MODCLK 7 +#define PM_DMAE0 7 +#define PM_SVMOUT 8 +#define PM_TA0CCR0A 9 +#define PM_TA0CCR1A 10 +#define PM_TA0CCR2A 11 +#define PM_TA0CCR3A 12 +#define PM_TA0CCR4A 13 +#define PM_TA1CCR0A 14 +#define PM_TA1CCR1A 15 +#define PM_TA1CCR2A 16 +#define PM_UCA0RXD 17 +#define PM_UCA0SOMI 17 +#define PM_UCA0TXD 18 +#define PM_UCA0SIMO 18 +#define PM_UCA0CLK 19 +#define PM_UCB0STE 19 +#define PM_UCB0SOMI 20 +#define PM_UCB0SCL 20 +#define PM_UCB0SIMO 21 +#define PM_UCB0SDA 21 +#define PM_UCB0CLK 22 +#define PM_UCA0STE 22 +#define PM_RFGDO0 23 +#define PM_RFGDO1 24 +#define PM_RFGDO2 25 +#define PM_ANALOG 31 + +/************************************************************ +* PMM - Power Management System +************************************************************/ +#define __MSP430_HAS_PMM__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PMM__ 0x0120 +#define PMM_BASE __MSP430_BASEADDRESS_PMM__ + +sfr_w(PMMCTL0); /* PMM Control 0 */ +sfr_b(PMMCTL0_L); /* PMM Control 0 */ +sfr_b(PMMCTL0_H); /* PMM Control 0 */ +sfr_w(PMMCTL1); /* PMM Control 1 */ +sfr_b(PMMCTL1_L); /* PMM Control 1 */ +sfr_b(PMMCTL1_H); /* PMM Control 1 */ +sfr_w(SVSMHCTL); /* SVS and SVM high side control register */ +sfr_b(SVSMHCTL_L); /* SVS and SVM high side control register */ +sfr_b(SVSMHCTL_H); /* SVS and SVM high side control register */ +sfr_w(SVSMLCTL); /* SVS and SVM low side control register */ +sfr_b(SVSMLCTL_L); /* SVS and SVM low side control register */ +sfr_b(SVSMLCTL_H); /* SVS and SVM low side control register */ +sfr_w(SVSMIO); /* SVSIN and SVSOUT control register */ +sfr_b(SVSMIO_L); /* SVSIN and SVSOUT control register */ +sfr_b(SVSMIO_H); /* SVSIN and SVSOUT control register */ +sfr_w(PMMIFG); /* PMM Interrupt Flag */ +sfr_b(PMMIFG_L); /* PMM Interrupt Flag */ +sfr_b(PMMIFG_H); /* PMM Interrupt Flag */ +sfr_w(PMMRIE); /* PMM and RESET Interrupt Enable */ +sfr_b(PMMRIE_L); /* PMM and RESET Interrupt Enable */ +sfr_b(PMMRIE_H); /* PMM and RESET Interrupt Enable */ + +#define PMMPW (0xA500) /* PMM Register Write Password */ +#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR (0x0004) /* PMM Software BOR */ +#define PMMSWPOR (0x0008) /* PMM Software POR */ +#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */ +#define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR_L (0x0004) /* PMM Software BOR */ +#define PMMSWPOR_L (0x0008) /* PMM Software POR */ +#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */ +#define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */ + +#define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */ +#define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */ +#define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */ +#define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */ + +/* PMMCTL1 Control Bits */ +#define PMMREFMD (0x0001) /* PMM Reference Mode */ +#define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ + +/* PMMCTL1 Control Bits */ +#define PMMREFMD_L (0x0001) /* PMM Reference Mode */ +#define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */ +#define SVSHMD (0x0010) /* SVS high side mode */ +#define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */ +#define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */ +#define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE (0x0400) /* SVS high side enable */ +#define SVSHFP (0x0800) /* SVS high side full performace mode */ +#define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */ +#define SVMHE (0x4000) /* SVM high side enable */ +#define SVMHFP (0x8000) /* SVM high side full performace mode */ + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */ +#define SVSHMD_L (0x0010) /* SVS high side mode */ +#define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */ +#define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */ + +/* SVSMHCTL Control Bits */ +#define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE_H (0x0004) /* SVS high side enable */ +#define SVSHFP_H (0x0008) /* SVS high side full performace mode */ +#define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */ +#define SVMHE_H (0x0040) /* SVM high side enable */ +#define SVMHFP_H (0x0080) /* SVM high side full performace mode */ + +#define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */ +#define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */ +#define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */ +#define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */ +#define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */ +#define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */ +#define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */ +#define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */ + +#define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */ +#define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */ +#define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */ +#define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */ + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */ +#define SVSLMD (0x0010) /* SVS low side mode */ +#define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */ +#define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */ +#define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE (0x0400) /* SVS low side enable */ +#define SVSLFP (0x0800) /* SVS low side full performace mode */ +#define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */ +#define SVMLE (0x4000) /* SVM low side enable */ +#define SVMLFP (0x8000) /* SVM low side full performace mode */ + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */ +#define SVSLMD_L (0x0010) /* SVS low side mode */ +#define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */ +#define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */ + +/* SVSMLCTL Control Bits */ +#define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE_H (0x0004) /* SVS low side enable */ +#define SVSLFP_H (0x0008) /* SVS low side full performace mode */ +#define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */ +#define SVMLE_H (0x0040) /* SVM low side enable */ +#define SVMLFP_H (0x0080) /* SVM low side full performace mode */ + +#define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */ +#define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */ +#define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */ +#define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */ +#define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */ +#define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */ +#define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */ +#define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */ + +#define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */ +#define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */ +#define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */ +#define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */ + +/* SVSMIO Control Bits */ +#define SVMLOE (0x0008) /* SVM low side output enable */ +#define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */ +#define SVMHOE (0x0800) /* SVM high side output enable */ +#define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */ + +/* SVSMIO Control Bits */ +#define SVMLOE_L (0x0008) /* SVM low side output enable */ +#define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */ + +/* SVSMIO Control Bits */ +#define SVMHOE_H (0x0008) /* SVM high side output enable */ +#define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */ + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG (0x0002) /* SVM low side interrupt flag */ +#define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG (0x0020) /* SVM high side interrupt flag */ +#define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ +#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */ +#define SVSHIFG (0x1000) /* SVS low side interrupt flag */ +#define SVSLIFG (0x2000) /* SVS high side interrupt flag */ +#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */ + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */ +#define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */ +#define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */ +#define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */ +#define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */ +#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */ + +#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */ + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE (0x0002) /* SVM low side interrupt enable */ +#define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE (0x0020) /* SVM high side interrupt enable */ +#define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ +#define SVSLPE (0x0100) /* SVS low side POR enable */ +#define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE (0x1000) /* SVS high side POR enable */ +#define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE_L (0x0002) /* SVM low side interrupt enable */ +#define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE_L (0x0020) /* SVM high side interrupt enable */ +#define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSLPE_H (0x0001) /* SVS low side POR enable */ +#define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE_H (0x0010) /* SVS high side POR enable */ +#define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */ + +/************************************************************* +* RAM Control Module +*************************************************************/ +#define __MSP430_HAS_RC__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_RC__ 0x0158 +#define RAM_BASE __MSP430_BASEADDRESS_RC__ + +sfr_w(RCCTL0); /* Ram Controller Control Register */ +sfr_b(RCCTL0_L); /* Ram Controller Control Register */ +sfr_b(RCCTL0_H); /* Ram Controller Control Register */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */ + +#define RCKEY (0x5A00) + +/************************************************************ +* Shared Reference +************************************************************/ +#define __MSP430_HAS_REF__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_REF__ 0x01B0 +#define REF_BASE __MSP430_BASEADDRESS_REF__ + +sfr_w(REFCTL0); /* REF Shared Reference control register 0 */ +sfr_b(REFCTL0_L); /* REF Shared Reference control register 0 */ +sfr_b(REFCTL0_H); /* REF Shared Reference control register 0 */ + +/* REFCTL0 Control Bits */ +#define REFON (0x0001) /* REF Reference On */ +#define REFOUT (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFMSTR (0x0080) /* REF Master Control */ +#define REFGENACT (0x0100) /* REF Reference generator active */ +#define REFBGACT (0x0200) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400) /* REF Reference generator busy */ +#define BGMODE (0x0800) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001) /* REF Reference On */ +#define REFOUT_L (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFMSTR_L (0x0080) /* REF Master Control */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0004) /* Reserved */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFGENACT_H (0x0001) /* REF Reference generator active */ +#define REFBGACT_H (0x0002) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */ +#define BGMODE_H (0x0008) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */ +#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */ + +/************************************************************ +* Real Time Clock +************************************************************/ +#define __MSP430_HAS_RTC__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_RTC__ 0x04A0 +#define RTC_A_BASE __MSP430_BASEADDRESS_RTC__ + +sfr_w(RTCCTL01); /* Real Timer Control 0/1 */ +sfr_b(RTCCTL01_L); /* Real Timer Control 0/1 */ +sfr_b(RTCCTL01_H); /* Real Timer Control 0/1 */ +sfr_w(RTCCTL23); /* Real Timer Control 2/3 */ +sfr_b(RTCCTL23_L); /* Real Timer Control 2/3 */ +sfr_b(RTCCTL23_H); /* Real Timer Control 2/3 */ +sfr_w(RTCPS0CTL); /* Real Timer Prescale Timer 0 Control */ +sfr_b(RTCPS0CTL_L); /* Real Timer Prescale Timer 0 Control */ +sfr_b(RTCPS0CTL_H); /* Real Timer Prescale Timer 0 Control */ +sfr_w(RTCPS1CTL); /* Real Timer Prescale Timer 1 Control */ +sfr_b(RTCPS1CTL_L); /* Real Timer Prescale Timer 1 Control */ +sfr_b(RTCPS1CTL_H); /* Real Timer Prescale Timer 1 Control */ +sfr_w(RTCPS); /* Real Timer Prescale Timer Control */ +sfr_b(RTCPS_L); /* Real Timer Prescale Timer Control */ +sfr_b(RTCPS_H); /* Real Timer Prescale Timer Control */ +sfr_w(RTCIV); /* Real Time Clock Interrupt Vector */ +sfr_w(RTCTIM0); /* Real Time Clock Time 0 */ +sfr_b(RTCTIM0_L); /* Real Time Clock Time 0 */ +sfr_b(RTCTIM0_H); /* Real Time Clock Time 0 */ +sfr_w(RTCTIM1); /* Real Time Clock Time 1 */ +sfr_b(RTCTIM1_L); /* Real Time Clock Time 1 */ +sfr_b(RTCTIM1_H); /* Real Time Clock Time 1 */ +sfr_w(RTCDATE); /* Real Time Clock Date */ +sfr_b(RTCDATE_L); /* Real Time Clock Date */ +sfr_b(RTCDATE_H); /* Real Time Clock Date */ +sfr_w(RTCYEAR); /* Real Time Clock Year */ +sfr_b(RTCYEAR_L); /* Real Time Clock Year */ +sfr_b(RTCYEAR_H); /* Real Time Clock Year */ +sfr_w(RTCAMINHR); /* Real Time Clock Alarm Min/Hour */ +sfr_b(RTCAMINHR_L); /* Real Time Clock Alarm Min/Hour */ +sfr_b(RTCAMINHR_H); /* Real Time Clock Alarm Min/Hour */ +sfr_w(RTCADOWDAY); /* Real Time Clock Alarm day of week/day */ +sfr_b(RTCADOWDAY_L); /* Real Time Clock Alarm day of week/day */ +sfr_b(RTCADOWDAY_H); /* Real Time Clock Alarm day of week/day */ + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000) /* RTC Hold */ +#define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x1000) /* RTC Ready */ +#define RTCSSEL1 (0x0800) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0400) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0200) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100) /* RTC Time Event 0 */ +//#define Reserved (0x0080) +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008) +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define Reserved (0x0080) +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008) +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040) /* RTC Hold */ +#define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_H (0x0010) /* RTC Ready */ +#define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */ +//#define Reserved (0x0080) +//#define Reserved (0x0008) + +#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */ +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040) + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +#define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +#define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */ +#define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */ +#define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */ +#define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */ +#define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */ +#define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */ +#define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */ +#define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */ +#define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */ +#define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */ +#define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */ +#define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */ +#define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */ +#define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */ +#define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */ + +#define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */ +#define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */ +#define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */ +#define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ + +#define RTC_A_VECTOR RTC_VECTOR /* 0xFFDC RTC */ + +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ +#define __MSP430_HAS_SFR__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_SFR__ 0x0100 +#define SFR_BASE __MSP430_BASEADDRESS_SFR__ + +sfr_w(SFRIE1); /* Interrupt Enable 1 */ +sfr_b(SFRIE1_L); /* Interrupt Enable 1 */ +sfr_b(SFRIE1_H); /* Interrupt Enable 1 */ + +/* SFRIE1 Control Bits */ +#define WDTIE (0x0001) /* WDT Interrupt Enable */ +#define OFIE (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE (0x0010) /* NMI Interrupt Enable */ +#define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */ +#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +#define WDTIE_L (0x0001) /* WDT Interrupt Enable */ +#define OFIE_L (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE_L (0x0010) /* NMI Interrupt Enable */ +#define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */ +#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +sfr_w(SFRIFG1); /* Interrupt Flag 1 */ +sfr_b(SFRIFG1_L); /* Interrupt Flag 1 */ +sfr_b(SFRIFG1_H); /* Interrupt Flag 1 */ +/* SFRIFG1 Control Bits */ +#define WDTIFG (0x0001) /* WDT Interrupt Flag */ +#define OFIFG (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */ +#define OFIFG_L (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +sfr_w(SFRRPCR); /* RESET Pin Control Register */ +sfr_b(SFRRPCR_L); /* RESET Pin Control Register */ +sfr_b(SFRRPCR_H); /* RESET Pin Control Register */ +/* SFRRPCR Control Bits */ +#define SYSNMI (0x0001) /* NMI select */ +#define SYSNMIIES (0x0002) /* NMI edge select */ +#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */ + +#define SYSNMI_L (0x0001) /* NMI select */ +#define SYSNMIIES_L (0x0002) /* NMI edge select */ +#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */ + +/************************************************************ +* SYS - System Module +************************************************************/ +#define __MSP430_HAS_SYS__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_SYS__ 0x0180 +#define SYS_BASE __MSP430_BASEADDRESS_SYS__ + +sfr_w(SYSCTL); /* System control */ +sfr_b(SYSCTL_L); /* System control */ +sfr_b(SYSCTL_H); /* System control */ +sfr_w(SYSBSLC); /* Boot strap configuration area */ +sfr_b(SYSBSLC_L); /* Boot strap configuration area */ +sfr_b(SYSBSLC_H); /* Boot strap configuration area */ +sfr_w(SYSJMBC); /* JTAG mailbox control */ +sfr_b(SYSJMBC_L); /* JTAG mailbox control */ +sfr_b(SYSJMBC_H); /* JTAG mailbox control */ +sfr_w(SYSJMBI0); /* JTAG mailbox input 0 */ +sfr_b(SYSJMBI0_L); /* JTAG mailbox input 0 */ +sfr_b(SYSJMBI0_H); /* JTAG mailbox input 0 */ +sfr_w(SYSJMBI1); /* JTAG mailbox input 1 */ +sfr_b(SYSJMBI1_L); /* JTAG mailbox input 1 */ +sfr_b(SYSJMBI1_H); /* JTAG mailbox input 1 */ +sfr_w(SYSJMBO0); /* JTAG mailbox output 0 */ +sfr_b(SYSJMBO0_L); /* JTAG mailbox output 0 */ +sfr_b(SYSJMBO0_H); /* JTAG mailbox output 0 */ +sfr_w(SYSJMBO1); /* JTAG mailbox output 1 */ +sfr_b(SYSJMBO1_L); /* JTAG mailbox output 1 */ +sfr_b(SYSJMBO1_H); /* JTAG mailbox output 1 */ + +sfr_w(SYSBERRIV); /* Bus Error vector generator */ +sfr_b(SYSBERRIV_L); /* Bus Error vector generator */ +sfr_b(SYSBERRIV_H); /* Bus Error vector generator */ +sfr_w(SYSUNIV); /* User NMI vector generator */ +sfr_b(SYSUNIV_L); /* User NMI vector generator */ +sfr_b(SYSUNIV_H); /* User NMI vector generator */ +sfr_w(SYSSNIV); /* System NMI vector generator */ +sfr_b(SYSSNIV_L); /* System NMI vector generator */ +sfr_b(SYSSNIV_H); /* System NMI vector generator */ +sfr_w(SYSRSTIV); /* Reset vector generator */ +sfr_b(SYSRSTIV_L); /* Reset vector generator */ +sfr_b(SYSRSTIV_H); /* Reset vector generator */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */ +#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */ +#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + + +/* SYSUNIV Definitions */ +#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */ +#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */ +#define SYSUNIV_ACCVIFG (0x0006) /* SYSUNIV : Access Violation - ACCVIFG */ +#define SYSUNIV_SYSBERRIV (0x0008) /* SYSUNIV : Bus Error - SYSBERRIV */ + +/* SYSSNIV Definitions */ +#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSSNIV_SVMLIFG (0x0002) /* SYSSNIV : SVMLIFG */ +#define SYSSNIV_SVMHIFG (0x0004) /* SYSSNIV : SVMHIFG */ +#define SYSSNIV_DLYLIFG (0x0006) /* SYSSNIV : DLYLIFG */ +#define SYSSNIV_DLYHIFG (0x0008) /* SYSSNIV : DLYHIFG */ +#define SYSSNIV_VMAIFG (0x000A) /* SYSSNIV : VMAIFG */ +#define SYSSNIV_JMBINIFG (0x000C) /* SYSSNIV : JMBINIFG */ +#define SYSSNIV_JMBOUTIFG (0x000E) /* SYSSNIV : JMBOUTIFG */ +#define SYSSNIV_VLRLIFG (0x0010) /* SYSSNIV : VLRLIFG */ +#define SYSSNIV_VLRHIFG (0x0012) /* SYSSNIV : VLRHIFG */ + +/* SYSRSTIV Definitions */ +#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */ +#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */ +#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */ +#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */ +#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */ +#define SYSRSTIV_SVSL (0x000C) /* SYSRSTIV : SVSL */ +#define SYSRSTIV_SVSH (0x000E) /* SYSRSTIV : SVSH */ +#define SYSRSTIV_SVML_OVP (0x0010) /* SYSRSTIV : SVML_OVP */ +#define SYSRSTIV_SVMH_OVP (0x0012) /* SYSRSTIV : SVMH_OVP */ +#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */ +#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */ +#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */ +#define SYSRSTIV_KEYV (0x001A) /* SYSRSTIV : Flash Key violation */ +#define SYSRSTIV_PLLUL (0x001C) /* SYSRSTIV : PLL unlock */ +#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */ +#define SYSRSTIV_PMMKEY (0x0020) /* SYSRSTIV : PMMKEY violation */ + +#define SYSRSTIV_PSSKEY (0x0020) /* SYSRSTIV : Legacy: PMMKEY violation */ + +/************************************************************ +* Timer0_A5 +************************************************************/ +#define __MSP430_HAS_T0A5__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_T0A5__ 0x0340 +#define TIMER_A0_BASE __MSP430_BASEADDRESS_T0A5__ + +sfr_w(TA0CTL); /* Timer0_A5 Control */ +sfr_w(TA0CCTL0); /* Timer0_A5 Capture/Compare Control 0 */ +sfr_w(TA0CCTL1); /* Timer0_A5 Capture/Compare Control 1 */ +sfr_w(TA0CCTL2); /* Timer0_A5 Capture/Compare Control 2 */ +sfr_w(TA0CCTL3); /* Timer0_A5 Capture/Compare Control 3 */ +sfr_w(TA0CCTL4); /* Timer0_A5 Capture/Compare Control 4 */ +sfr_w(TA0R); /* Timer0_A5 */ +sfr_w(TA0CCR0); /* Timer0_A5 Capture/Compare 0 */ +sfr_w(TA0CCR1); /* Timer0_A5 Capture/Compare 1 */ +sfr_w(TA0CCR2); /* Timer0_A5 Capture/Compare 2 */ +sfr_w(TA0CCR3); /* Timer0_A5 Capture/Compare 3 */ +sfr_w(TA0CCR4); /* Timer0_A5 Capture/Compare 4 */ +sfr_w(TA0IV); /* Timer0_A5 Interrupt Vector Word */ +sfr_w(TA0EX0); /* Timer0_A5 Expansion Register 0 */ + +/* TAxCTL Control Bits */ +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */ +#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ +#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */ +#define MC__CONTINOUS (0x0020) /* Legacy define */ +#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */ + +/* TAxCCTLx Control Bits */ +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ +#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ +#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ +#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ +#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ +#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ + +/* TAxEX0 Control Bits */ +#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */ +#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */ +#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */ + +#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */ +#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */ +#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */ +#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */ +#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */ +#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */ +#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */ +#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */ + +/* T0A5IV Definitions */ +#define TA0IV_NONE (0x0000) /* No Interrupt pending */ +#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_TACCR3 (0x0006) /* TA0CCR3_CCIFG */ +#define TA0IV_TACCR4 (0x0008) /* TA0CCR4_CCIFG */ +#define TA0IV_5 (0x000A) /* Reserved */ +#define TA0IV_6 (0x000C) /* Reserved */ +#define TA0IV_TAIFG (0x000E) /* TA0IFG */ + +/* Legacy Defines */ +#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_TA0CCR3 (0x0006) /* TA0CCR3_CCIFG */ +#define TA0IV_TA0CCR4 (0x0008) /* TA0CCR4_CCIFG */ +#define TA0IV_TA0IFG (0x000E) /* TA0IFG */ + +/************************************************************ +* Timer1_A3 +************************************************************/ +#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_T1A3__ 0x0380 +#define TIMER_A1_BASE __MSP430_BASEADDRESS_T1A3__ + +sfr_w(TA1CTL); /* Timer1_A3 Control */ +sfr_w(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */ +sfr_w(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */ +sfr_w(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */ +sfr_w(TA1R); /* Timer1_A3 */ +sfr_w(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */ +sfr_w(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */ +sfr_w(TA1CCR2); /* Timer1_A3 Capture/Compare 2 */ +sfr_w(TA1IV); /* Timer1_A3 Interrupt Vector Word */ +sfr_w(TA1EX0); /* Timer1_A3 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TA1IV Definitions */ +#define TA1IV_NONE (0x0000) /* No Interrupt pending */ +#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_3 (0x0006) /* Reserved */ +#define TA1IV_4 (0x0008) /* Reserved */ +#define TA1IV_5 (0x000A) /* Reserved */ +#define TA1IV_6 (0x000C) /* Reserved */ +#define TA1IV_TAIFG (0x000E) /* TA1IFG */ + +/* Legacy Defines */ +#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_TA1IFG (0x000E) /* TA1IFG */ + +/************************************************************ +* UNIFIED CLOCK SYSTEM FOR Radio Devices +************************************************************/ +#define __MSP430_HAS_UCS_RF__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_UCS_RF__ 0x0160 +#define UCS_BASE __MSP430_BASEADDRESS_UCS_RF__ + +sfr_w(UCSCTL0); /* UCS Control Register 0 */ +sfr_b(UCSCTL0_L); /* UCS Control Register 0 */ +sfr_b(UCSCTL0_H); /* UCS Control Register 0 */ +sfr_w(UCSCTL1); /* UCS Control Register 1 */ +sfr_b(UCSCTL1_L); /* UCS Control Register 1 */ +sfr_b(UCSCTL1_H); /* UCS Control Register 1 */ +sfr_w(UCSCTL2); /* UCS Control Register 2 */ +sfr_b(UCSCTL2_L); /* UCS Control Register 2 */ +sfr_b(UCSCTL2_H); /* UCS Control Register 2 */ +sfr_w(UCSCTL3); /* UCS Control Register 3 */ +sfr_b(UCSCTL3_L); /* UCS Control Register 3 */ +sfr_b(UCSCTL3_H); /* UCS Control Register 3 */ +sfr_w(UCSCTL4); /* UCS Control Register 4 */ +sfr_b(UCSCTL4_L); /* UCS Control Register 4 */ +sfr_b(UCSCTL4_H); /* UCS Control Register 4 */ +sfr_w(UCSCTL5); /* UCS Control Register 5 */ +sfr_b(UCSCTL5_L); /* UCS Control Register 5 */ +sfr_b(UCSCTL5_H); /* UCS Control Register 5 */ +sfr_w(UCSCTL6); /* UCS Control Register 6 */ +sfr_b(UCSCTL6_L); /* UCS Control Register 6 */ +sfr_b(UCSCTL6_H); /* UCS Control Register 6 */ +sfr_w(UCSCTL7); /* UCS Control Register 7 */ +sfr_b(UCSCTL7_L); /* UCS Control Register 7 */ +sfr_b(UCSCTL7_H); /* UCS Control Register 7 */ +sfr_w(UCSCTL8); /* UCS Control Register 8 */ +sfr_b(UCSCTL8_L); /* UCS Control Register 8 */ +sfr_b(UCSCTL8_H); /* UCS Control Register 8 */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */ +#define DCO0 (0x0100) /* DCO TAP Bit : 0 */ +#define DCO1 (0x0200) /* DCO TAP Bit : 1 */ +#define DCO2 (0x0400) /* DCO TAP Bit : 2 */ +#define DCO3 (0x0800) /* DCO TAP Bit : 3 */ +#define DCO4 (0x1000) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */ +#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */ +#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */ +#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */ +#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD_L (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */ +#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */ +#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */ +#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */ +#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */ +#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */ +#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */ +#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */ + +/* UCSCTL2 Control Bits */ +#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */ +#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */ +#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */ +#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */ +#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */ +#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */ +#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */ +#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */ +#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */ +#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */ +#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */ +#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */ +#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */ +#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */ +#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */ +#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */ +#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */ +#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */ +#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */ +#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */ +#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */ +#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */ +#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */ +#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */ +#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */ +#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */ +#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */ +#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */ + +/* UCSCTL4 Control Bits */ +#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define SELM_0 (0x0000) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007) /* MCLK Source Select 7 */ +#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */ +#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ +#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */ +#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ +#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */ +#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */ + +#define SELS_0 (0x0000) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070) /* SMCLK Source Select 7 */ +#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */ +#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ +#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */ +#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ +#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */ +#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */ + +#define SELA_0 (0x0000) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700) /* ACLK Source Select 7 */ +#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */ +#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ +#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */ +#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */ +#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */ +#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */ + +/* UCSCTL5 Control Bits */ +#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ +#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */ +#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */ +#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ +#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */ +#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */ +#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ +#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */ +#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */ +#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ + +#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */ +#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */ +#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */ +#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */ +#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */ +#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */ +#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */ +#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */ +#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */ +#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */ +#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */ +#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */ +#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */ +#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF (0x0002) /* SMCLK Off */ +#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */ +#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF_L (0x0002) /* SMCLK Off */ +#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */ +#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */ +#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */ +#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */ +#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */ +#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */ +#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */ +#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG_L (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/************************************************************ +* USCI A0 +************************************************************/ +#define __MSP430_HAS_USCI_A0__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_USCI_A0__ 0x05C0 +#define USCI_A0_BASE __MSP430_BASEADDRESS_USCI_A0__ + +sfr_w(UCA0CTLW0); /* USCI A0 Control Word Register 0 */ +sfr_b(UCA0CTLW0_L); /* USCI A0 Control Word Register 0 */ +sfr_b(UCA0CTLW0_H); /* USCI A0 Control Word Register 0 */ +#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */ +#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */ +sfr_w(UCA0BRW); /* USCI A0 Baud Word Rate 0 */ +sfr_b(UCA0BRW_L); /* USCI A0 Baud Word Rate 0 */ +sfr_b(UCA0BRW_H); /* USCI A0 Baud Word Rate 0 */ +#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */ +#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */ +sfr_b(UCA0MCTL); /* USCI A0 Modulation Control */ +sfr_b(UCA0STAT); /* USCI A0 Status Register */ +sfr_b(UCA0RXBUF); /* USCI A0 Receive Buffer */ +sfr_b(UCA0TXBUF); /* USCI A0 Transmit Buffer */ +sfr_b(UCA0ABCTL); /* USCI A0 LIN Control */ +sfr_w(UCA0IRCTL); /* USCI A0 IrDA Transmit Control */ +sfr_b(UCA0IRCTL_L); /* USCI A0 IrDA Transmit Control */ +sfr_b(UCA0IRCTL_H); /* USCI A0 IrDA Transmit Control */ +#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */ +#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */ +sfr_w(UCA0ICTL); /* USCI A0 Interrupt Enable Register */ +sfr_b(UCA0ICTL_L); /* USCI A0 Interrupt Enable Register */ +sfr_b(UCA0ICTL_H); /* USCI A0 Interrupt Enable Register */ +#define UCA0IE UCA0ICTL_L /* USCI A0 Interrupt Enable Register */ +#define UCA0IFG UCA0ICTL_H /* USCI A0 Interrupt Flags Register */ +sfr_w(UCA0IV); /* USCI A0 Interrupt Vector Register */ + + +/************************************************************ +* USCI B0 +************************************************************/ +#define __MSP430_HAS_USCI_B0__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_USCI_B0__ 0x05E0 +#define USCI_B0_BASE __MSP430_BASEADDRESS_USCI_B0__ + + +sfr_w(UCB0CTLW0); /* USCI B0 Control Word Register 0 */ +sfr_b(UCB0CTLW0_L); /* USCI B0 Control Word Register 0 */ +sfr_b(UCB0CTLW0_H); /* USCI B0 Control Word Register 0 */ +#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */ +#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */ +sfr_w(UCB0BRW); /* USCI B0 Baud Word Rate 0 */ +sfr_b(UCB0BRW_L); /* USCI B0 Baud Word Rate 0 */ +sfr_b(UCB0BRW_H); /* USCI B0 Baud Word Rate 0 */ +#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */ +#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */ +sfr_b(UCB0STAT); /* USCI B0 Status Register */ +sfr_b(UCB0RXBUF); /* USCI B0 Receive Buffer */ +sfr_b(UCB0TXBUF); /* USCI B0 Transmit Buffer */ +sfr_w(UCB0I2COA); /* USCI B0 I2C Own Address */ +sfr_b(UCB0I2COA_L); /* USCI B0 I2C Own Address */ +sfr_b(UCB0I2COA_H); /* USCI B0 I2C Own Address */ +sfr_w(UCB0I2CSA); /* USCI B0 I2C Slave Address */ +sfr_b(UCB0I2CSA_L); /* USCI B0 I2C Slave Address */ +sfr_b(UCB0I2CSA_H); /* USCI B0 I2C Slave Address */ +sfr_w(UCB0ICTL); /* USCI B0 Interrupt Enable Register */ +sfr_b(UCB0ICTL_L); /* USCI B0 Interrupt Enable Register */ +sfr_b(UCB0ICTL_H); /* USCI B0 Interrupt Enable Register */ +#define UCB0IE UCB0ICTL_L /* USCI B0 Interrupt Enable Register */ +#define UCB0IFG UCB0ICTL_H /* USCI B0 Interrupt Flags Register */ +sfr_w(UCB0IV); /* USCI B0 Interrupt Vector Register */ + +// UCAxCTL0 UART-Mode Control Bits +#define UCPEN (0x80) /* Async. Mode: Parity enable */ +#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTL0 SPI-Mode Control Bits +#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x08) /* Sync. Mode: Master Select */ + +// UCBxCTL0 I2C-Mode Control Bits +#define UCA10 (0x80) /* 10-bit Address Mode */ +#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ +#define UCMM (0x20) /* Multi-Master Environment */ +//#define res (0x10) /* reserved */ +#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ + +// UCAxCTL1 UART-Mode Control Bits +#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x20) /* RX Error interrupt enable */ +#define UCBRKIE (0x10) /* Break interrupt enable */ +#define UCDORM (0x08) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x04) /* Send next Data as Address */ +#define UCTXBRK (0x02) /* Send next Data as Break */ +#define UCSWRST (0x01) /* USCI Software Reset */ + +// UCxxCTL1 SPI-Mode Control Bits +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +//#define res (0x08) /* reserved */ +//#define res (0x04) /* reserved */ +//#define res (0x02) /* reserved */ + +// UCBxCTL1 I2C-Mode Control Bits +//#define res (0x20) /* reserved */ +#define UCTR (0x10) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x08) /* Transmit NACK */ +#define UCTXSTP (0x04) /* Transmit STOP */ +#define UCTXSTT (0x02) /* Transmit START */ +#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */ + +/* UCAxMCTL Control Bits */ +#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ +#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ +#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ +#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ +#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ +#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ +#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ +#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ +#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ +#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ + +/* UCAxSTAT Control Bits */ +#define UCLISTEN (0x80) /* USCI Listen mode */ +#define UCFE (0x40) /* USCI Frame Error Flag */ +#define UCOE (0x20) /* USCI Overrun Error Flag */ +#define UCPE (0x10) /* USCI Parity Error Flag */ +#define UCBRK (0x08) /* USCI Break received */ +#define UCRXERR (0x04) /* USCI RX Error Flag */ +#define UCADDR (0x02) /* USCI Address received Flag */ +#define UCBUSY (0x01) /* USCI Busy Flag */ +#define UCIDLE (0x02) /* USCI Idle line detected Flag */ + +/* UCBxSTAT Control Bits */ +#define UCSCLLOW (0x40) /* SCL low */ +#define UCGC (0x20) /* General Call address received Flag */ +#define UCBBUSY (0x10) /* Bus Busy Flag */ + +/* UCAxIRTCTL Control Bits */ +#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRRCTL Control Bits */ +#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOA9 (0x0200) /* I2C Own Address 9 */ +#define UCOA8 (0x0100) /* I2C Own Address 8 */ +#define UCOA7 (0x0080) /* I2C Own Address 7 */ +#define UCOA6 (0x0040) /* I2C Own Address 6 */ +#define UCOA5 (0x0020) /* I2C Own Address 5 */ +#define UCOA4 (0x0010) /* I2C Own Address 4 */ +#define UCOA3 (0x0008) /* I2C Own Address 3 */ +#define UCOA2 (0x0004) /* I2C Own Address 2 */ +#define UCOA1 (0x0002) /* I2C Own Address 1 */ +#define UCOA0 (0x0001) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCOA7_L (0x0080) /* I2C Own Address 7 */ +#define UCOA6_L (0x0040) /* I2C Own Address 6 */ +#define UCOA5_L (0x0020) /* I2C Own Address 5 */ +#define UCOA4_L (0x0010) /* I2C Own Address 4 */ +#define UCOA3_L (0x0008) /* I2C Own Address 3 */ +#define UCOA2_L (0x0004) /* I2C Own Address 2 */ +#define UCOA1_L (0x0002) /* I2C Own Address 1 */ +#define UCOA0_L (0x0001) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN_H (0x0080) /* I2C General Call enable */ +#define UCOA9_H (0x0002) /* I2C Own Address 9 */ +#define UCOA8_H (0x0001) /* I2C Own Address 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200) /* I2C Slave Address 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080) /* I2C Slave Address 7 */ +#define UCSA6_L (0x0040) /* I2C Slave Address 6 */ +#define UCSA5_L (0x0020) /* I2C Slave Address 5 */ +#define UCSA4_L (0x0010) /* I2C Slave Address 4 */ +#define UCSA3_L (0x0008) /* I2C Slave Address 3 */ +#define UCSA2_L (0x0004) /* I2C Slave Address 2 */ +#define UCSA1_L (0x0002) /* I2C Slave Address 1 */ +#define UCSA0_L (0x0001) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002) /* I2C Slave Address 9 */ +#define UCSA8_H (0x0001) /* I2C Slave Address 8 */ + +/* UCAxIE Control Bits */ +#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ + +/* UCBxIE Control Bits */ +#define UCNACKIE (0x0020) /* NACK Condition interrupt enable */ +#define UCALIE (0x0010) /* Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008) /* STOP Condition interrupt enable */ +#define UCSTTIE (0x0004) /* START Condition interrupt enable */ +#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ + +/* UCAxIFG Control Bits */ +#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */ +#define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */ +#define UCSTTIFG (0x0004) /* START Condition interrupt Flag */ +#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ + +/* USCI Interrupt Vector Definitions */ +#define USCI_NONE (0x0000) /* No Interrupt pending */ +#define USCI_UCRXIFG (0x0002) /* Interrupt Vector: UCRXIFG */ +#define USCI_UCTXIFG (0x0004) /* Interrupt Vector: UCTXIFG */ +#define USCI_I2C_UCALIFG (0x0002) /* Interrupt Vector: I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004) /* Interrupt Vector: I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006) /* Interrupt Vector: I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008) /* Interrupt Vector: I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG (0x000A) /* Interrupt Vector: I2C Mode: UCRXIFG */ +#define USCI_I2C_UCTXIFG (0x000C) /* Interrupt Vector: I2C Mode: UCTXIFG */ + +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ +#define __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_WDT_A__ 0x0150 +#define WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__ + +sfr_w(WDTCTL); /* Watchdog Timer Control */ +sfr_b(WDTCTL_L); /* Watchdog Timer Control */ +sfr_b(WDTCTL_H); /* Watchdog Timer Control */ +/* The bit names have been prefixed with "WDT" */ +/* WDTCTL Control Bits */ +#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD (0x0080) /* WDT - Timer hold */ + +/* WDTCTL Control Bits */ +#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD_L (0x0080) /* WDT - Timer hold */ + +#define WDTPW (0x5A00) + +#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */ +#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */ +#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */ +#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */ +#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */ +#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */ +#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */ +#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */ +#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */ +#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */ +#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */ +#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */ + +#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ +#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */ +#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ + + +/************************************************************ +* TLV Descriptors +************************************************************/ +#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */ +#define TLV_BASE __MSP430_BASEADDRESS_TLV__ + +#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */ +#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */ +#define TLV_START (0x1A08) /* Start Address of the TLV structure */ +#define TLV_END (0x1AFF) /* End Address of the TLV structure */ + +#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ +#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ +#define TLV_Reserved3 (0x03) /* Future usage */ +#define TLV_Reserved4 (0x04) /* Future usage */ +#define TLV_BLANK (0x05) /* Blank descriptor */ +#define TLV_Reserved6 (0x06) /* Future usage */ +#define TLV_Reserved7 (0x07) /* Serial Number */ +#define TLV_DIERECORD (0x08) /* Die Record */ +#define TLV_ADCCAL (0x11) /* ADC12 calibration */ +#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ +#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ +#define TLV_REFCAL (0x12) /* REF calibration */ +#define TLV_TAGEXT (0xFE) /* Tag extender */ +#define TLV_TAGEND (0xFF) // Tag End of Table + +/************************************************************ +* Interrupt Vectors (offset from 0xFF80) +************************************************************/ + + +#define AES_VECTOR (46) /* 0xFFDA AES */ +#define RTC_VECTOR (47) /* 0xFFDC RTC */ +#define LCD_B_VECTOR (48) /* 0xFFDE LCD B */ +#define PORT2_VECTOR (49) /* 0xFFE0 Port 2 */ +#define PORT1_VECTOR (50) /* 0xFFE2 Port 1 */ +#define TIMER1_A1_VECTOR (51) /* 0xFFE4 Timer1_A3 CC1-2, TA1 */ +#define TIMER1_A0_VECTOR (52) /* 0xFFE6 Timer1_A3 CC0 */ +#define DMA_VECTOR (53) /* 0xFFE8 DMA */ +#define CC1101_VECTOR (54) /* 0xFFEA CC1101 Radio Interface */ +#define TIMER0_A1_VECTOR (55) /* 0xFFEC Timer0_A5 CC1-4, TA */ +#define TIMER0_A0_VECTOR (56) /* 0xFFEE Timer0_A5 CC0 */ +#define ADC12_VECTOR (57) /* 0xFFF0 ADC */ +#define USCI_B0_VECTOR (58) /* 0xFFF2 USCI B0 Receive/Transmit */ +#define USCI_A0_VECTOR (59) /* 0xFFF4 USCI A0 Receive/Transmit */ +#define WDT_VECTOR (60) /* 0xFFF6 Watchdog Timer */ +#define COMP_B_VECTOR (61) /* 0xFFF8 Comparator B */ +#define UNMI_VECTOR (62) /* 0xFFFA User Non-maskable */ +#define SYSNMI_VECTOR (63) /* 0xFFFC System Non-maskable */ +#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ + +/************************************************************ +* End of Modules +************************************************************/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* #ifndef __cc430x613x */ + diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/cc430f6137.ld b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/cc430f6137.ld new file mode 100644 index 0000000000..2cf5606898 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/cc430f6137.ld @@ -0,0 +1,404 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports CC430F6137 devices. */ +/* Version: 1.208 */ +/* Default linker script, for normal executables */ + +OUTPUT_ARCH(msp430) +ENTRY(_start) + +MEMORY { + SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ + BSL : ORIGIN = 0x1000, LENGTH = 0x0800 + RAM : ORIGIN = 0x1C00, LENGTH = 0x0FFE /* END=0x2BFD, size 4094 */ + INFOMEM : ORIGIN = 0x1800, LENGTH = 0x0200 /* END=0x19FF, size 512 as 4 128-byte segments */ + INFOA : ORIGIN = 0x1980, LENGTH = 0x0080 /* END=0x19FF, size 128 */ + INFOB : ORIGIN = 0x1900, LENGTH = 0x0080 /* END=0x197F, size 128 */ + INFOC : ORIGIN = 0x1880, LENGTH = 0x0080 /* END=0x18FF, size 128 */ + INFOD : ORIGIN = 0x1800, LENGTH = 0x0080 /* END=0x187F, size 128 */ + ROM (rx) : ORIGIN = 0x8000, LENGTH = 0x7F80 /* END=0xFF7F, size 32640 */ + VECT1 : ORIGIN = 0xFF80, LENGTH = 0x0002 + VECT2 : ORIGIN = 0xFF82, LENGTH = 0x0002 + VECT3 : ORIGIN = 0xFF84, LENGTH = 0x0002 + VECT4 : ORIGIN = 0xFF86, LENGTH = 0x0002 + VECT5 : ORIGIN = 0xFF88, LENGTH = 0x0002 + VECT6 : ORIGIN = 0xFF8A, LENGTH = 0x0002 + VECT7 : ORIGIN = 0xFF8C, LENGTH = 0x0002 + VECT8 : ORIGIN = 0xFF8E, LENGTH = 0x0002 + VECT9 : ORIGIN = 0xFF90, LENGTH = 0x0002 + VECT10 : ORIGIN = 0xFF92, LENGTH = 0x0002 + VECT11 : ORIGIN = 0xFF94, LENGTH = 0x0002 + VECT12 : ORIGIN = 0xFF96, LENGTH = 0x0002 + VECT13 : ORIGIN = 0xFF98, LENGTH = 0x0002 + VECT14 : ORIGIN = 0xFF9A, LENGTH = 0x0002 + VECT15 : ORIGIN = 0xFF9C, LENGTH = 0x0002 + VECT16 : ORIGIN = 0xFF9E, LENGTH = 0x0002 + VECT17 : ORIGIN = 0xFFA0, LENGTH = 0x0002 + VECT18 : ORIGIN = 0xFFA2, LENGTH = 0x0002 + VECT19 : ORIGIN = 0xFFA4, LENGTH = 0x0002 + VECT20 : ORIGIN = 0xFFA6, LENGTH = 0x0002 + VECT21 : ORIGIN = 0xFFA8, LENGTH = 0x0002 + VECT22 : ORIGIN = 0xFFAA, LENGTH = 0x0002 + VECT23 : ORIGIN = 0xFFAC, LENGTH = 0x0002 + VECT24 : ORIGIN = 0xFFAE, LENGTH = 0x0002 + VECT25 : ORIGIN = 0xFFB0, LENGTH = 0x0002 + VECT26 : ORIGIN = 0xFFB2, LENGTH = 0x0002 + VECT27 : ORIGIN = 0xFFB4, LENGTH = 0x0002 + VECT28 : ORIGIN = 0xFFB6, LENGTH = 0x0002 + VECT29 : ORIGIN = 0xFFB8, LENGTH = 0x0002 + VECT30 : ORIGIN = 0xFFBA, LENGTH = 0x0002 + VECT31 : ORIGIN = 0xFFBC, LENGTH = 0x0002 + VECT32 : ORIGIN = 0xFFBE, LENGTH = 0x0002 + VECT33 : ORIGIN = 0xFFC0, LENGTH = 0x0002 + VECT34 : ORIGIN = 0xFFC2, LENGTH = 0x0002 + VECT35 : ORIGIN = 0xFFC4, LENGTH = 0x0002 + VECT36 : ORIGIN = 0xFFC6, LENGTH = 0x0002 + VECT37 : ORIGIN = 0xFFC8, LENGTH = 0x0002 + VECT38 : ORIGIN = 0xFFCA, LENGTH = 0x0002 + VECT39 : ORIGIN = 0xFFCC, LENGTH = 0x0002 + VECT40 : ORIGIN = 0xFFCE, LENGTH = 0x0002 + VECT41 : ORIGIN = 0xFFD0, LENGTH = 0x0002 + VECT42 : ORIGIN = 0xFFD2, LENGTH = 0x0002 + VECT43 : ORIGIN = 0xFFD4, LENGTH = 0x0002 + VECT44 : ORIGIN = 0xFFD6, LENGTH = 0x0002 + VECT45 : ORIGIN = 0xFFD8, LENGTH = 0x0002 + VECT46 : ORIGIN = 0xFFDA, LENGTH = 0x0002 + VECT47 : ORIGIN = 0xFFDC, LENGTH = 0x0002 + VECT48 : ORIGIN = 0xFFDE, LENGTH = 0x0002 + VECT49 : ORIGIN = 0xFFE0, LENGTH = 0x0002 + VECT50 : ORIGIN = 0xFFE2, LENGTH = 0x0002 + VECT51 : ORIGIN = 0xFFE4, LENGTH = 0x0002 + VECT52 : ORIGIN = 0xFFE6, LENGTH = 0x0002 + VECT53 : ORIGIN = 0xFFE8, LENGTH = 0x0002 + VECT54 : ORIGIN = 0xFFEA, LENGTH = 0x0002 + VECT55 : ORIGIN = 0xFFEC, LENGTH = 0x0002 + VECT56 : ORIGIN = 0xFFEE, LENGTH = 0x0002 + VECT57 : ORIGIN = 0xFFF0, LENGTH = 0x0002 + VECT58 : ORIGIN = 0xFFF2, LENGTH = 0x0002 + VECT59 : ORIGIN = 0xFFF4, LENGTH = 0x0002 + VECT60 : ORIGIN = 0xFFF6, LENGTH = 0x0002 + VECT61 : ORIGIN = 0xFFF8, LENGTH = 0x0002 + VECT62 : ORIGIN = 0xFFFA, LENGTH = 0x0002 + VECT63 : ORIGIN = 0xFFFC, LENGTH = 0x0002 + RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 +} + +SECTIONS +{ + __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) } > VECT1 + __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2 + __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) } > VECT3 + __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) } > VECT4 + __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5 + __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) } > VECT6 + __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) } > VECT7 + __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) } > VECT8 + __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) } > VECT9 + __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) } > VECT10 + __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) } > VECT11 + __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) } > VECT12 + __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) } > VECT13 + __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) } > VECT14 + __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) } > VECT15 + __interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) } > VECT16 + __interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) } > VECT17 + __interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) } > VECT18 + __interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) } > VECT19 + __interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) } > VECT20 + __interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) } > VECT21 + __interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) } > VECT22 + __interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) } > VECT23 + __interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) } > VECT24 + __interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) } > VECT25 + __interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) } > VECT26 + __interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) } > VECT27 + __interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) } > VECT28 + __interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) } > VECT29 + __interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) } > VECT30 + __interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) } > VECT31 + __interrupt_vector_32 : { KEEP (*(__interrupt_vector_32)) } > VECT32 + __interrupt_vector_33 : { KEEP (*(__interrupt_vector_33)) } > VECT33 + __interrupt_vector_34 : { KEEP (*(__interrupt_vector_34)) } > VECT34 + __interrupt_vector_35 : { KEEP (*(__interrupt_vector_35)) } > VECT35 + __interrupt_vector_36 : { KEEP (*(__interrupt_vector_36)) } > VECT36 + __interrupt_vector_37 : { KEEP (*(__interrupt_vector_37)) } > VECT37 + __interrupt_vector_38 : { KEEP (*(__interrupt_vector_38)) } > VECT38 + __interrupt_vector_39 : { KEEP (*(__interrupt_vector_39)) } > VECT39 + __interrupt_vector_40 : { KEEP (*(__interrupt_vector_40)) } > VECT40 + __interrupt_vector_41 : { KEEP (*(__interrupt_vector_41)) } > VECT41 + __interrupt_vector_42 : { KEEP (*(__interrupt_vector_42)) } > VECT42 + __interrupt_vector_43 : { KEEP (*(__interrupt_vector_43)) } > VECT43 + __interrupt_vector_44 : { KEEP (*(__interrupt_vector_44)) } > VECT44 + __interrupt_vector_45 : { KEEP (*(__interrupt_vector_45)) } > VECT45 + __interrupt_vector_46 : { KEEP (*(__interrupt_vector_46)) KEEP (*(__interrupt_vector_aes)) } > VECT46 + __interrupt_vector_47 : { KEEP (*(__interrupt_vector_47)) KEEP (*(__interrupt_vector_rtc)) } > VECT47 + __interrupt_vector_48 : { KEEP (*(__interrupt_vector_48)) KEEP (*(__interrupt_vector_lcd_b)) } > VECT48 + __interrupt_vector_49 : { KEEP (*(__interrupt_vector_49)) KEEP (*(__interrupt_vector_port2)) } > VECT49 + __interrupt_vector_50 : { KEEP (*(__interrupt_vector_50)) KEEP (*(__interrupt_vector_port1)) } > VECT50 + __interrupt_vector_51 : { KEEP (*(__interrupt_vector_51)) KEEP (*(__interrupt_vector_timer1_a1)) } > VECT51 + __interrupt_vector_52 : { KEEP (*(__interrupt_vector_52)) KEEP (*(__interrupt_vector_timer1_a0)) } > VECT52 + __interrupt_vector_53 : { KEEP (*(__interrupt_vector_53)) KEEP (*(__interrupt_vector_dma)) } > VECT53 + __interrupt_vector_54 : { KEEP (*(__interrupt_vector_54)) KEEP (*(__interrupt_vector_cc1101)) } > VECT54 + __interrupt_vector_55 : { KEEP (*(__interrupt_vector_55)) KEEP (*(__interrupt_vector_timer0_a1)) } > VECT55 + __interrupt_vector_56 : { KEEP (*(__interrupt_vector_56)) KEEP (*(__interrupt_vector_timer0_a0)) } > VECT56 + __interrupt_vector_57 : { KEEP (*(__interrupt_vector_57)) KEEP (*(__interrupt_vector_adc12)) } > VECT57 + __interrupt_vector_58 : { KEEP (*(__interrupt_vector_58)) KEEP (*(__interrupt_vector_usci_b0)) } > VECT58 + __interrupt_vector_59 : { KEEP (*(__interrupt_vector_59)) KEEP (*(__interrupt_vector_usci_a0)) } > VECT59 + __interrupt_vector_60 : { KEEP (*(__interrupt_vector_60)) KEEP (*(__interrupt_vector_wdt)) } > VECT60 + __interrupt_vector_61 : { KEEP (*(__interrupt_vector_61)) KEEP (*(__interrupt_vector_comp_b)) } > VECT61 + __interrupt_vector_62 : { KEEP (*(__interrupt_vector_62)) KEEP (*(__interrupt_vector_unmi)) } > VECT62 + __interrupt_vector_63 : { KEEP (*(__interrupt_vector_63)) KEEP (*(__interrupt_vector_sysnmi)) } > VECT63 + __reset_vector : + { + KEEP (*(__interrupt_vector_64)) + KEEP (*(__interrupt_vector_reset)) + KEEP (*(.resetvec)) + } > RESETVEC + + .rodata : + { + . = ALIGN(2); + *(.plt) + *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) + *(.rodata1) + KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) + } > ROM + + /* Note: This is a separate .rodata section for sections which are + read only but which older linkers treat as read-write. + This prevents older linkers from marking the entire .rodata + section as read-write. */ + .rodata2 : + { + . = ALIGN(2); + PROVIDE (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + . = ALIGN(2); + PROVIDE (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE (__init_array_end = .); + . = ALIGN(2); + PROVIDE (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE (__fini_array_end = .); + . = ALIGN(2); + *(.eh_frame_hdr) + KEEP (*(.eh_frame)) + + /* gcc uses crtbegin.o to find the start of the constructors, so + we make sure it is first. Because this is a wildcard, it + doesn't matter if the user does not actually link against + crtbegin.o; the linker won't look for a file to match a + wildcard. The wildcard also means that it doesn't matter which + directory crtbegin.o is in. */ + KEEP (*crtbegin*.o(.ctors)) + + /* We don't want to include the .ctor section from from the + crtend.o file until after the sorted ctors. The .ctor section + from the crtend file contains the end of ctors marker and it + must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > ROM + + .text : + { + . = ALIGN(2); + PROVIDE (_start = .); + KEEP (*(SORT(.crt_*))) + *(.lowtext .text .stub .text.* .gnu.linkonce.t.* .text:*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.interp .hash .dynsym .dynstr .gnu.version*) + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + . = ALIGN(2); + KEEP (*(.init)) + KEEP (*(.fini)) + KEEP (*(.tm_clone_table)) + } > ROM + + .data : + { + . = ALIGN(2); + PROVIDE (__datastart = .); + + KEEP (*(.jcr)) + *(.data.rel.ro.local) *(.data.rel.ro*) + *(.dynamic) + + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + *(.data1) + *(.got.plt) *(.got) + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + . = ALIGN(2); + *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) + + . = ALIGN(2); + _edata = .; + PROVIDE (edata = .); + PROVIDE (__dataend = .); + } > RAM AT>ROM + + /* Note that crt0 assumes this is a multiple of two; all the + start/stop symbols are also assumed word-aligned. */ + PROVIDE(__romdatastart = LOADADDR(.data)); + PROVIDE (__romdatacopysize = SIZEOF(.data)); + + .bss : + { + . = ALIGN(2); + PROVIDE (__bssstart = .); + *(.dynbss) + *(.sbss .sbss.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(2); + *(COMMON) + PROVIDE (__bssend = .); + } > RAM + PROVIDE (__bsssize = SIZEOF(.bss)); + + /* This section contains data that is not initialised during load + or application reset. */ + .noinit (NOLOAD) : + { + . = ALIGN(2); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(2); + PROVIDE (__noinit_end = .); + end = .; + } > RAM + + /* We create this section so that "end" will always be in the + RAM region (matching .stack below), even if the .bss + section is empty. */ + .heap (NOLOAD) : + { + . = ALIGN(2); + __heap_start__ = .; + _end = __heap_start__; + PROVIDE (end = .); + KEEP (*(.heap)) + _end = .; + PROVIDE (end = .); + /* This word is here so that the section is not empty, and thus + not discarded by the linker. The actual value does not matter + and is ignored. */ + LONG(0); + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > RAM + /* WARNING: Do not place anything in RAM here. + The heap section must be the last section in RAM and the stack + section must be placed at the very end of the RAM region. */ + + .stack (ORIGIN (RAM) + LENGTH(RAM)) : + { + PROVIDE (__stack = .); + *(.stack) + } + + .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + .MSP430.attributes 0 : + { + KEEP (*(.MSP430.attributes)) + KEEP (*(.gnu.attributes)) + KEEP (*(__TI_build_attributes)) + } + + /* The rest are all not normally part of the runtime image. */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /DISCARD/ : { *(.note.GNU-stack) } +} + + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +INCLUDE cc430f6137_symbols.ld + diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/cc430f6137_symbols.ld b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/cc430f6137_symbols.ld new file mode 100644 index 0000000000..68f48b43f3 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/cc430f6137_symbols.ld @@ -0,0 +1,825 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports CC430F6137 devices. */ +/* Version: 1.208 */ + +/************************************************************ +* STANDARD BITS +************************************************************/ +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ +/************************************************************ +* ADC12 PLUS +************************************************************/ +PROVIDE(ADC12CTL0 = 0x0700); +PROVIDE(ADC12CTL0_L = 0x0700); +PROVIDE(ADC12CTL0_H = 0x0701); +PROVIDE(ADC12CTL1 = 0x0702); +PROVIDE(ADC12CTL1_L = 0x0702); +PROVIDE(ADC12CTL1_H = 0x0703); +PROVIDE(ADC12CTL2 = 0x0704); +PROVIDE(ADC12CTL2_L = 0x0704); +PROVIDE(ADC12CTL2_H = 0x0705); +PROVIDE(ADC12IFG = 0x070A); +PROVIDE(ADC12IFG_L = 0x070A); +PROVIDE(ADC12IFG_H = 0x070B); +PROVIDE(ADC12IE = 0x070C); +PROVIDE(ADC12IE_L = 0x070C); +PROVIDE(ADC12IE_H = 0x070D); +PROVIDE(ADC12IV = 0x070E); +PROVIDE(ADC12IV_L = 0x070E); +PROVIDE(ADC12IV_H = 0x070F); +PROVIDE(ADC12MEM0 = 0x0720); +PROVIDE(ADC12MEM0_L = 0x0720); +PROVIDE(ADC12MEM0_H = 0x0721); +PROVIDE(ADC12MEM1 = 0x0722); +PROVIDE(ADC12MEM1_L = 0x0722); +PROVIDE(ADC12MEM1_H = 0x0723); +PROVIDE(ADC12MEM2 = 0x0724); +PROVIDE(ADC12MEM2_L = 0x0724); +PROVIDE(ADC12MEM2_H = 0x0725); +PROVIDE(ADC12MEM3 = 0x0726); +PROVIDE(ADC12MEM3_L = 0x0726); +PROVIDE(ADC12MEM3_H = 0x0727); +PROVIDE(ADC12MEM4 = 0x0728); +PROVIDE(ADC12MEM4_L = 0x0728); +PROVIDE(ADC12MEM4_H = 0x0729); +PROVIDE(ADC12MEM5 = 0x072A); +PROVIDE(ADC12MEM5_L = 0x072A); +PROVIDE(ADC12MEM5_H = 0x072B); +PROVIDE(ADC12MEM6 = 0x072C); +PROVIDE(ADC12MEM6_L = 0x072C); +PROVIDE(ADC12MEM6_H = 0x072D); +PROVIDE(ADC12MEM7 = 0x072E); +PROVIDE(ADC12MEM7_L = 0x072E); +PROVIDE(ADC12MEM7_H = 0x072F); +PROVIDE(ADC12MEM8 = 0x0730); +PROVIDE(ADC12MEM8_L = 0x0730); +PROVIDE(ADC12MEM8_H = 0x0731); +PROVIDE(ADC12MEM9 = 0x0732); +PROVIDE(ADC12MEM9_L = 0x0732); +PROVIDE(ADC12MEM9_H = 0x0733); +PROVIDE(ADC12MEM10 = 0x0734); +PROVIDE(ADC12MEM10_L = 0x0734); +PROVIDE(ADC12MEM10_H = 0x0735); +PROVIDE(ADC12MEM11 = 0x0736); +PROVIDE(ADC12MEM11_L = 0x0736); +PROVIDE(ADC12MEM11_H = 0x0737); +PROVIDE(ADC12MEM12 = 0x0738); +PROVIDE(ADC12MEM12_L = 0x0738); +PROVIDE(ADC12MEM12_H = 0x0739); +PROVIDE(ADC12MEM13 = 0x073A); +PROVIDE(ADC12MEM13_L = 0x073A); +PROVIDE(ADC12MEM13_H = 0x073B); +PROVIDE(ADC12MEM14 = 0x073C); +PROVIDE(ADC12MEM14_L = 0x073C); +PROVIDE(ADC12MEM14_H = 0x073D); +PROVIDE(ADC12MEM15 = 0x073E); +PROVIDE(ADC12MEM15_L = 0x073E); +PROVIDE(ADC12MEM15_H = 0x073F); +PROVIDE(ADC12MCTL0 = 0x0710); +PROVIDE(ADC12MCTL1 = 0x0711); +PROVIDE(ADC12MCTL2 = 0x0712); +PROVIDE(ADC12MCTL3 = 0x0713); +PROVIDE(ADC12MCTL4 = 0x0714); +PROVIDE(ADC12MCTL5 = 0x0715); +PROVIDE(ADC12MCTL6 = 0x0716); +PROVIDE(ADC12MCTL7 = 0x0717); +PROVIDE(ADC12MCTL8 = 0x0718); +PROVIDE(ADC12MCTL9 = 0x0719); +PROVIDE(ADC12MCTL10 = 0x071A); +PROVIDE(ADC12MCTL11 = 0x071B); +PROVIDE(ADC12MCTL12 = 0x071C); +PROVIDE(ADC12MCTL13 = 0x071D); +PROVIDE(ADC12MCTL14 = 0x071E); +PROVIDE(ADC12MCTL15 = 0x071F); +/************************************************************ +* AES Accelerator +************************************************************/ +PROVIDE(AESACTL0 = 0x09C0); +PROVIDE(AESACTL0_L = 0x09C0); +PROVIDE(AESACTL0_H = 0x09C1); +PROVIDE(AESASTAT = 0x09C4); +PROVIDE(AESASTAT_L = 0x09C4); +PROVIDE(AESASTAT_H = 0x09C5); +PROVIDE(AESAKEY = 0x09C6); +PROVIDE(AESAKEY_L = 0x09C6); +PROVIDE(AESAKEY_H = 0x09C7); +PROVIDE(AESADIN = 0x09C8); +PROVIDE(AESADIN_L = 0x09C8); +PROVIDE(AESADIN_H = 0x09C9); +PROVIDE(AESADOUT = 0x09CA); +PROVIDE(AESADOUT_L = 0x09CA); +PROVIDE(AESADOUT_H = 0x09CB); +/************************************************************ +* Comparator B +************************************************************/ +PROVIDE(CBCTL0 = 0x08C0); +PROVIDE(CBCTL0_L = 0x08C0); +PROVIDE(CBCTL0_H = 0x08C1); +PROVIDE(CBCTL1 = 0x08C2); +PROVIDE(CBCTL1_L = 0x08C2); +PROVIDE(CBCTL1_H = 0x08C3); +PROVIDE(CBCTL2 = 0x08C4); +PROVIDE(CBCTL2_L = 0x08C4); +PROVIDE(CBCTL2_H = 0x08C5); +PROVIDE(CBCTL3 = 0x08C6); +PROVIDE(CBCTL3_L = 0x08C6); +PROVIDE(CBCTL3_H = 0x08C7); +PROVIDE(CBINT = 0x08CC); +PROVIDE(CBINT_L = 0x08CC); +PROVIDE(CBINT_H = 0x08CD); +PROVIDE(CBIV = 0x08CE); +/************************************************************ +* CC1101 Radio Interface +************************************************************/ +PROVIDE(RF1AIFCTL0 = 0x0F00); +PROVIDE(RF1AIFCTL0_L = 0x0F00); +PROVIDE(RF1AIFCTL0_H = 0x0F01); +PROVIDE(RF1AIFCTL1 = 0x0F02); +PROVIDE(RF1AIFCTL1_L = 0x0F02); +PROVIDE(RF1AIFCTL1_H = 0x0F03); +PROVIDE(RF1AIFCTL2 = 0x0F04); +PROVIDE(RF1AIFCTL2_L = 0x0F04); +PROVIDE(RF1AIFCTL2_H = 0x0F05); +PROVIDE(RF1AIFERR = 0x0F06); +PROVIDE(RF1AIFERR_L = 0x0F06); +PROVIDE(RF1AIFERR_H = 0x0F07); +PROVIDE(RF1AIFERRV = 0x0F0C); +PROVIDE(RF1AIFERRV_L = 0x0F0C); +PROVIDE(RF1AIFERRV_H = 0x0F0D); +PROVIDE(RF1AIFIV = 0x0F0E); +PROVIDE(RF1AIFIV_L = 0x0F0E); +PROVIDE(RF1AIFIV_H = 0x0F0F); +PROVIDE(RF1AINSTRW = 0x0F10); +PROVIDE(RF1AINSTRW_L = 0x0F10); +PROVIDE(RF1AINSTRW_H = 0x0F11); +PROVIDE(RF1AINSTR1W = 0x0F12); +PROVIDE(RF1AINSTR1W_L = 0x0F12); +PROVIDE(RF1AINSTR1W_H = 0x0F13); +PROVIDE(RF1AINSTR2W = 0x0F14); +PROVIDE(RF1AINSTR2W_L = 0x0F14); +PROVIDE(RF1AINSTR2W_H = 0x0F15); +PROVIDE(RF1ADINW = 0x0F16); +PROVIDE(RF1ADINW_L = 0x0F16); +PROVIDE(RF1ADINW_H = 0x0F17); +PROVIDE(RF1ASTAT0W = 0x0F20); +PROVIDE(RF1ASTAT0W_L = 0x0F20); +PROVIDE(RF1ASTAT0W_H = 0x0F21); +PROVIDE(RF1ASTAT1W = 0x0F22); +PROVIDE(RF1ASTAT1W_L = 0x0F22); +PROVIDE(RF1ASTAT1W_H = 0x0F23); +PROVIDE(RF1ASTAT2W = 0x0F24); +PROVIDE(RF1ASTAT2W_L = 0x0F24); +PROVIDE(RF1ASTAT2W_H = 0x0F25); +PROVIDE(RF1ADOUT0W = 0x0F28); +PROVIDE(RF1ADOUT0W_L = 0x0F28); +PROVIDE(RF1ADOUT0W_H = 0x0F29); +PROVIDE(RF1ADOUT1W = 0x0F2A); +PROVIDE(RF1ADOUT1W_L = 0x0F2A); +PROVIDE(RF1ADOUT1W_H = 0x0F2B); +PROVIDE(RF1ADOUT2W = 0x0F2C); +PROVIDE(RF1ADOUT2W_L = 0x0F2C); +PROVIDE(RF1ADOUT2W_H = 0x0F2D); +PROVIDE(RF1AIN = 0x0F30); +PROVIDE(RF1AIN_L = 0x0F30); +PROVIDE(RF1AIN_H = 0x0F31); +PROVIDE(RF1AIFG = 0x0F32); +PROVIDE(RF1AIFG_L = 0x0F32); +PROVIDE(RF1AIFG_H = 0x0F33); +PROVIDE(RF1AIES = 0x0F34); +PROVIDE(RF1AIES_L = 0x0F34); +PROVIDE(RF1AIES_H = 0x0F35); +PROVIDE(RF1AIE = 0x0F36); +PROVIDE(RF1AIE_L = 0x0F36); +PROVIDE(RF1AIE_H = 0x0F37); +PROVIDE(RF1AIV = 0x0F38); +PROVIDE(RF1AIV_L = 0x0F38); +PROVIDE(RF1AIV_H = 0x0F39); +PROVIDE(RF1ARXFIFO = 0x0F3C); +PROVIDE(RF1ARXFIFO_L = 0x0F3C); +PROVIDE(RF1ARXFIFO_H = 0x0F3D); +PROVIDE(RF1ATXFIFO = 0x0F3E); +PROVIDE(RF1ATXFIFO_L = 0x0F3E); +PROVIDE(RF1ATXFIFO_H = 0x0F3F); +/************************************************************* +* CRC Module +*************************************************************/ +PROVIDE(CRCDI = 0x0150); +PROVIDE(CRCDI_L = 0x0150); +PROVIDE(CRCDI_H = 0x0151); +PROVIDE(CRCINIRES = 0x0154); +PROVIDE(CRCINIRES_L = 0x0154); +PROVIDE(CRCINIRES_H = 0x0155); +/************************************************************ +* DMA_X +************************************************************/ +PROVIDE(DMACTL0 = 0x0500); +PROVIDE(DMACTL1 = 0x0502); +PROVIDE(DMACTL2 = 0x0504); +PROVIDE(DMACTL3 = 0x0506); +PROVIDE(DMACTL4 = 0x0508); +PROVIDE(DMAIV = 0x050E); +PROVIDE(DMA0CTL = 0x0510); +PROVIDE(DMA0SA = 0x0512); +PROVIDE(DMA0SAL = 0x0512); +PROVIDE(DMA0DA = 0x0516); +PROVIDE(DMA0DAL = 0x0516); +PROVIDE(DMA0SZ = 0x051A); +PROVIDE(DMA1CTL = 0x0520); +PROVIDE(DMA1SA = 0x0522); +PROVIDE(DMA1SAL = 0x0522); +PROVIDE(DMA1DA = 0x0526); +PROVIDE(DMA1DAL = 0x0526); +PROVIDE(DMA1SZ = 0x052A); +PROVIDE(DMA2CTL = 0x0530); +PROVIDE(DMA2SA = 0x0532); +PROVIDE(DMA2SAL = 0x0532); +PROVIDE(DMA2DA = 0x0536); +PROVIDE(DMA2DAL = 0x0536); +PROVIDE(DMA2SZ = 0x053A); +/************************************************************* +* Flash Memory +*************************************************************/ +PROVIDE(FCTL1 = 0x0140); +PROVIDE(FCTL1_L = 0x0140); +PROVIDE(FCTL1_H = 0x0141); +PROVIDE(FCTL3 = 0x0144); +PROVIDE(FCTL3_L = 0x0144); +PROVIDE(FCTL3_H = 0x0145); +PROVIDE(FCTL4 = 0x0146); +PROVIDE(FCTL4_L = 0x0146); +PROVIDE(FCTL4_H = 0x0147); +/************************************************************ +* LCD_B +************************************************************/ +PROVIDE(LCDBCTL0 = 0x0A00); +PROVIDE(LCDBCTL0_L = 0x0A00); +PROVIDE(LCDBCTL0_H = 0x0A01); +PROVIDE(LCDBCTL1 = 0x0A02); +PROVIDE(LCDBCTL1_L = 0x0A02); +PROVIDE(LCDBCTL1_H = 0x0A03); +PROVIDE(LCDBBLKCTL = 0x0A04); +PROVIDE(LCDBBLKCTL_L = 0x0A04); +PROVIDE(LCDBBLKCTL_H = 0x0A05); +PROVIDE(LCDBMEMCTL = 0x0A06); +PROVIDE(LCDBMEMCTL_L = 0x0A06); +PROVIDE(LCDBMEMCTL_H = 0x0A07); +PROVIDE(LCDBVCTL = 0x0A08); +PROVIDE(LCDBVCTL_L = 0x0A08); +PROVIDE(LCDBVCTL_H = 0x0A09); +PROVIDE(LCDBPCTL0 = 0x0A0A); +PROVIDE(LCDBPCTL0_L = 0x0A0A); +PROVIDE(LCDBPCTL0_H = 0x0A0B); +PROVIDE(LCDBPCTL1 = 0x0A0C); +PROVIDE(LCDBPCTL1_L = 0x0A0C); +PROVIDE(LCDBPCTL1_H = 0x0A0D); +PROVIDE(LCDBPCTL2 = 0x0A0E); +PROVIDE(LCDBPCTL2_L = 0x0A0E); +PROVIDE(LCDBPCTL2_H = 0x0A0F); +PROVIDE(LCDBPCTL3 = 0x0A10); +PROVIDE(LCDBPCTL3_L = 0x0A10); +PROVIDE(LCDBPCTL3_H = 0x0A11); +PROVIDE(LCDBCPCTL = 0x0A12); +PROVIDE(LCDBCPCTL_L = 0x0A12); +PROVIDE(LCDBCPCTL_H = 0x0A13); +PROVIDE(LCDBIV = 0x0A1E); +PROVIDE(LCDM1 = 0x0A20); +PROVIDE(LCDM2 = 0x0A21); +PROVIDE(LCDM3 = 0x0A22); +PROVIDE(LCDM4 = 0x0A23); +PROVIDE(LCDM5 = 0x0A24); +PROVIDE(LCDM6 = 0x0A25); +PROVIDE(LCDM7 = 0x0A26); +PROVIDE(LCDM8 = 0x0A27); +PROVIDE(LCDM9 = 0x0A28); +PROVIDE(LCDM10 = 0x0A29); +PROVIDE(LCDM11 = 0x0A2A); +PROVIDE(LCDM12 = 0x0A2B); +PROVIDE(LCDM13 = 0x0A2C); +PROVIDE(LCDM14 = 0x0A2D); +PROVIDE(LCDM15 = 0x0A2E); +PROVIDE(LCDM16 = 0x0A2F); +PROVIDE(LCDM17 = 0x0A30); +PROVIDE(LCDM18 = 0x0A31); +PROVIDE(LCDM19 = 0x0A32); +PROVIDE(LCDM20 = 0x0A33); +PROVIDE(LCDM21 = 0x0A34); +PROVIDE(LCDM22 = 0x0A35); +PROVIDE(LCDM23 = 0x0A36); +PROVIDE(LCDM24 = 0x0A37); +PROVIDE(LCDBM1 = 0x0A40); +PROVIDE(LCDBM2 = 0x0A41); +PROVIDE(LCDBM3 = 0x0A42); +PROVIDE(LCDBM4 = 0x0A43); +PROVIDE(LCDBM5 = 0x0A44); +PROVIDE(LCDBM6 = 0x0A45); +PROVIDE(LCDBM7 = 0x0A46); +PROVIDE(LCDBM8 = 0x0A47); +PROVIDE(LCDBM9 = 0x0A48); +PROVIDE(LCDBM10 = 0x0A49); +PROVIDE(LCDBM11 = 0x0A4A); +PROVIDE(LCDBM12 = 0x0A4B); +PROVIDE(LCDBM13 = 0x0A4C); +PROVIDE(LCDBM14 = 0x0A4D); +PROVIDE(LCDBM15 = 0x0A4E); +PROVIDE(LCDBM16 = 0x0A4F); +PROVIDE(LCDBM17 = 0x0A50); +PROVIDE(LCDBM18 = 0x0A51); +PROVIDE(LCDBM19 = 0x0A52); +PROVIDE(LCDBM20 = 0x0A53); +PROVIDE(LCDBM21 = 0x0A54); +PROVIDE(LCDBM22 = 0x0A55); +PROVIDE(LCDBM23 = 0x0A56); +PROVIDE(LCDBM24 = 0x0A57); +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ +PROVIDE(MPY = 0x04C0); +PROVIDE(MPY_L = 0x04C0); +PROVIDE(MPY_H = 0x04C1); +PROVIDE(MPYS = 0x04C2); +PROVIDE(MPYS_L = 0x04C2); +PROVIDE(MPYS_H = 0x04C3); +PROVIDE(MAC = 0x04C4); +PROVIDE(MAC_L = 0x04C4); +PROVIDE(MAC_H = 0x04C5); +PROVIDE(MACS = 0x04C6); +PROVIDE(MACS_L = 0x04C6); +PROVIDE(MACS_H = 0x04C7); +PROVIDE(OP2 = 0x04C8); +PROVIDE(OP2_L = 0x04C8); +PROVIDE(OP2_H = 0x04C9); +PROVIDE(RESLO = 0x04CA); +PROVIDE(RESLO_L = 0x04CA); +PROVIDE(RESLO_H = 0x04CB); +PROVIDE(RESHI = 0x04CC); +PROVIDE(RESHI_L = 0x04CC); +PROVIDE(RESHI_H = 0x04CD); +PROVIDE(SUMEXT = 0x04CE); +PROVIDE(SUMEXT_L = 0x04CE); +PROVIDE(SUMEXT_H = 0x04CF); +PROVIDE(MPY32L = 0x04D0); +PROVIDE(MPY32L_L = 0x04D0); +PROVIDE(MPY32L_H = 0x04D1); +PROVIDE(MPY32H = 0x04D2); +PROVIDE(MPY32H_L = 0x04D2); +PROVIDE(MPY32H_H = 0x04D3); +PROVIDE(MPYS32L = 0x04D4); +PROVIDE(MPYS32L_L = 0x04D4); +PROVIDE(MPYS32L_H = 0x04D5); +PROVIDE(MPYS32H = 0x04D6); +PROVIDE(MPYS32H_L = 0x04D6); +PROVIDE(MPYS32H_H = 0x04D7); +PROVIDE(MAC32L = 0x04D8); +PROVIDE(MAC32L_L = 0x04D8); +PROVIDE(MAC32L_H = 0x04D9); +PROVIDE(MAC32H = 0x04DA); +PROVIDE(MAC32H_L = 0x04DA); +PROVIDE(MAC32H_H = 0x04DB); +PROVIDE(MACS32L = 0x04DC); +PROVIDE(MACS32L_L = 0x04DC); +PROVIDE(MACS32L_H = 0x04DD); +PROVIDE(MACS32H = 0x04DE); +PROVIDE(MACS32H_L = 0x04DE); +PROVIDE(MACS32H_H = 0x04DF); +PROVIDE(OP2L = 0x04E0); +PROVIDE(OP2L_L = 0x04E0); +PROVIDE(OP2L_H = 0x04E1); +PROVIDE(OP2H = 0x04E2); +PROVIDE(OP2H_L = 0x04E2); +PROVIDE(OP2H_H = 0x04E3); +PROVIDE(RES0 = 0x04E4); +PROVIDE(RES0_L = 0x04E4); +PROVIDE(RES0_H = 0x04E5); +PROVIDE(RES1 = 0x04E6); +PROVIDE(RES1_L = 0x04E6); +PROVIDE(RES1_H = 0x04E7); +PROVIDE(RES2 = 0x04E8); +PROVIDE(RES2_L = 0x04E8); +PROVIDE(RES2_H = 0x04E9); +PROVIDE(RES3 = 0x04EA); +PROVIDE(RES3_L = 0x04EA); +PROVIDE(RES3_H = 0x04EB); +PROVIDE(MPY32CTL0 = 0x04EC); +PROVIDE(MPY32CTL0_L = 0x04EC); +PROVIDE(MPY32CTL0_H = 0x04ED); +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(PAIN = 0x0200); +PROVIDE(PAIN_L = 0x0200); +PROVIDE(PAIN_H = 0x0201); +PROVIDE(PAOUT = 0x0202); +PROVIDE(PAOUT_L = 0x0202); +PROVIDE(PAOUT_H = 0x0203); +PROVIDE(PADIR = 0x0204); +PROVIDE(PADIR_L = 0x0204); +PROVIDE(PADIR_H = 0x0205); +PROVIDE(PAREN = 0x0206); +PROVIDE(PAREN_L = 0x0206); +PROVIDE(PAREN_H = 0x0207); +PROVIDE(PADS = 0x0208); +PROVIDE(PADS_L = 0x0208); +PROVIDE(PADS_H = 0x0209); +PROVIDE(PASEL = 0x020A); +PROVIDE(PASEL_L = 0x020A); +PROVIDE(PASEL_H = 0x020B); +PROVIDE(PAIES = 0x0218); +PROVIDE(PAIES_L = 0x0218); +PROVIDE(PAIES_H = 0x0219); +PROVIDE(PAIE = 0x021A); +PROVIDE(PAIE_L = 0x021A); +PROVIDE(PAIE_H = 0x021B); +PROVIDE(PAIFG = 0x021C); +PROVIDE(PAIFG_L = 0x021C); +PROVIDE(PAIFG_H = 0x021D); +PROVIDE(P1IV = 0x020E); +PROVIDE(P2IV = 0x021E); +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(PBIN = 0x0220); +PROVIDE(PBIN_L = 0x0220); +PROVIDE(PBIN_H = 0x0221); +PROVIDE(PBOUT = 0x0222); +PROVIDE(PBOUT_L = 0x0222); +PROVIDE(PBOUT_H = 0x0223); +PROVIDE(PBDIR = 0x0224); +PROVIDE(PBDIR_L = 0x0224); +PROVIDE(PBDIR_H = 0x0225); +PROVIDE(PBREN = 0x0226); +PROVIDE(PBREN_L = 0x0226); +PROVIDE(PBREN_H = 0x0227); +PROVIDE(PBDS = 0x0228); +PROVIDE(PBDS_L = 0x0228); +PROVIDE(PBDS_H = 0x0229); +PROVIDE(PBSEL = 0x022A); +PROVIDE(PBSEL_L = 0x022A); +PROVIDE(PBSEL_H = 0x022B); +/************************************************************ +* DIGITAL I/O Port5 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(PCIN = 0x0240); +PROVIDE(PCIN_L = 0x0240); +PROVIDE(PCIN_H = 0x0241); +PROVIDE(PCOUT = 0x0242); +PROVIDE(PCOUT_L = 0x0242); +PROVIDE(PCOUT_H = 0x0243); +PROVIDE(PCDIR = 0x0244); +PROVIDE(PCDIR_L = 0x0244); +PROVIDE(PCDIR_H = 0x0245); +PROVIDE(PCREN = 0x0246); +PROVIDE(PCREN_L = 0x0246); +PROVIDE(PCREN_H = 0x0247); +PROVIDE(PCDS = 0x0248); +PROVIDE(PCDS_L = 0x0248); +PROVIDE(PCDS_H = 0x0249); +PROVIDE(PCSEL = 0x024A); +PROVIDE(PCSEL_L = 0x024A); +PROVIDE(PCSEL_H = 0x024B); +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ +PROVIDE(PJIN = 0x0320); +PROVIDE(PJIN_L = 0x0320); +PROVIDE(PJIN_H = 0x0321); +PROVIDE(PJOUT = 0x0322); +PROVIDE(PJOUT_L = 0x0322); +PROVIDE(PJOUT_H = 0x0323); +PROVIDE(PJDIR = 0x0324); +PROVIDE(PJDIR_L = 0x0324); +PROVIDE(PJDIR_H = 0x0325); +PROVIDE(PJREN = 0x0326); +PROVIDE(PJREN_L = 0x0326); +PROVIDE(PJREN_H = 0x0327); +PROVIDE(PJDS = 0x0328); +PROVIDE(PJDS_L = 0x0328); +PROVIDE(PJDS_H = 0x0329); +/************************************************************ +* PORT MAPPING CONTROLLER +************************************************************/ +PROVIDE(PMAPKEYID = 0x01C0); +PROVIDE(PMAPKEYID_L = 0x01C0); +PROVIDE(PMAPKEYID_H = 0x01C1); +PROVIDE(PMAPCTL = 0x01C2); +PROVIDE(PMAPCTL_L = 0x01C2); +PROVIDE(PMAPCTL_H = 0x01C3); +/************************************************************ +* PORT 1 MAPPING CONTROLLER +************************************************************/ +PROVIDE(P1MAP01 = 0x01C8); +PROVIDE(P1MAP01_L = 0x01C8); +PROVIDE(P1MAP01_H = 0x01C9); +PROVIDE(P1MAP23 = 0x01CA); +PROVIDE(P1MAP23_L = 0x01CA); +PROVIDE(P1MAP23_H = 0x01CB); +PROVIDE(P1MAP45 = 0x01CC); +PROVIDE(P1MAP45_L = 0x01CC); +PROVIDE(P1MAP45_H = 0x01CD); +PROVIDE(P1MAP67 = 0x01CE); +PROVIDE(P1MAP67_L = 0x01CE); +PROVIDE(P1MAP67_H = 0x01CF); +/************************************************************ +* PORT 2 MAPPING CONTROLLER +************************************************************/ +PROVIDE(P2MAP01 = 0x01D0); +PROVIDE(P2MAP01_L = 0x01D0); +PROVIDE(P2MAP01_H = 0x01D1); +PROVIDE(P2MAP23 = 0x01D2); +PROVIDE(P2MAP23_L = 0x01D2); +PROVIDE(P2MAP23_H = 0x01D3); +PROVIDE(P2MAP45 = 0x01D4); +PROVIDE(P2MAP45_L = 0x01D4); +PROVIDE(P2MAP45_H = 0x01D5); +PROVIDE(P2MAP67 = 0x01D6); +PROVIDE(P2MAP67_L = 0x01D6); +PROVIDE(P2MAP67_H = 0x01D7); +/************************************************************ +* PORT 3 MAPPING CONTROLLER +************************************************************/ +PROVIDE(P3MAP01 = 0x01D8); +PROVIDE(P3MAP01_L = 0x01D8); +PROVIDE(P3MAP01_H = 0x01D9); +PROVIDE(P3MAP23 = 0x01DA); +PROVIDE(P3MAP23_L = 0x01DA); +PROVIDE(P3MAP23_H = 0x01DB); +PROVIDE(P3MAP45 = 0x01DC); +PROVIDE(P3MAP45_L = 0x01DC); +PROVIDE(P3MAP45_H = 0x01DD); +PROVIDE(P3MAP67 = 0x01DE); +PROVIDE(P3MAP67_L = 0x01DE); +PROVIDE(P3MAP67_H = 0x01DF); +/************************************************************ +* PMM - Power Management System +************************************************************/ +PROVIDE(PMMCTL0 = 0x0120); +PROVIDE(PMMCTL0_L = 0x0120); +PROVIDE(PMMCTL0_H = 0x0121); +PROVIDE(PMMCTL1 = 0x0122); +PROVIDE(PMMCTL1_L = 0x0122); +PROVIDE(PMMCTL1_H = 0x0123); +PROVIDE(SVSMHCTL = 0x0124); +PROVIDE(SVSMHCTL_L = 0x0124); +PROVIDE(SVSMHCTL_H = 0x0125); +PROVIDE(SVSMLCTL = 0x0126); +PROVIDE(SVSMLCTL_L = 0x0126); +PROVIDE(SVSMLCTL_H = 0x0127); +PROVIDE(SVSMIO = 0x0128); +PROVIDE(SVSMIO_L = 0x0128); +PROVIDE(SVSMIO_H = 0x0129); +PROVIDE(PMMIFG = 0x012C); +PROVIDE(PMMIFG_L = 0x012C); +PROVIDE(PMMIFG_H = 0x012D); +PROVIDE(PMMRIE = 0x012E); +PROVIDE(PMMRIE_L = 0x012E); +PROVIDE(PMMRIE_H = 0x012F); +/************************************************************* +* RAM Control Module +*************************************************************/ +PROVIDE(RCCTL0 = 0x0158); +PROVIDE(RCCTL0_L = 0x0158); +PROVIDE(RCCTL0_H = 0x0159); +/************************************************************ +* Shared Reference +************************************************************/ +PROVIDE(REFCTL0 = 0x01B0); +PROVIDE(REFCTL0_L = 0x01B0); +PROVIDE(REFCTL0_H = 0x01B1); +/************************************************************ +* Real Time Clock +************************************************************/ +PROVIDE(RTCCTL01 = 0x04A0); +PROVIDE(RTCCTL01_L = 0x04A0); +PROVIDE(RTCCTL01_H = 0x04A1); +PROVIDE(RTCCTL23 = 0x04A2); +PROVIDE(RTCCTL23_L = 0x04A2); +PROVIDE(RTCCTL23_H = 0x04A3); +PROVIDE(RTCPS0CTL = 0x04A8); +PROVIDE(RTCPS0CTL_L = 0x04A8); +PROVIDE(RTCPS0CTL_H = 0x04A9); +PROVIDE(RTCPS1CTL = 0x04AA); +PROVIDE(RTCPS1CTL_L = 0x04AA); +PROVIDE(RTCPS1CTL_H = 0x04AB); +PROVIDE(RTCPS = 0x04AC); +PROVIDE(RTCPS_L = 0x04AC); +PROVIDE(RTCPS_H = 0x04AD); +PROVIDE(RTCIV = 0x04AE); +PROVIDE(RTCTIM0 = 0x04B0); +PROVIDE(RTCTIM0_L = 0x04B0); +PROVIDE(RTCTIM0_H = 0x04B1); +PROVIDE(RTCTIM1 = 0x04B2); +PROVIDE(RTCTIM1_L = 0x04B2); +PROVIDE(RTCTIM1_H = 0x04B3); +PROVIDE(RTCDATE = 0x04B4); +PROVIDE(RTCDATE_L = 0x04B4); +PROVIDE(RTCDATE_H = 0x04B5); +PROVIDE(RTCYEAR = 0x04B6); +PROVIDE(RTCYEAR_L = 0x04B6); +PROVIDE(RTCYEAR_H = 0x04B7); +PROVIDE(RTCAMINHR = 0x04B8); +PROVIDE(RTCAMINHR_L = 0x04B8); +PROVIDE(RTCAMINHR_H = 0x04B9); +PROVIDE(RTCADOWDAY = 0x04BA); +PROVIDE(RTCADOWDAY_L = 0x04BA); +PROVIDE(RTCADOWDAY_H = 0x04BB); +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ +PROVIDE(SFRIE1 = 0x0100); +PROVIDE(SFRIE1_L = 0x0100); +PROVIDE(SFRIE1_H = 0x0101); +PROVIDE(SFRIFG1 = 0x0102); +PROVIDE(SFRIFG1_L = 0x0102); +PROVIDE(SFRIFG1_H = 0x0103); +PROVIDE(SFRRPCR = 0x0104); +PROVIDE(SFRRPCR_L = 0x0104); +PROVIDE(SFRRPCR_H = 0x0105); +/************************************************************ +* SYS - System Module +************************************************************/ +PROVIDE(SYSCTL = 0x0180); +PROVIDE(SYSCTL_L = 0x0180); +PROVIDE(SYSCTL_H = 0x0181); +PROVIDE(SYSBSLC = 0x0182); +PROVIDE(SYSBSLC_L = 0x0182); +PROVIDE(SYSBSLC_H = 0x0183); +PROVIDE(SYSJMBC = 0x0186); +PROVIDE(SYSJMBC_L = 0x0186); +PROVIDE(SYSJMBC_H = 0x0187); +PROVIDE(SYSJMBI0 = 0x0188); +PROVIDE(SYSJMBI0_L = 0x0188); +PROVIDE(SYSJMBI0_H = 0x0189); +PROVIDE(SYSJMBI1 = 0x018A); +PROVIDE(SYSJMBI1_L = 0x018A); +PROVIDE(SYSJMBI1_H = 0x018B); +PROVIDE(SYSJMBO0 = 0x018C); +PROVIDE(SYSJMBO0_L = 0x018C); +PROVIDE(SYSJMBO0_H = 0x018D); +PROVIDE(SYSJMBO1 = 0x018E); +PROVIDE(SYSJMBO1_L = 0x018E); +PROVIDE(SYSJMBO1_H = 0x018F); +PROVIDE(SYSBERRIV = 0x0198); +PROVIDE(SYSBERRIV_L = 0x0198); +PROVIDE(SYSBERRIV_H = 0x0199); +PROVIDE(SYSUNIV = 0x019A); +PROVIDE(SYSUNIV_L = 0x019A); +PROVIDE(SYSUNIV_H = 0x019B); +PROVIDE(SYSSNIV = 0x019C); +PROVIDE(SYSSNIV_L = 0x019C); +PROVIDE(SYSSNIV_H = 0x019D); +PROVIDE(SYSRSTIV = 0x019E); +PROVIDE(SYSRSTIV_L = 0x019E); +PROVIDE(SYSRSTIV_H = 0x019F); +/************************************************************ +* Timer0_A5 +************************************************************/ +PROVIDE(TA0CTL = 0x0340); +PROVIDE(TA0CCTL0 = 0x0342); +PROVIDE(TA0CCTL1 = 0x0344); +PROVIDE(TA0CCTL2 = 0x0346); +PROVIDE(TA0CCTL3 = 0x0348); +PROVIDE(TA0CCTL4 = 0x034A); +PROVIDE(TA0R = 0x0350); +PROVIDE(TA0CCR0 = 0x0352); +PROVIDE(TA0CCR1 = 0x0354); +PROVIDE(TA0CCR2 = 0x0356); +PROVIDE(TA0CCR3 = 0x0358); +PROVIDE(TA0CCR4 = 0x035A); +PROVIDE(TA0IV = 0x036E); +PROVIDE(TA0EX0 = 0x0360); +/************************************************************ +* Timer1_A3 +************************************************************/ +PROVIDE(TA1CTL = 0x0380); +PROVIDE(TA1CCTL0 = 0x0382); +PROVIDE(TA1CCTL1 = 0x0384); +PROVIDE(TA1CCTL2 = 0x0386); +PROVIDE(TA1R = 0x0390); +PROVIDE(TA1CCR0 = 0x0392); +PROVIDE(TA1CCR1 = 0x0394); +PROVIDE(TA1CCR2 = 0x0396); +PROVIDE(TA1IV = 0x03AE); +PROVIDE(TA1EX0 = 0x03A0); +/************************************************************ +* UNIFIED CLOCK SYSTEM FOR Radio Devices +************************************************************/ +PROVIDE(UCSCTL0 = 0x0160); +PROVIDE(UCSCTL0_L = 0x0160); +PROVIDE(UCSCTL0_H = 0x0161); +PROVIDE(UCSCTL1 = 0x0162); +PROVIDE(UCSCTL1_L = 0x0162); +PROVIDE(UCSCTL1_H = 0x0163); +PROVIDE(UCSCTL2 = 0x0164); +PROVIDE(UCSCTL2_L = 0x0164); +PROVIDE(UCSCTL2_H = 0x0165); +PROVIDE(UCSCTL3 = 0x0166); +PROVIDE(UCSCTL3_L = 0x0166); +PROVIDE(UCSCTL3_H = 0x0167); +PROVIDE(UCSCTL4 = 0x0168); +PROVIDE(UCSCTL4_L = 0x0168); +PROVIDE(UCSCTL4_H = 0x0169); +PROVIDE(UCSCTL5 = 0x016A); +PROVIDE(UCSCTL5_L = 0x016A); +PROVIDE(UCSCTL5_H = 0x016B); +PROVIDE(UCSCTL6 = 0x016C); +PROVIDE(UCSCTL6_L = 0x016C); +PROVIDE(UCSCTL6_H = 0x016D); +PROVIDE(UCSCTL7 = 0x016E); +PROVIDE(UCSCTL7_L = 0x016E); +PROVIDE(UCSCTL7_H = 0x016F); +PROVIDE(UCSCTL8 = 0x0170); +PROVIDE(UCSCTL8_L = 0x0170); +PROVIDE(UCSCTL8_H = 0x0171); +/************************************************************ +* USCI A0 +************************************************************/ +PROVIDE(UCA0CTLW0 = 0x05C0); +PROVIDE(UCA0CTLW0_L = 0x05C0); +PROVIDE(UCA0CTLW0_H = 0x05C1); +PROVIDE(UCA0BRW = 0x05C6); +PROVIDE(UCA0BRW_L = 0x05C6); +PROVIDE(UCA0BRW_H = 0x05C7); +PROVIDE(UCA0MCTL = 0x05C8); +PROVIDE(UCA0STAT = 0x05CA); +PROVIDE(UCA0RXBUF = 0x05CC); +PROVIDE(UCA0TXBUF = 0x05CE); +PROVIDE(UCA0ABCTL = 0x05D0); +PROVIDE(UCA0IRCTL = 0x05D2); +PROVIDE(UCA0IRCTL_L = 0x05D2); +PROVIDE(UCA0IRCTL_H = 0x05D3); +PROVIDE(UCA0ICTL = 0x05DC); +PROVIDE(UCA0ICTL_L = 0x05DC); +PROVIDE(UCA0ICTL_H = 0x05DD); +PROVIDE(UCA0IV = 0x05DE); +/************************************************************ +* USCI B0 +************************************************************/ +PROVIDE(UCB0CTLW0 = 0x05E0); +PROVIDE(UCB0CTLW0_L = 0x05E0); +PROVIDE(UCB0CTLW0_H = 0x05E1); +PROVIDE(UCB0BRW = 0x05E6); +PROVIDE(UCB0BRW_L = 0x05E6); +PROVIDE(UCB0BRW_H = 0x05E7); +PROVIDE(UCB0STAT = 0x05EA); +PROVIDE(UCB0RXBUF = 0x05EC); +PROVIDE(UCB0TXBUF = 0x05EE); +PROVIDE(UCB0I2COA = 0x05F0); +PROVIDE(UCB0I2COA_L = 0x05F0); +PROVIDE(UCB0I2COA_H = 0x05F1); +PROVIDE(UCB0I2CSA = 0x05F2); +PROVIDE(UCB0I2CSA_L = 0x05F2); +PROVIDE(UCB0I2CSA_H = 0x05F3); +PROVIDE(UCB0ICTL = 0x05FC); +PROVIDE(UCB0ICTL_L = 0x05FC); +PROVIDE(UCB0ICTL_H = 0x05FD); +PROVIDE(UCB0IV = 0x05FE); +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ +PROVIDE(WDTCTL = 0x015C); +PROVIDE(WDTCTL_L = 0x015C); +PROVIDE(WDTCTL_H = 0x015D); +/************************************************************ +* TLV Descriptors +************************************************************/ +/************************************************************ +* Interrupt Vectors (offset from 0xFF80) +************************************************************/ +/************************************************************ +* End of Modules +************************************************************/ diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/devices.csv b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/devices.csv new file mode 100644 index 0000000000..5c541e470f --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/devices.csv @@ -0,0 +1,689 @@ +# /* ============================================================================ */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* Copyright (c) 2016, Texas Instruments Incorporated */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* All rights reserved. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* Redistribution and use in source and binary forms, with or without */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* modification, are permitted provided that the following conditions */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* are met: */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* * Redistributions of source code must retain the above copyright */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* notice, this list of conditions and the following disclaimer. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* * Redistributions in binary form must reproduce the above copyright */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* notice, this list of conditions and the following disclaimer in the */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* documentation and/or other materials provided with the distribution. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* * Neither the name of Texas Instruments Incorporated nor the names of */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* its contributors may be used to endorse or promote products derived */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* from this software without specific prior written permission. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +"# /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" */",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# /* ============================================================================ */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Version:,1.208,,,,Date:,08/21/19,15:53:27,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# ============================================================================,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# CPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 0 STD MSP430 CPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 1 MSP430X CPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 2 MSP430XV2 CPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# HWMPY,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 0 No Hardware Multiplier,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 1 16 Bit Hardware Multiplier,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 2 16 Bit Hardware Multiplier with sign Extension (2xx Devices),,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 4 32 Bit Hardware Multiplier,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 8 32 Bit Hardware Multiplier (5xx),,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# SPI2Wire,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 0 JTAG only - no scan,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 1 SBW (default) - scan allowed,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 2 JTAG (Default) - scan allowed,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# 3 SBW only - no scan,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# ============================================================================,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +# Device Name,CPU_TYPE,CPU_Bugs,MPY_TYPE,SBW,EEM,BREAKPOINTS,CLOCKCONTROL,CYCLECOUNTER,STACKSIZE,RAMStart,RAMEnd,RAMStart2,RAMEnd2,TINYRAMStart,TINYRAMEnd,USBRAMStart,USBRAMEnd,LEARAMStart,LEARAMEnd,MirrowedRAMSource,MirrowedRAMStart,MirrowedRAMEnd,BSLStart,BSLSize,BSLEnd,INFOStart,INFOSize,INFOEnd,INFOA,INFOB,INFOC,INFOD,FStart,FEnd,FStart2,FEnd2,Signature_Start,Signature_Size,INTStart,INTEnd +msp430c111,0,0,0,0,NONE,0,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F800,FFDF,0,0,,,FFE0,FFFF +msp430c1111,0,0,0,0,NONE,0,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F800,FFDF,0,0,,,FFE0,FFFF +msp430c112,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430c1121,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430c1331,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430c1351,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF +msp430c311s,0,0,0,0,NONE,0,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F800,FFDF,0,0,,,FFE0,FFFF +msp430c312,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430c313,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430c314,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,D000,FFDF,0,0,,,FFE0,FFFF +msp430c315,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF +msp430c323,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430c325,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF +msp430c336,0,0,1,0,NONE,0,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,A000,FFDF,0,0,,,FFE0,FFFF +msp430c337,0,0,1,0,NONE,0,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8000,FFDF,0,0,,,FFE0,FFFF +msp430c412,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430c413,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430cg4616,1,CPU16,1,0,NONE,0,NONE,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBF,10000,18FFF,,,FFC0,FFFF +msp430cg4617,1,CPU16,1,0,NONE,0,NONE,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBF,10000,19FFF,,,FFC0,FFFF +msp430cg4618,1,CPU16,1,0,NONE,0,NONE,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBF,10000,1FFFF,,,FFC0,FFFF +msp430cg4619,1,CPU16,1,0,NONE,0,NONE,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBF,10000,1FFFF,,,FFC0,FFFF +msp430e112,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430e313,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430e315,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF +msp430e325,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF +msp430e337,0,0,1,0,NONE,0,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8000,FFDF,0,0,,,FFE0,FFFF +msp430f110,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1080,80,10FF,1080,0,0,0,FC00,FFDF,0,0,,,FFE0,FFFF +msp430f1101,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1080,80,10FF,1080,0,0,0,FC00,FFDF,0,0,,,FFE0,FFFF +msp430f1101a,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1080,80,10FF,1080,0,0,0,FC00,FFDF,0,0,,,FFE0,FFFF +msp430f1111,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F800,FFDF,0,0,,,FFE0,FFFF +msp430f1111a,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F800,FFDF,0,0,,,FFE0,FFFF +msp430f112,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430f1121,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430f1121a,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430f1122,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430f1132,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430f122,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430f1222,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430f123,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430f1232,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430f133,0,0,0,0,EMEX_MEDIUM,3,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430f135,0,0,0,0,EMEX_MEDIUM,3,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF 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+msp430f479,0,0,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,1100,FFDF,0,0,,,FFE0,FFFF +msp430fg477,0,CPU19,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDF,0,0,,,FFE0,FFFF +msp430fg478,0,CPU19,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,4000,FFDF,0,0,,,FFE0,FFFF +msp430fg479,0,CPU19,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,1100,FFDF,0,0,,,FFE0,FFFF +msp430f46161,1,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF +msp430f46171,1,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF +msp430f46181,1,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF +msp430f46191,1,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF +msp430f4616,1,CPU16,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF +msp430f4617,1,CPU16,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF +msp430f4618,1,CPU16,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF +msp430f4619,1,CPU16,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF +msp430fg4616,1,CPU16,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF +msp430fg4617,1,CPU16,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF +msp430fg4618,1,CPU16,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF +msp430fg4619,1,CPU16,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF +msp430f5418,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,25BFB,,,FF80,FFFF +msp430f5419,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,25BFB,,,FF80,FFFF +msp430f5435,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,35BFB,,,FF80,FFFF +msp430f5436,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,35BFB,,,FF80,FFFF +msp430f5437,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFB,,,FF80,FFFF +msp430f5438,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFB,,,FF80,FFFF +msp430f5418a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,25BFF,,,FF80,FFFF +msp430f5419a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,25BFF,,,FF80,FFFF +msp430f5435a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,35BFF,,,FF80,FFFF +msp430f5436a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,35BFF,,,FF80,FFFF +msp430f5437a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFF,,,FF80,FFFF +msp430f5438a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFF,,,FF80,FFFF +msp430f5212,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5213,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5214,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5217,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5218,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5219,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5222,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5223,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5224,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5227,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5228,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5229,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5232,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5234,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5237,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5239,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5242,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5244,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5247,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5249,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5304,2,CPU21; CPU22; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF +msp430f5308,2,CPU21; CPU22; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f5309,2,CPU21; CPU22; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A000,FF7F,0,0,,,FF80,FFFF +msp430f5310,2,CPU21; CPU22; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f5340,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5341,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5342,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5324,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5325,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5326,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5327,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5328,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5329,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5500,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF +msp430f5501,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f5502,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A000,FF7F,0,0,,,FF80,FFFF +msp430f5503,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f5504,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF +msp430f5505,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f5506,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A000,FF7F,0,0,,,FF80,FFFF +msp430f5507,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f5508,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f5509,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A000,FF7F,0,0,,,FF80,FFFF +msp430f5510,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f5513,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f5514,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5515,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5517,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,3BFF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5519,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5521,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,3BFF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f5522,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f5524,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5525,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430f5526,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,3BFF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5527,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,3BFF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF +msp430f5528,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430f5529,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430p112,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF +msp430p313,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF +msp430p315,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF +msp430p315s,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF +msp430p325,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF +msp430p337,0,0,1,0,NONE,0,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8000,FFDF,0,0,,,FFE0,FFFF +cc430f5133,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF +cc430f5135,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +cc430f5137,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +cc430f6125,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +cc430f6126,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +cc430f6127,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +cc430f6135,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +cc430f6137,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +cc430f5123,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF +cc430f5125,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +cc430f5143,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF +cc430f5145,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +cc430f5147,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +cc430f6143,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF +cc430f6145,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +cc430f6147,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f5333,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f5335,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f5336,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f5338,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f5630,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f5631,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF +msp430f5632,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f5633,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f5634,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF +msp430f5635,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f5636,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f5637,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF +msp430f5638,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f6433,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f6435,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f6436,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f6438,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f6630,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f6631,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF +msp430f6632,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f6633,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f6634,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF +msp430f6635,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f6636,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF +msp430f6637,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF +msp430f6638,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF +msp430f5358,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,F8000,FBFFF,0,0,0,0,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,67FFF,,,FF80,FFFF +msp430f5359,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,F0000,FBFFF,0,0,0,0,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,87FFF,,,FF80,FFFF +msp430f5658,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,F8000,FBFFF,0,0,1C00,23FF,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,67FFF,,,FF80,FFFF +msp430f5659,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,F0000,FBFFF,0,0,1C00,23FF,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,87FFF,,,FF80,FFFF +msp430f6458,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,F8000,FBFFF,0,0,0,0,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,67FFF,,,FF80,FFFF +msp430f6459,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,F0000,FBFFF,0,0,0,0,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,87FFF,,,FF80,FFFF +msp430f6658,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,F8000,FBFFF,0,0,1C00,23FF,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,67FFF,,,FF80,FFFF +msp430f6659,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,F0000,FBFFF,0,0,1C00,23FF,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,87FFF,,,FF80,FFFF +msp430fg6425,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430fg6426,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430fg6625,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF +msp430fg6626,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF +msp430l092,0,CPU21; CPU22; CPU40,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,2380,23FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1C00,60,1C5F,1C00,0,0,0,1C80,237F,0,0,,,1C60,1C7F +msp430c091,0,CPU21; CPU22; CPU40,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,2380,23FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1C00,60,1C5F,1C00,0,0,0,FC80,FFDF,0,0,,,FFE0,FFFF +msp430c092,0,CPU21; CPU22; CPU40,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,2380,23FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1C00,60,1C5F,1C00,0,0,0,F880,FFDF,0,0,,,FFE0,FFFF +msp430xgeneric,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF +msp430f5xx_6xxgeneric,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF +msp430fr5xx_6xxgeneric,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF +msp430fr2xx_4xxgeneric,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF +msp430fr57xxgeneric,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF +msp430i2xxgeneric,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,C000,FFDB,0,0,FFDC,4,FF80,FFFF +msp430f5131,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF +msp430f5151,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f5171,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f5132,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF +msp430f5152,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f5172,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f6720,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f6721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f6723,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF +msp430f6724,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,1BFFF,,,FF80,FFFF +msp430f6725,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f6726,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f6730,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f6731,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f6733,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF +msp430f6734,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,1BFFF,,,FF80,FFFF +msp430f6735,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f6736,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f67621,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF +msp430f67641,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f6720a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f6721a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f6723a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF +msp430f6724a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,1BFFF,,,FF80,FFFF +msp430f6725a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f6726a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f6730a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430f6731a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +msp430f6733a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF +msp430f6734a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,1BFFF,,,FF80,FFFF +msp430f6735a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f6736a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f67621a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF +msp430f67641a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF +msp430f67451,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f67651,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f67751,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f67461,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67661,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67761,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67471,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67671,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67771,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67481,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67681,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67781,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67491,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67691,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67791,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6745,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f6765,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f6775,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f6746,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6766,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6776,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6747,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6767,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6777,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6748,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6768,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6778,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6749,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6769,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6779,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67451a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f67651a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f67751a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f67461a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67661a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67761a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67471a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67671a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67771a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f67481a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67681a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67781a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67491a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67691a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f67791a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6745a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f6765a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f6775a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF +msp430f6746a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6766a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6776a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6747a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6767a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6777a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF +msp430f6748a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6768a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6778a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6749a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6769a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430f6779a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF +msp430fr5720,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,F000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,F000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5722,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5723,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5724,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5725,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5726,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5727,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5728,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5729,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5730,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,F000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5731,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,F000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5732,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5733,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5734,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5735,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5736,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5737,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5738,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5739,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF +msp430g2211,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF +msp430g2201,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF +msp430g2111,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF +msp430g2101,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF +msp430g2001,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FE00,FFDF,0,0,,,FFE0,FFFF +msp430g2231,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF +msp430g2221,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF +msp430g2131,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF +msp430g2121,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF +msp430afe221,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF +msp430afe231,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF +msp430afe251,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDF,0,0,,,FFE0,FFFF +msp430afe222,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF +msp430afe232,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF +msp430afe252,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDF,0,0,,,FFE0,FFFF +msp430afe223,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF +msp430afe233,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF +msp430afe253,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDF,0,0,,,FFE0,FFFF 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+msp430g2352,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF +msp430g2452,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF +msp430g2113,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2213,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2313,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2413,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2513,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2153,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2253,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2353,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2453,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2553,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2203,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2303,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2403,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2233,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2333,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2433,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2533,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430tch5e,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2444,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2544,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2744,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2755,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2855,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,4000,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2955,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFDD,0,0,FFDE,2,FFE0,FFFF +msp430g2230,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF +msp430g2210,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF +msp430bt5190,2,CPU21; CPU22; CPU23; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFF,,,FF80,FFFF +msp430fr5857,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5858,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5859,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr5847,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr58471,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5848,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5849,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr5867,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr58671,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5868,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5869,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr5957,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5958,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5959,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr5947,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr59471,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5948,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5949,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr5967,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5968,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5969,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr59691,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430i2020,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,C000,FFDB,0,0,FFDC,4,FFE0,FFFF +msp430i2021,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,8000,FFDB,0,0,FFDC,4,FFE0,FFFF +msp430i2030,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,C000,FFDB,0,0,FFDC,4,FFE0,FFFF +msp430i2031,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,8000,FFDB,0,0,FFDC,4,FFE0,FFFF +msp430i2040,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,C000,FFDB,0,0,FFDC,4,FFE0,FFFF +msp430i2041,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,8000,FFDB,0,0,FFDC,4,FFE0,FFFF +rf430frl152h,0,CPU21; CPU22; CPU40,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF +rf430frl153h,0,CPU21; CPU22; CPU40,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF +rf430frl154h,0,CPU21; CPU22; CPU40,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF +rf430frl152h_rom,0,CPU21; CPU22; CPU40,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,1DFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF +rf430frl153h_rom,0,CPU21; CPU22; CPU40,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,1DFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF +rf430frl154h_rom,0,CPU21; CPU22; CPU40,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,1DFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF +rf430f5175,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF +rf430f5155,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +rf430f5144,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF +msp430fr69271,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr68791,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr69791,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr6927,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr6928,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF +msp430fr6877,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr6977,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr6879,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr6979,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr58891,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr68891,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr59891,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr69891,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr5887,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr5888,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF +msp430fr5889,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr6887,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr6888,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF +msp430fr6889,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr5986,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5987,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr5988,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF +msp430fr5989,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr6987,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr6988,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF +msp430fr6989,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr5922,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr5870,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5970,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5872,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr5972,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr6820,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr6920,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr6822,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr6922,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr6870,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr6970,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr6872,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr6972,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr59221,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr58721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr59721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr68221,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr69221,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr68721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430fr69721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF +msp430sl5438a,2,CPU21; CPU22; CPU23; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFF,,,FF80,FFFF +msp430fr4131,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,21FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,F000,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr4132,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,E000,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr4133,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2032,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,E000,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2033,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2110,2,CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,0,0,0,0,0,0,0,F800,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2111,2,CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,0,0,0,0,0,0,0,F100,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2310,2,CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,F800,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2311,2,CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,F100,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2433,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,2FFF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2532,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,E000,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2533,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2632,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,E000,FF7F,0,0,FF80,8,FF88,FFFF +msp430fr2633,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,2FFF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF +msp430f5252,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF +msp430f5253,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF +msp430f5254,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,A3FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF +msp430f5255,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,A3FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF +msp430f5256,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF +msp430f5257,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF +msp430f5258,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,A3FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF +msp430f5259,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,A3FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF 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+msp430fr2475,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,2FFF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,8000,FF7F,0,0,FF80,22,FFA2,FFFF +msp430fr50431,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,6000,FF7F,10000,15FFF,FF80,10,FF90,FFFF +msp430fr6041,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr6043,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,6000,FF7F,10000,15FFF,FF80,10,FF90,FFFF +msp430fr5041,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,8000,FF7F,0,0,FF80,10,FF90,FFFF +msp430fr5043,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,6000,FF7F,10000,15FFF,FF80,10,FF90,FFFF +msp430fr60431,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,6000,FF7F,10000,15FFF,FF80,10,FF90,FFFF +msp430fr6037,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF +msp430fr6035,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr60471,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF +msp430fr60371,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF +msp430fr6045,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,23FFF,FF80,10,FF90,FFFF +msp430fr6047,2,CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/in430.h b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/in430.h new file mode 100644 index 0000000000..b5cd47bde9 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/in430.h @@ -0,0 +1,345 @@ +/******************************************************************************* + * in430.h - + * + * Copyright (C) 2003-2019 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +/* 1.208 */ + +#ifndef __IN430_H__ +#define __IN430_H__ + +/* Definitions for projects using the GNU C/C++ compiler */ +#if !defined(__ASSEMBLER__) + +/* Definitions of things which are intrinsics with IAR and CCS, but which don't + appear to be intrinsics with the GCC compiler */ + +/* The data type used to hold interrupt state */ +typedef unsigned int __istate_t; + +#define _no_operation() __asm__ __volatile__ ("nop") + +#define _get_interrupt_state() \ +({ \ + unsigned int __x; \ + __asm__ __volatile__( \ + "mov SR, %0" \ + : "=r" ((unsigned int) __x) \ + :); \ + __x; \ +}) + +#if defined(__MSP430_HAS_MSP430XV2_CPU__) || defined(__MSP430_HAS_MSP430X_CPU__) +#define _set_interrupt_state(x) \ +({ \ + __asm__ __volatile__ ("nop { mov %0, SR { nop" \ + : : "ri"((unsigned int) x) \ + );\ +}) + +#define _enable_interrupts() __asm__ __volatile__ ("nop { eint { nop") + +#define _bis_SR_register(x) \ + __asm__ __volatile__ ("nop { bis.w %0, SR { nop" \ + : : "ri"((unsigned int) x) \ + ) +#else + +#define _set_interrupt_state(x) \ +({ \ + __asm__ __volatile__ ("mov %0, SR { nop" \ + : : "ri"((unsigned int) x) \ + );\ +}) + +#define _enable_interrupts() __asm__ __volatile__ ("eint") + +#define _bis_SR_register(x) \ + __asm__ __volatile__ ("bis.w %0, SR" \ + : : "ri"((unsigned int) x) \ + ) + +#endif + +#define _disable_interrupts() __asm__ __volatile__ ("dint { nop") + +#define _bic_SR_register(x) \ + __asm__ __volatile__ ("bic.w %0, SR { nop" \ + : : "ri"((unsigned int) x) \ + ) + +#define _get_SR_register() \ +({ \ + unsigned int __x; \ + __asm__ __volatile__( \ + "mov SR, %0" \ + : "=r" ((unsigned int) __x) \ + :); \ + __x; \ +}) + +#define _swap_bytes(x) \ +({ \ + unsigned int __dst = x; \ + __asm__ __volatile__( \ + "swpb %0" \ + : "+r" ((unsigned int) __dst) \ + :); \ + __dst; \ +}) + +/* Alternative names for GCC built-ins */ +#define _bic_SR_register_on_exit(x) __bic_SR_register_on_exit(x) +#define _bis_SR_register_on_exit(x) __bis_SR_register_on_exit(x) + +/* Additional intrinsics provided for IAR/CCS compatibility */ +#define _bcd_add_short(x,y) \ +({ \ + unsigned short __z = ((unsigned short) y); \ + __asm__ __volatile__( \ + "clrc \n\t" \ + "dadd.w %1, %0" \ + : "+r" ((unsigned short) __z) \ + : "ri" ((unsigned short) x) \ + ); \ + __z; \ +}) + +#define __bcd_add_short(x,y) _bcd_add_short(x,y) + +#define _bcd_add_long(x,y) \ +({ \ + unsigned long __z = ((unsigned long) y); \ + __asm__ __volatile__( \ + "clrc \n\t" \ + "dadd.w %L1, %L0 \n\t" \ + "dadd.w %H1, %H0" \ + : "+r" ((unsigned long) __z) \ + : "ri" ((unsigned long) x) \ + ); \ + __z; \ + }) + +#define __bcd_add_long(x,y) _bcd_add_long(x,y) + +#define _get_SP_register() \ +({ \ + unsigned int __x; \ + __asm__ __volatile__( \ + "mov SP, %0" \ + : "=r" ((unsigned int) __x) \ + :); \ + __x; \ +}) + +#define __get_SP_register() _get_SP_register() + +#define _set_SP_register(x) \ +({ \ + __asm__ __volatile__ ("mov %0, SP" \ + : : "ri"((unsigned int) x) \ + );\ +}) + +#define __set_SP_register(x) _set_SP_register(x) + +#define _data16_write_addr(addr,src) \ +({ \ + unsigned long __src = src; \ + __asm__ __volatile__ ( \ + "movx.a %1, 0(%0)" \ + : : "r"((unsigned int) addr), "m"((unsigned long) __src) \ + ); \ +}) + +#define __data16_write_addr(addr,src) _data16_write_addr(addr,src) + +#define _data16_read_addr(addr) \ +({ \ + unsigned long __dst; \ + __asm__ __volatile__ ( \ + "movx.a @%1, %0" \ + : "=m"((unsigned long) __dst) \ + : "r"((unsigned int) addr) \ + ); \ + __dst; \ +}) + +#define __data16_read_addr(addr) _data16_read_addr(addr) + +#define _data20_write_char(addr,src) \ +({ \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %1, %0 \n\t" \ + "mov.b %2, 0(%0)" \ + : "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr), "ri"((char) src) \ + ); \ +}) + +#define __data20_write_char(addr,src) _data20_write_char(addr,src) + +#define _data20_read_char(addr) \ +({ \ + char __dst; \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %2, %1 \n\t" \ + "mov.b 0(%1), %0" \ + : "=r"((char) __dst), "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr) \ + ); \ + __dst ; \ +}) + +#define __data20_read_char(addr) _data20_read_char(addr) + +#define _data20_write_short(addr,src) \ +({ \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %1, %0 \n\t" \ + "mov.w %2, 0(%0)" \ + : "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr), "ri"((short) src) \ + ); \ +}) + +#define __data20_write_short(addr,src) _data20_write_short(addr,src) + +#define _data20_read_short(addr) \ +({ \ + short __dst; \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %2, %1 \n\t" \ + "mov.w 0(%1), %0" \ + : "=r"((short) __dst), "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr) \ + ); \ + __dst ; \ +}) + +#define __data20_read_short(addr) _data20_read_short(addr) + +#define _data20_write_long(addr,src) \ +({ \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %1, %0 \n\t" \ + "mov.w %L2, 0(%0) \n\t" \ + "mov.w %H2, 2(%0)" \ + : "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr), "ri"((long) src) \ + ); \ +}) + +#define __data20_write_long(addr,src) _data20_write_long(addr,src) + +#define _data20_read_long(addr) \ +({ \ + long __dst; \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %2, %1 \n\t" \ + "mov.w 0(%1), %L0 \n\t" \ + "mov.w 2(%1), %H0" \ + : "=r"((long) __dst), "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr) \ + ); \ + __dst ; \ +}) + +#define __data20_read_long(addr) _data20_read_long(addr) + +#define _low_power_mode_0() _bis_SR_register(0x18) +#define _low_power_mode_1() _bis_SR_register(0x58) +#define _low_power_mode_2() _bis_SR_register(0x98) +#define _low_power_mode_3() _bis_SR_register(0xD8) +#define _low_power_mode_4() _bis_SR_register(0xF8) +#define _low_power_mode_off_on_exit() _bic_SR_register_on_exit(0xF0) + +#define __low_power_mode_0() _low_power_mode_0() +#define __low_power_mode_1() _low_power_mode_1() +#define __low_power_mode_2() _low_power_mode_2() +#define __low_power_mode_3() _low_power_mode_3() +#define __low_power_mode_4() _low_power_mode_4() +#define __low_power_mode_off_on_exit() _low_power_mode_off_on_exit() + +#define _even_in_range(x,y) (x) +#define __even_in_range(x,y) _even_in_range(x,y) + +/* Define some alternative names for the intrinsics, which have been used + in the various versions of IAR and GCC */ +#define __no_operation() _no_operation() + +#define __get_interrupt_state() _get_interrupt_state() +#define __set_interrupt_state(x) _set_interrupt_state(x) +#define __enable_interrupt() _enable_interrupts() +#define __disable_interrupt() _disable_interrupts() + +#define __bic_SR_register(x) _bic_SR_register(x) +#define __bis_SR_register(x) _bis_SR_register(x) +#define __get_SR_register() _get_SR_register() + +#define __swap_bytes(x) _swap_bytes(x) + +#define __nop() _no_operation() + +#define __eint() _enable_interrupts() +#define __dint() _disable_interrupts() + +#define _NOP() _no_operation() +#define _EINT() _enable_interrupts() +#define _DINT() _disable_interrupts() + +#define _BIC_SR(x) _bic_SR_register(x) +#define _BIC_SR_IRQ(x) _bic_SR_register_on_exit(x) +#define _BIS_SR(x) _bis_SR_register(x) +#define _BIS_SR_IRQ(x) _bis_SR_register_on_exit(x) +#define _BIS_NMI_IE1(x) _bis_nmi_ie1(x) + +#define _SWAP_BYTES(x) _swap_bytes(x) + +#define __no_init __attribute__((noinit)) + +#endif /* !defined _GNU_ASSEMBLER_ */ + +#endif /* __IN430_H__ */ diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/iomacros.h b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/iomacros.h new file mode 100644 index 0000000000..3c071be4d1 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/iomacros.h @@ -0,0 +1,87 @@ +/******************************************************************************* + * iomacros.h - + * + * Copyright (C) 2003-2019 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +/* 1.208 */ + +#if !defined(_IOMACROS_H_) +#define _IOMACROS_H_ + + +#if defined(__ASSEMBLER__) + +/* Definitions for assembly compilation using the GNU assembler */ +#define sfrb(x,x_) x=x_ +#define sfrw(x,x_) x=x_ +#define sfra(x,x_) x=x_ +#define sfrl(x,x_) x=x_ + +#define const_sfrb(x,x_) x=x_ +#define const_sfrw(x,x_) x=x_ +#define const_sfra(x,x_) x=x_ +#define const_sfrl(x,x_) x=x_ + +#define sfr_b(x) +#define sfr_w(x) +#define sfr_a(x) +#define sfr_l(x) + +#else + +#define sfr_b(x) extern volatile unsigned char x +#define sfr_w(x) extern volatile unsigned int x +#define sfr_a(x) extern volatile unsigned long int x +#define sfr_l(x) extern volatile unsigned long int x + +#define sfrb_(x,x_) extern volatile unsigned char x __asm__(#x_) +#define sfrw_(x,x_) extern volatile unsigned int x __asm__(#x_) +#define sfra_(x,x_) extern volatile unsigned long int x __asm__(#x_) +#define sfrl_(x,x_) extern volatile unsigned long int x __asm__(#x_) + +#define sfrb(x,x_) sfrb_(x,x_) +#define sfrw(x,x_) sfrw_(x,x_) +#define sfra(x,x_) sfra_(x,x_) +#define sfrl(x,x_) sfrl_(x,x_) + +#define const_sfrb(x,x_) const sfrb_(x,x_) +#define const_sfrw(x,x_) const sfrw_(x,x_) +#define const_sfra(x,x_) const sfra_(x,x_) +#define const_sfrl(x,x_) const sfrl_(x,x_) + +#define __interrupt __attribute__((__interrupt__)) +#define __interrupt_vec(vec) __attribute__((interrupt(vec))) + +#endif /* defined(__ASSEMBLER__) */ + +#endif /* _IOMACROS_H_ */ diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/legacy.h b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/legacy.h new file mode 100644 index 0000000000..08759b88be --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/legacy.h @@ -0,0 +1,2355 @@ +//***************************************************************************** +// +// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//**************************************************************************** + + +/************************************************************ +* ADC +************************************************************/ + +#ifdef __MSP430_HAS_ADC__ + +#define ADCIV_ADCHIIFG ADCIV__ADCHIIFG +#define ADCIV_ADCIFG ADCIV__ADCIFG0 +#define ADCIV_ADCINIFG ADCIV__ADCINIFG +#define ADCIV_ADCLOIFG ADCIV__ADCLOIFG +#define ADCIV_ADCOVIFG ADCIV__ADCOVIFG +#define ADCIV_ADCTOVIFG ADCIV__ADCTOVIFG +#define ADCIV_NONE ADCIV__NONE + +#endif + +/************************************************************ +* ADC12_B +************************************************************/ +#ifdef __MSP430_HAS_ADC12_B__ + +#define ADC12_VECTOR ADC12_B_VECTOR + +#define ADC12IV_NONE ADC12IV__NONE +#define ADC12IV_ADC12HIIFG ADC12IV__ADC12HIIFG +#define ADC12IV_ADC12IFG0 ADC12IV__ADC12IFG0 +#define ADC12IV_ADC12IFG1 ADC12IV__ADC12IFG1 +#define ADC12IV_ADC12IFG2 ADC12IV__ADC12IFG2 +#define ADC12IV_ADC12IFG3 ADC12IV__ADC12IFG3 +#define ADC12IV_ADC12IFG4 ADC12IV__ADC12IFG4 +#define ADC12IV_ADC12IFG5 ADC12IV__ADC12IFG5 +#define ADC12IV_ADC12IFG6 ADC12IV__ADC12IFG6 +#define ADC12IV_ADC12IFG7 ADC12IV__ADC12IFG7 +#define ADC12IV_ADC12IFG8 ADC12IV__ADC12IFG8 +#define ADC12IV_ADC12IFG9 ADC12IV__ADC12IFG9 +#define ADC12IV_ADC12IFG10 ADC12IV__ADC12IFG10 +#define ADC12IV_ADC12IFG11 ADC12IV__ADC12IFG11 +#define ADC12IV_ADC12IFG12 ADC12IV__ADC12IFG12 +#define ADC12IV_ADC12IFG13 ADC12IV__ADC12IFG13 +#define ADC12IV_ADC12IFG14 ADC12IV__ADC12IFG14 +#define ADC12IV_ADC12IFG15 ADC12IV__ADC12IFG15 +#define ADC12IV_ADC12IFG16 ADC12IV__ADC12IFG16 +#define ADC12IV_ADC12IFG17 ADC12IV__ADC12IFG17 +#define ADC12IV_ADC12IFG18 ADC12IV__ADC12IFG18 +#define ADC12IV_ADC12IFG19 ADC12IV__ADC12IFG19 +#define ADC12IV_ADC12IFG20 ADC12IV__ADC12IFG20 +#define ADC12IV_ADC12IFG21 ADC12IV__ADC12IFG21 +#define ADC12IV_ADC12IFG22 ADC12IV__ADC12IFG22 +#define ADC12IV_ADC12IFG23 ADC12IV__ADC12IFG23 +#define ADC12IV_ADC12IFG24 ADC12IV__ADC12IFG24 +#define ADC12IV_ADC12IFG25 ADC12IV__ADC12IFG25 +#define ADC12IV_ADC12IFG26 ADC12IV__ADC12IFG26 +#define ADC12IV_ADC12IFG27 ADC12IV__ADC12IFG27 +#define ADC12IV_ADC12IFG28 ADC12IV__ADC12IFG28 +#define ADC12IV_ADC12IFG29 ADC12IV__ADC12IFG29 +#define ADC12IV_ADC12IFG30 ADC12IV__ADC12IFG30 +#define ADC12IV_ADC12IFG31 ADC12IV__ADC12IFG31 +#define ADC12IV_ADC12INIFG ADC12IV__ADC12INIFG +#define ADC12IV_ADC12LOIFG ADC12IV__ADC12LOIFG +#define ADC12IV_ADC12OVIFG ADC12IV__ADC12OVIFG +#define ADC12IV_ADC12RDYIFG ADC12IV__ADC12RDYIFG +#define ADC12IV_ADC12TOVIFG ADC12IV__ADC12TOVIFG + +#endif + +/************************************************************ +* CAP TOUCH +************************************************************/ + +#ifdef __MSP430_HAS_CAPTIO0__ +#define __MSP430_HAS_CAP_TOUCH_IO_0__ +#define CAP_TOUCH_0_BASE CAPTIO0_BASE +#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_0__ CAPTIO0_BASE +#define CAPSIO0CTL CAPTIO0CTL +#endif +#ifdef __MSP430_HAS_CAPTIO1__ +#define __MSP430_HAS_CAP_TOUCH_IO_1__ +#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_1__ CAPTIO1_BASE +#define CAP_TOUCH_1_BASE CAPTIO1_BASE +#define CAPSIO1CTL CAPTIO1CTL +#endif + +#ifdef __MSP430_HAS_CAPTIOx__ + +#define CAPSIOPISEL0 CAPTIOPISEL0 +#define CAPSIOPISEL1 CAPTIOPISEL1 +#define CAPSIOPISEL2 CAPTIOPISEL2 +#define CAPSIOPOSEL0 CAPTIOPOSEL0 +#define CAPSIOPOSEL1 CAPTIOPOSEL1 +#define CAPSIOPOSEL2 CAPTIOPOSEL2 +#define CAPSIOPOSEL3 CAPTIOPOSEL3 +#define CAPSIOEN CAPTIOEN +#define CAPSIO CAPTIO + +#endif + +/************************************************************ +* CLOCK SYSTEM +************************************************************/ + +#ifdef __MSP430_HAS_CS__ + +#ifdef __MSP430FR2XX_FR4XX_FAMILY__ + +#define DCOFTRIM_0 (0x0000) /* DCO frequency trim: 0 */ +#define DCOFTRIM_1 (0x0010) /* DCO frequency trim: 1 */ +#define DCOFTRIM_2 (0x0020) /* DCO frequency trim: 2 */ +#define DCOFTRIM_3 (0x0030) /* DCO frequency trim: 3 */ +#define DCOFTRIM_4 (0x0040) /* DCO frequency trim: 4 */ +#define DCOFTRIM_5 (0x0050) /* DCO frequency trim: 5 */ +#define DCOFTRIM_6 (0x0060) /* DCO frequency trim: 6 */ +#define DCOFTRIM_7 (0x0070) /* DCO frequency trim: 7 */ + +#endif + +#define SELM__LFMODOSC SELM__LFMODCLK +#define SELM__MODOSC SELM__MODCLK +#define SELS__LFMODOSC SELS__LFMODCLK +#define SELS__MODOSC SELS__MODCLK +#define SELA__LFMODOSC SELA__LFMODCLK + +#define SELA_7 SELA +#define SELM_7 SELM +#define SELS_7 SELS + +#ifndef MODCLKREQEN +#define MODCLKREQEN MODOSCREQEN +#define MODCLKREQEN_L MODOSCREQEN_L +#endif + +#endif + +/************************************************************ +* COMP_E +************************************************************/ + +#ifdef __MSP430_HAS_COMP_E__ + +#define CEIV_CEIFG CEIV__CEIFG +#define CEIV_CEIIFG CEIV__CEIIFG +#define CEIV_CERDYIFG CEIV__CERDYIFG +#define CEIV_NONE CEIV__NONE + +#define CEPWRMD_3 CEPWRMD + +#define CEREF0_0 (0x0000) /* Comp. E Int. Ref.0 Select 0 : 1/32 */ +#define CEREF0_1 (0x0001) /* Comp. E Int. Ref.0 Select 1 : 2/32 */ +#define CEREF0_2 (0x0002) /* Comp. E Int. Ref.0 Select 2 : 3/32 */ +#define CEREF0_3 (0x0003) /* Comp. E Int. Ref.0 Select 3 : 4/32 */ +#define CEREF0_4 (0x0004) /* Comp. E Int. Ref.0 Select 4 : 5/32 */ +#define CEREF0_5 (0x0005) /* Comp. E Int. Ref.0 Select 5 : 6/32 */ +#define CEREF0_6 (0x0006) /* Comp. E Int. Ref.0 Select 6 : 7/32 */ +#define CEREF0_7 (0x0007) /* Comp. E Int. Ref.0 Select 7 : 8/32 */ +#define CEREF0_8 (0x0008) /* Comp. E Int. Ref.0 Select 0 : 9/32 */ +#define CEREF0_9 (0x0009) /* Comp. E Int. Ref.0 Select 1 : 10/32 */ +#define CEREF0_10 (0x000A) /* Comp. E Int. Ref.0 Select 2 : 11/32 */ +#define CEREF0_11 (0x000B) /* Comp. E Int. Ref.0 Select 3 : 12/32 */ +#define CEREF0_12 (0x000C) /* Comp. E Int. Ref.0 Select 4 : 13/32 */ +#define CEREF0_13 (0x000D) /* Comp. E Int. Ref.0 Select 5 : 14/32 */ +#define CEREF0_14 (0x000E) /* Comp. E Int. Ref.0 Select 6 : 15/32 */ +#define CEREF0_15 (0x000F) /* Comp. E Int. Ref.0 Select 7 : 16/32 */ +#define CEREF0_16 (0x0010) /* Comp. E Int. Ref.0 Select 0 : 17/32 */ +#define CEREF0_17 (0x0011) /* Comp. E Int. Ref.0 Select 1 : 18/32 */ +#define CEREF0_18 (0x0012) /* Comp. E Int. Ref.0 Select 2 : 19/32 */ +#define CEREF0_19 (0x0013) /* Comp. E Int. Ref.0 Select 3 : 20/32 */ +#define CEREF0_20 (0x0014) /* Comp. E Int. Ref.0 Select 4 : 21/32 */ +#define CEREF0_21 (0x0015) /* Comp. E Int. Ref.0 Select 5 : 22/32 */ +#define CEREF0_22 (0x0016) /* Comp. E Int. Ref.0 Select 6 : 23/32 */ +#define CEREF0_23 (0x0017) /* Comp. E Int. Ref.0 Select 7 : 24/32 */ +#define CEREF0_24 (0x0018) /* Comp. E Int. Ref.0 Select 0 : 25/32 */ +#define CEREF0_25 (0x0019) /* Comp. E Int. Ref.0 Select 1 : 26/32 */ +#define CEREF0_26 (0x001A) /* Comp. E Int. Ref.0 Select 2 : 27/32 */ +#define CEREF0_27 (0x001B) /* Comp. E Int. Ref.0 Select 3 : 28/32 */ +#define CEREF0_28 (0x001C) /* Comp. E Int. Ref.0 Select 4 : 29/32 */ +#define CEREF0_29 (0x001D) /* Comp. E Int. Ref.0 Select 5 : 30/32 */ +#define CEREF0_30 (0x001E) /* Comp. E Int. Ref.0 Select 6 : 31/32 */ +#define CEREF0_31 (0x001F) /* Comp. E Int. Ref.0 Select 7 : 32/32 */ +#define CEREF1_0 (0x0000) /* Comp. E Int. Ref.1 Select 0 : 1/32 */ + +#define CEREF1_1 (0x0100) /* Comp. E Int. Ref.1 Select 1 : 2/32 */ +#define CEREF1_2 (0x0200) /* Comp. E Int. Ref.1 Select 2 : 3/32 */ +#define CEREF1_3 (0x0300) /* Comp. E Int. Ref.1 Select 3 : 4/32 */ +#define CEREF1_4 (0x0400) /* Comp. E Int. Ref.1 Select 4 : 5/32 */ +#define CEREF1_5 (0x0500) /* Comp. E Int. Ref.1 Select 5 : 6/32 */ +#define CEREF1_6 (0x0600) /* Comp. E Int. Ref.1 Select 6 : 7/32 */ +#define CEREF1_7 (0x0700) /* Comp. E Int. Ref.1 Select 7 : 8/32 */ +#define CEREF1_8 (0x0800) /* Comp. E Int. Ref.1 Select 0 : 9/32 */ +#define CEREF1_9 (0x0900) /* Comp. E Int. Ref.1 Select 1 : 10/32 */ +#define CEREF1_10 (0x0A00) /* Comp. E Int. Ref.1 Select 2 : 11/32 */ +#define CEREF1_11 (0x0B00) /* Comp. E Int. Ref.1 Select 3 : 12/32 */ +#define CEREF1_12 (0x0C00) /* Comp. E Int. Ref.1 Select 4 : 13/32 */ +#define CEREF1_13 (0x0D00) /* Comp. E Int. Ref.1 Select 5 : 14/32 */ +#define CEREF1_14 (0x0E00) /* Comp. E Int. Ref.1 Select 6 : 15/32 */ +#define CEREF1_15 (0x0F00) /* Comp. E Int. Ref.1 Select 7 : 16/32 */ +#define CEREF1_16 (0x1000) /* Comp. E Int. Ref.1 Select 0 : 17/32 */ +#define CEREF1_17 (0x1100) /* Comp. E Int. Ref.1 Select 1 : 18/32 */ +#define CEREF1_18 (0x1200) /* Comp. E Int. Ref.1 Select 2 : 19/32 */ +#define CEREF1_19 (0x1300) /* Comp. E Int. Ref.1 Select 3 : 20/32 */ +#define CEREF1_20 (0x1400) /* Comp. E Int. Ref.1 Select 4 : 21/32 */ +#define CEREF1_21 (0x1500) /* Comp. E Int. Ref.1 Select 5 : 22/32 */ +#define CEREF1_22 (0x1600) /* Comp. E Int. Ref.1 Select 6 : 23/32 */ +#define CEREF1_23 (0x1700) /* Comp. E Int. Ref.1 Select 7 : 24/32 */ +#define CEREF1_24 (0x1800) /* Comp. E Int. Ref.1 Select 0 : 25/32 */ +#define CEREF1_25 (0x1900) /* Comp. E Int. Ref.1 Select 1 : 26/32 */ +#define CEREF1_26 (0x1A00) /* Comp. E Int. Ref.1 Select 2 : 27/32 */ +#define CEREF1_27 (0x1B00) /* Comp. E Int. Ref.1 Select 3 : 28/32 */ +#define CEREF1_28 (0x1C00) /* Comp. E Int. Ref.1 Select 4 : 29/32 */ +#define CEREF1_29 (0x1D00) /* Comp. E Int. Ref.1 Select 5 : 30/32 */ +#define CEREF1_30 (0x1E00) /* Comp. E Int. Ref.1 Select 6 : 31/32 */ +#define CEREF1_31 (0x1F00) /* Comp. E Int. Ref.1 Select 7 : 32/32 */ + +#endif + +/************************************************************ +* CRC32 +************************************************************/ + +#ifdef __MSP430_HAS_CRC32__ + +#define CRC32DIB0 CRC32DIW0_L +#define CRC32DIRBB0 CRC32DIRBW0_H +#define CRC32RESB0 CRC32INIRESW0_L +#define CRC32RESB1 CRC32INIRESW0_H +#define CRC32RESB2 CRC32INIRESW1_L +#define CRC32RESB3 CRC32INIRESW1_H +#define CRC32RESRB3 CRC32RESRW1_L +#define CRC32RESRB2 CRC32RESRW1_H +#define CRC32RESRB1 CRC32RESRW0_L +#define CRC32RESRB0 CRC32RESRW0_H +#define CRC16DIB0 CRC16DIW0_L +#define CRC16DIRBB0 CRC16DIRBW0_L +#define CRC16INIRESB1 CRC16INIRESW0_H +#define CRC16INIRESB0 CRC16INIRESW0_L +#define CRC16RESRB1 CRC16RESRW0_L +#define CRC16RESRB0 CRC16RESRW0_H + +#endif + +/************************************************************ +* DIO +************************************************************/ + +#ifdef __MSP430_HAS_DIO__ + +#ifdef __MSP430_HAS_PORT1_R__ +#define P1IV_NONE P1IV__NONE +#define P1IV_P1IFG0 P1IV__P1IFG0 +#define P1IV_P1IFG1 P1IV__P1IFG1 +#define P1IV_P1IFG2 P1IV__P1IFG2 +#define P1IV_P1IFG3 P1IV__P1IFG3 +#define P1IV_P1IFG4 P1IV__P1IFG4 +#define P1IV_P1IFG5 P1IV__P1IFG5 +#define P1IV_P1IFG6 P1IV__P1IFG6 +#define P1IV_P1IFG7 P1IV__P1IFG7 +#endif +#ifdef __MSP430_HAS_PORT2_R__ +#define P2IV_NONE P2IV__NONE +#define P2IV_P2IFG0 P2IV__P2IFG0 +#define P2IV_P2IFG1 P2IV__P2IFG1 +#define P2IV_P2IFG2 P2IV__P2IFG2 +#define P2IV_P2IFG3 P2IV__P2IFG3 +#define P2IV_P2IFG4 P2IV__P2IFG4 +#define P2IV_P2IFG5 P2IV__P2IFG5 +#define P2IV_P2IFG6 P2IV__P2IFG6 +#define P2IV_P2IFG7 P2IV__P2IFG7 +#endif +#ifdef __MSP430_HAS_PORT3_R__ +#define P3IV_NONE P3IV__NONE +#define P3IV_P3IFG0 P3IV__P3IFG0 +#define P3IV_P3IFG1 P3IV__P3IFG1 +#define P3IV_P3IFG2 P3IV__P3IFG2 +#define P3IV_P3IFG3 P3IV__P3IFG3 +#define P3IV_P3IFG4 P3IV__P3IFG4 +#define P3IV_P3IFG5 P3IV__P3IFG5 +#define P3IV_P3IFG6 P3IV__P3IFG6 +#define P3IV_P3IFG7 P3IV__P3IFG7 +#endif +#ifdef __MSP430_HAS_PORT4_R__ +#define P4IV_NONE P4IV__NONE +#define P4IV_P4IFG0 P4IV__P4IFG0 +#define P4IV_P4IFG1 P4IV__P4IFG1 +#define P4IV_P4IFG2 P4IV__P4IFG2 +#define P4IV_P4IFG3 P4IV__P4IFG3 +#define P4IV_P4IFG4 P4IV__P4IFG4 +#define P4IV_P4IFG5 P4IV__P4IFG5 +#define P4IV_P4IFG6 P4IV__P4IFG6 +#define P4IV_P4IFG7 P4IV__P4IFG7 +#endif +#ifdef __MSP430_HAS_PORT5_R__ +#define P5IV_NONE P5IV__NONE +#define P5IV_P5IFG0 P5IV__P5IFG0 +#define P5IV_P5IFG1 P5IV__P5IFG1 +#define P5IV_P5IFG2 P5IV__P5IFG2 +#define P5IV_P5IFG3 P5IV__P5IFG3 +#define P5IV_P5IFG4 P5IV__P5IFG4 +#define P5IV_P5IFG5 P5IV__P5IFG5 +#define P5IV_P5IFG6 P5IV__P5IFG6 +#define P5IV_P5IFG7 P5IV__P5IFG7 +#endif +#ifdef __MSP430_HAS_PORT6_R__ +#define P6IV_NONE P6IV__NONE +#define P6IV_P6IFG0 P6IV__P6IFG0 +#define P6IV_P6IFG1 P6IV__P6IFG1 +#define P6IV_P6IFG2 P6IV__P6IFG2 +#define P6IV_P6IFG3 P6IV__P6IFG3 +#define P6IV_P6IFG4 P6IV__P6IFG4 +#define P6IV_P6IFG5 P6IV__P6IFG5 +#define P6IV_P6IFG6 P6IV__P6IFG6 +#define P6IV_P6IFG7 P6IV__P6IFG7 +#endif +#ifdef __MSP430_HAS_PORT7_R__ +#define P7IV_NONE P7IV__NONE +#define P7IV_P7IFG0 P7IV__P7IFG0 +#define P7IV_P7IFG1 P7IV__P7IFG1 +#define P7IV_P7IFG2 P7IV__P7IFG2 +#define P7IV_P7IFG3 P7IV__P7IFG3 +#define P7IV_P7IFG4 P7IV__P7IFG4 +#define P7IV_P7IFG5 P7IV__P7IFG5 +#define P7IV_P7IFG6 P7IV__P7IFG6 +#define P7IV_P7IFG7 P7IV__P7IFG7 +#endif +#ifdef __MSP430_HAS_PORT8_R__ +#define P8IV_NONE P8IV__NONE +#define P8IV_P8IFG0 P8IV__P8IFG0 +#define P8IV_P8IFG1 P8IV__P8IFG1 +#define P8IV_P8IFG2 P8IV__P8IFG2 +#define P8IV_P8IFG3 P8IV__P8IFG3 +#define P8IV_P8IFG4 P8IV__P8IFG4 +#define P8IV_P8IFG5 P8IV__P8IFG5 +#define P8IV_P8IFG6 P8IV__P8IFG6 +#define P8IV_P8IFG7 P8IV__P8IFG7 +#endif +#endif + +/************************************************************ +* DMA +************************************************************/ + +#ifdef __MSP430_HAS_DMA__ + +#define __MSP430_HAS_DMAX_6__ +#define __MSP430_BASEADDRESS_DMAX_6__ DMA_BASE + +#define DMAIV_NONE DMAIV__NONE +#define DMAIV_DMA0IFG DMAIV__DMA0IFG +#define DMAIV_DMA1IFG DMAIV__DMA1IFG +#define DMAIV_DMA2IFG DMAIV__DMA2IFG +#define DMAIV_DMA3IFG DMAIV__DMA3IFG +#define DMAIV_DMA4IFG DMAIV__DMA4IFG +#define DMAIV_DMA5IFG DMAIV__DMA5IFG + +#define DMASBDB DMASRCBYTE | DMADSTBYTE +#define DMASBDW DMASRCBYTE +#define DMASWDB DMADSTBYTE +#define DMASWDW (0x0000) + +#ifdef DMA0CTL +#define DMA0SAL DMA0SA_L +#define DMA0SAH DMA0SA_H +#define DMA0DAL DMA0DA_L +#define DMA0DAH DMA0DA_H +#endif +#ifdef DMA1CTL +#define DMA1SAL DMA1SA_L +#define DMA1SAH DMA1SA_H +#define DMA1DAL DMA1DA_L +#define DMA1DAH DMA1DA_H +#endif +#ifdef DMA2CTL +#define DMA2SAL DMA2SA_L +#define DMA2SAH DMA2SA_H +#define DMA2DAL DMA2DA_L +#define DMA2DAH DMA2DA_H +#endif + +#endif + +/************************************************************ +* ECOMP0 +************************************************************/ + +#ifdef __MSP430_HAS_ECOMP0__ +#define ECOMP_BASE ECOMP0_BASE + +#ifdef OFS_CP0CTL0 +#define CPCTL0 CP0CTL0 +#define CPCTL0_L CP0CTL0_L +#define CPCTL0_H CP0CTL0_H +#define OFS_CPCTL0 OFS_CP0CTL0 +#define OFS_CPCTL0_L OFS_CP0CTL0 +#define OFS_CPCTL0_H OFS_CP0CTL0+1 +#endif +#ifdef OFS_CP0CTL1 +#define CPCTL1 CP0CTL1 +#define CPCTL1_L CP0CTL1_L +#define CPCTL1_H CP0CTL1_H +#define OFS_CPCTL1 OFS_CP0CTL1 +#define OFS_CPCTL1_L OFS_CP0CTL1 +#define OFS_CPCTL1_H OFS_CP0CTL1+1 +#endif +#ifdef OFS_CP0INT +#define CPINT CP0INT +#define CPINT_L CP0INT_L +#define CPINT_H CP0INT_H +#define OFS_CPINT OFS_CP0INT +#define OFS_CPINT_L OFS_CP0INT +#define OFS_CPINT_H OFS_CP0INT+1 +#endif +#ifdef OFS_CP0IV +// not provided due to possible invalid re-define +//#define CPIV CP0IV +//#define CPIV_L CP0IV_L +//#define CPIV_H CP0IV_H +#define OFS_CPIV OFS_CP0IV +#define OFS_CPIV_L OFS_CP0IV_L +#define OFS_CPIV_H OFS_CP0IV+1 +#endif +#ifdef OFS_CP0DACCTL +#define CPDACCTL CP0DACCTL +#define CPDACCTL_L CP0DACCTL_L +#define CPDACCTL_H CP0DACCTL_H +#define OFS_CPDACCTL OFS_CP0DACCTL +#define OFS_CPDACCTL_L OFS_CP0DACCTL +#define OFS_CPDACCTL_H OFS_CP0DACCTL+1 +#endif +#ifdef OFS_CP0DACDATA +#define CPDACDATA CP0DACDATA +#define CPDACDATA_L CP0DACDATA_L +#define CPDACDATA_H CP0DACDATA_H +#define OFS_CPDACDATA OFS_CP0DACDATA +#define OFS_CPDACDATA_L OFS_CP0DACDATA +#define OFS_CPDACDATA_H OFS_CP0DACDATA+1 +#endif + +#endif + +/************************************************************ +* FRCTL +************************************************************/ + +#ifdef __MSP430_HAS_FRCTL__ + +#define __MSP430_HAS_FRAM__ +#define __MSP430_HAS_GC__ +#define __MSP430_BASEADDRESS_FRAM__ FRCTL_BASE +#define FRAM_BASE FRCTL_BASE + +#define FWPW FRCTLPW +#define FRPW (0x9600) /* FRAM password returned by read */ +#define FXPW (0x3300) /* for use with XOR instruction */ + +#endif + +/************************************************************ +* LCD_C +************************************************************/ + +#ifdef __MSP430_HAS_LCD_C__ + +#define OFS_LCDBM1 OFS_LCDM33_LCDBM1 +#define OFS_LCDBM2 OFS_LCDM34_LCDBM2 +#define OFS_LCDBM3 OFS_LCDM35_LCDBM3 +#define OFS_LCDBM4 OFS_LCDM36_LCDBM4 +#define OFS_LCDBM5 OFS_LCDM37_LCDBM5 +#define OFS_LCDBM6 OFS_LCDM38_LCDBM6 +#define OFS_LCDBM7 OFS_LCDM39_LCDBM7 +#define OFS_LCDBM8 OFS_LCDM40_LCDBM8 +#define OFS_LCDBM9 OFS_LCDM41_LCDBM9 +#define OFS_LCDBM10 OFS_LCDM42_LCDBM10 +#define OFS_LCDBM11 OFS_LCDM43_LCDBM11 +#define OFS_LCDBM12 OFS_LCDM44_LCDBM12 +#define OFS_LCDBM13 OFS_LCDM45_LCDBM13 +#define OFS_LCDBM14 OFS_LCDM46_LCDBM14 +#define OFS_LCDBM15 OFS_LCDM47_LCDBM15 +#define OFS_LCDBM16 OFS_LCDM48_LCDBM16 +#define OFS_LCDBM17 OFS_LCDM49_LCDBM17 +#define OFS_LCDBM18 OFS_LCDM50_LCDBM18 +#define OFS_LCDBM19 OFS_LCDM51_LCDBM19 +#define OFS_LCDBM20 OFS_LCDM52_LCDBM20 + +#endif + +/************************************************************ +* LEA +************************************************************/ + +#ifdef __MSP430_HAS_LEA__ + +#define __MSP430_HAS_LEA_SC__ +#define __MSP430_BASEADDRESS_LEA_SC__ LEA_BASE +#define LEA_SC_BASE LEA_BASE + +#define LEASCCAP LEACAP +#define LEASCCAPL LEACAPL +#define LEASCCAPH LEACAPH +#define LEASCCNF0 LEACNF0 +#define LEASCCNF0L LEACNF0L +#define LEASCCNF0H LEACNF0H +#define LEASCCNF1 LEACNF1 +#define LEASCCNF1L LEACNF1L +#define LEASCCNF1H LEACNF1H +#define LEASCCNF2 LEACNF2 +#define LEASCCNF2L LEACNF2L +#define LEASCCNF2H LEACNF2H +#define LEASCMB LEAMB +#define LEASCMBL LEAMBL +#define LEASCMBH LEAMBH +#define LEASCMT LEAMT +#define LEASCMTL LEAMTL +#define LEASCMTH LEAMTH +#define LEASCCMA LEACMA +#define LEASCCMAL LEACMAL +#define LEASCCMAH LEACMAH +#define LEASCCMCTL LEACMCTL +#define LEASCCMCTLL LEACMCTLL +#define LEASCCMCTLH LEACMCTLH +#define LEASCCMDSTAT LEACMDSTAT +#define LEASCCMDSTATL LEACMDSTATL +#define LEASCCMDSTATH LEACMDSTATH +#define LEASCS1STAT LEAS1STAT +#define LEASCS1STATL LEAS1STATL +#define LEASCS1STATH LEAS1STATH +#define LEASCS0STAT LEAS0STAT +#define LEASCS0STATL LEAS0STATL +#define LEASCS0STATH LEAS0STATH +#define LEASCDSTSTAT LEADSTSTAT +#define LEASCDSTSTATL LEADSTSTATL +#define LEASCDSTSTATH LEADSTSTATH +#define LEASCPMCTL LEAPMCTL +#define LEASCPMCTLL LEAPMCTLL +#define LEASCPMCTLH LEAPMCTLH +#define LEASCPMDST LEAPMDST +#define LEASCPMDSTL LEAPMDSTL +#define LEASCPMDSTH LEAPMDSTH +#define LEASCPMS1 LEAPMS1 +#define LEASCPMS1L LEAPMS1L +#define LEASCPMS1H LEAPMS1H +#define LEASCPMS0 LEAPMS0 +#define LEASCPMS0L LEAPMS0L +#define LEASCPMS0H LEAPMS0H +#define LEASCPMCB LEAPMCB +#define LEASCPMCBL LEAPMCBL +#define LEASCPMCBH LEAPMCBH +#define LEASCIFGSET LEAIFGSET +#define LEASCIFGSETL LEAIFGSETL +#define LEASCIFGSETH LEAIFGSETH +#define LEASCIE LEAIE +#define LEASCIEL LEAIEL +#define LEASCIEH LEAIEH +#define LEASCIFG LEAIFG +#define LEASCIFGL LEAIFGL +#define LEASCIFGH LEAIFGH +#define LEASCIV LEAIV +#define LEASCIVL LEAIVL +#define LEASCIVH LEAIVH + +#define OFS_LEASCCAP OFS_LEACAP +#define OFS_LEASCCAP_L OFS_LEACAP_L +#define OFS_LEASCCAP_H OFS_LEACAP_H +#define OFS_LEASCCNF0 OFS_LEACNF0 +#define OFS_LEASCCNF0_L OFS_LEACNF0_L +#define OFS_LEASCCNF0_H OFS_LEACNF0_H +#define OFS_LEASCCNF1 OFS_LEACNF1 +#define OFS_LEASCCNF1_L OFS_LEACNF1_L +#define OFS_LEASCCNF1_H OFS_LEACNF1_H +#define OFS_LEASCCNF2 OFS_LEACNF2 +#define OFS_LEASCCNF2_L OFS_LEACNF2_L +#define OFS_LEASCCNF2_H OFS_LEACNF2_H +#define OFS_LEASCMB OFS_LEAMB +#define OFS_LEASCMB_L OFS_LEAMB_L +#define OFS_LEASCMB_H OFS_LEAMB_H +#define OFS_LEASCMT OFS_LEAMT +#define OFS_LEASCMT_L OFS_LEAMT_L +#define OFS_LEASCMT_H OFS_LEAMT_H +#define OFS_LEASCCMA OFS_LEACMA +#define OFS_LEASCCMA_L OFS_LEACMA_L +#define OFS_LEASCCMA_H OFS_LEACMA_H +#define OFS_LEASCCMCTL OFS_LEACMCTL +#define OFS_LEASCCMCTL_L OFS_LEACMCTL_L +#define OFS_LEASCCMCTL_H OFS_LEACMCTL_H +#define OFS_LEASCCMDSTAT OFS_LEACMDSTAT +#define OFS_LEASCCMDSTAT_L OFS_LEACMDSTAT_L +#define OFS_LEASCCMDSTAT_H OFS_LEACMDSTAT_H +#define OFS_LEASCS1STAT OFS_LEAS1STAT +#define OFS_LEASCS1STAT_L OFS_LEAS1STAT_L +#define OFS_LEASCS1STAT_H OFS_LEAS1STAT_H +#define OFS_LEASCS0STAT OFS_LEAS0STAT +#define OFS_LEASCS0STAT_L OFS_LEAS0STAT_L +#define OFS_LEASCS0STAT_H OFS_LEAS0STAT_H +#define OFS_LEASCDSTSTAT OFS_LEADSTSTAT +#define OFS_LEASCDSTSTAT_L OFS_LEADSTSTAT_L +#define OFS_LEASCDSTSTAT_H OFS_LEADSTSTAT_H +#define OFS_LEASCPMCTL OFS_LEAPMCTL +#define OFS_LEASCPMCTL_L OFS_LEAPMCTL_L +#define OFS_LEASCPMCTL_H OFS_LEAPMCTL_H +#define OFS_LEASCPMDST OFS_LEAPMDST +#define OFS_LEASCPMDST_L OFS_LEAPMDST_L +#define OFS_LEASCPMDST_H OFS_LEAPMDST_H +#define OFS_LEASCPMS1 OFS_LEAPMS1 +#define OFS_LEASCPMS1_L OFS_LEAPMS1_L +#define OFS_LEASCPMS1_H OFS_LEAPMS1_H +#define OFS_LEASCPMS0 OFS_LEAPMS0 +#define OFS_LEASCPMS0_L OFS_LEAPMS0_L +#define OFS_LEASCPMS0_H OFS_LEAPMS0_H +#define OFS_LEASCPMCB OFS_LEAPMCB +#define OFS_LEASCPMCB_L OFS_LEAPMCB_L +#define OFS_LEASCPMCB_H OFS_LEAPMCB_H +#define OFS_LEASCIFGSET OFS_LEAIFGSET +#define OFS_LEASCIFGSET_L OFS_LEAIFGSET_L +#define OFS_LEASCIFGSET_H OFS_LEAIFGSET_H +#define OFS_LEASCIE OFS_LEAIE +#define OFS_LEASCIE_L OFS_LEAIE_L +#define OFS_LEASCIE_H OFS_LEAIE_H +#define OFS_LEASCIFG OFS_LEAIFG +#define OFS_LEASCIFG_L OFS_LEAIFG_L +#define OFS_LEASCIFG_H OFS_LEAIFG_H +#define OFS_LEASCIV OFS_LEAIV +#define OFS_LEASCIV_L OFS_LEAIV_L +#define OFS_LEASCIV_H OFS_LEAIV_H + +#define LEASCSWRST LEASWRST +#define LEASCFTHOLD LEAFTHOLD +#define LEASCFTHOLD_0 LEAFTHOLD_0 +#define LEASCFTHOLD_1 LEAFTHOLD_1 +#define LEASCLPR LEALPR +#define LEASCLPR_0 LEALPR_0 +#define LEASCLPR_1 LEALPR_1 +#define LEASCILPM LEAILPM +#define LEASCILPM_0 LEAILPM_0 +#define LEASCILPM_1 LEAILPM_1 +#define LEASCILB LEAILB +#define LEASCTIMFLTE LEATIMFLTE +#define LEASCTIMFLT_0 LEATIMFLT_0 +#define LEASCTIMFLTE_1 LEATIMFLTE_1 +#define LEASCCFLT LEACFLT +#define LEASCCFLT_0 LEACFLT_0 +#define LEASCCFLT_1 LEACFLT_1 +#define LEASCMEMFLTE LEAMEMFLTE +#define LEASCMEMFLTE_0 LEAMEMFLTE_0 +#define LEASCMEMFLTE_1 LEAMEMFLTE_1 +#define LEASCDONES LEADONES +#define LEASCFREES LEAFREES +#define LEASCTIMFLTS LEATIMFLTS +#define LEASCCFLTS LEACFLTS +#define LEASCCFLTS_0 LEACFLTS_0 +#define LEASCCFLTS_1 LEACFLTS_1 +#define LEASCMEMFLTS LEAMEMFLTS +#define LEASCMEMFLTS_0 LEAMEMFLTS_0 +#define LEASCMEMFLTS_1 LEAMEMFLTS_1 +#define LEASCTRST LEATRST +#define LEASCTEN LEATEN +#define LEASCTISEL0 LEATISEL0 +#define LEASCTISEL1 LEATISEL1 +#define LEASCTISEL2 LEATISEL2 +#define LEASCTISEL3 LEATISEL3 +#define LEASCTISEL LEATISEL +#define LEASCTISEL_0 LEATISEL_0 +#define LEASCTISEL_1 LEATISEL_1 +#define LEASCTISEL_2 LEATISEL_2 +#define LEASCTISEL_3 LEATISEL_3 +#define LEASCTISEL_4 LEATISEL_4 +#define LEASCTISEL_5 LEATISEL_5 +#define LEASCTISEL_6 LEATISEL_6 +#define LEASCTISEL_7 LEATISEL_7 +#define LEASCTISEL_8 LEATISEL_8 +#define LEASCTISEL_9 LEATISEL_9 +#define LEASCTISEL_10 LEATISEL_10 +#define LEASCTISEL_11 LEATISEL_11 +#define LEASCTISEL_12 LEATISEL_12 +#define LEASCTISEL_13 LEATISEL_13 +#define LEASCTISEL_14 LEATISEL_14 +#define LEASCTISEL_15 LEATISEL_15 + +#define LEASCBUSY LEABUSY +#define LEASCBUSY_0 LEABUSY_0 +#define LEASCBUSY_1 LEABUSY_1 +#define LEASCBUSY__READY LEABUSY__READY +#define LEASCBUSY__BUSY LEABUSY__BUSY +#define LEASCMODE LEAMODE +#define LEASCMODE0 LEAMODE0 +#define LEASCMODE1 LEAMODE1 +#define LEASCMODE2 LEAMODE2 +#define LEASCMODE3 LEAMODE3 +#define LEASCMODE_0 LEAMODE_0 +#define LEASCMODE_1 LEAMODE_1 +#define LEASCMODE_2 LEAMODE_2 +#define LEASCMODE_3 LEAMODE_3 +#define LEASCMODE_4 LEAMODE_4 +#define LEASCMODE_5 LEAMODE_5 +#define LEASCMODE_6 LEAMODE_6 +#define LEASCMODE_7 LEAMODE_7 +#define LEASCMODE__OFF LEAMODE__OFF +#define LEASCMODE__READY LEAMODE__READY +#define LEASCMODE__RUNS LEAMODE__RUNS +#define LEASCMODE__RUNR LEAMODE__RUNR +#define LEASCMODE__RUNA LEAMODE__RUNA +#define LEASCMODE__NOTIFY LEAMODE__NOTIFY +#define LEASCMODE__SLEEP LEAMODE__SLEEP +#define LEASCMODE__RUNL LEAMODE__RUNL +#define LEASCPWST LEAPWST +#define LEASCPWST0 LEAPWST0 +#define LEASCPWST1 LEAPWST1 +#define LEASCPWST2 LEAPWST2 +#define LEASCPWST3 LEAPWST3 +#define LEASCASST LEAASST +#define LEASCASST0 LEAASST0 +#define LEASCASST1 LEAASST1 +#define LEASCASST2 LEAASST2 +#define LEASCASST3 LEAASST3 +#define LEASCDONEC LEADONEC +#define LEASCFREEC LEAFREEC +#define LEASCTIMFLTC LEATIMFLTC +#define LEASCCFLTC LEACFLTC +#define LEASCCFLTC_0 LEACFLTC_0 +#define LEASCCFLTC_1 LEACFLTC_1 +#define LEASCMEMFLTC LEAMEMFLTC +#define LEASCMEMFLTC_0 LEAMEMFLTC_0 +#define LEASCMEMFLTC_1 LEAMEMFLTC_1 +#define LEASCRDSTAT LEARDSTAT +#define LEASCRDSTAT0 LEARDSTAT0 +#define LEASCRDSTAT1 LEARDSTAT1 +#define LEASCRDSTAT2 LEARDSTAT2 +#define LEASCRDSTAT3 LEARDSTAT3 +#define LEASCWRSTAT LEAWRSTAT +#define LEASCWRSTAT0 LEAWRSTAT0 +#define LEASCWRSTAT1 LEAWRSTAT1 +#define LEASCWRSTAT2 LEAWRSTAT2 +#define LEASCWRSTAT3 LEAWRSTAT3 + +#define LEASCSPTR LEASPTR +#define LEASCSPTR0 LEASPTR0 +#define LEASCSPTR1 LEASPTR1 +#define LEASCSPTR2 LEASPTR2 +#define LEASCSPTR3 LEASPTR3 +#define LEASCSPTR4 LEASPTR4 +#define LEASCSPTR5 LEASPTR5 +#define LEASCSPTR6 LEASPTR6 +#define LEASCSPTR7 LEASPTR7 +#define LEASCSPTR8 LEASPTR8 +#define LEASCSPTR9 LEASPTR9 +#define LEASCSPTR10 LEASPTR10 +#define LEASCSPTR11 LEASPTR11 +#define LEASCSPTR12 LEASPTR12 +#define LEASCSPTR13 LEASPTR13 +#define LEASCSPTR14 LEASPTR14 +#define LEASCSPTR15 LEASPTR15 + +#define LEASCMB0 LEAMB0 +#define LEASCMB1 LEAMB1 +#define LEASCMB2 LEAMB2 +#define LEASCMB3 LEAMB3 +#define LEASCMB4 LEAMB4 +#define LEASCMB5 LEAMB5 +#define LEASCMB6 LEAMB6 +#define LEASCMB7 LEAMB7 +#define LEASCMB8 LEAMB8 +#define LEASCMB9 LEAMB9 +#define LEASCMB10 LEAMB10 +#define LEASCMB11 LEAMB11 +#define LEASCMB12 LEAMB12 +#define LEASCMB13 LEAMB13 +#define LEASCMB14 LEAMB14 +#define LEASCMB15 LEAMB15 + +#define LEASCMT0 LEAMT0 +#define LEASCMT1 LEAMT1 +#define LEASCMT2 LEAMT2 +#define LEASCMT3 LEAMT3 +#define LEASCMT4 LEAMT4 +#define LEASCMT5 LEAMT5 +#define LEASCMT6 LEAMT6 +#define LEASCMT7 LEAMT7 +#define LEASCMT8 LEAMT8 +#define LEASCMT9 LEAMT9 +#define LEASCMT10 LEAMT10 +#define LEASCMT11 LEAMT11 +#define LEASCMT12 LEAMT12 +#define LEASCMT13 LEAMT13 +#define LEASCMT14 LEAMT14 +#define LEASCMT15 LEAMT15 + +#define LEASCCMDP LEACMDP +#define LEASCCMDP0 LEACMDP0 +#define LEASCCMDP1 LEACMDP1 +#define LEASCCMDP2 LEACMDP2 +#define LEASCCMDP3 LEACMDP3 +#define LEASCCMDP4 LEACMDP4 +#define LEASCCMDP5 LEACMDP5 +#define LEASCCMDP6 LEACMDP6 +#define LEASCCMDP7 LEACMDP7 +#define LEASCCMDP8 LEACMDP8 +#define LEASCCMDP9 LEACMDP9 +#define LEASCCMDP10 LEACMDP10 +#define LEASCCMDP11 LEACMDP11 +#define LEASCCMDP12 LEACMDP12 +#define LEASCCMDP13 LEACMDP13 +#define LEASCCMDP14 LEACMDP14 +#define LEASCCMDP15 LEACMDP15 +#define LEASCCMDP16 LEACMDP16 +#define LEASCCMDP17 LEACMDP17 +#define LEASCCMDP18 LEACMDP18 +#define LEASCCMDP19 LEACMDP19 +#define LEASCCMDP20 LEACMDP20 +#define LEASCCMDP21 LEACMDP21 +#define LEASCCMDP22 LEACMDP22 +#define LEASCCMDP23 LEACMDP23 +#define LEASCCMDP24 LEACMDP24 +#define LEASCCMDP25 LEACMDP25 +#define LEASCCMDP26 LEACMDP26 +#define LEASCCMDP27 LEACMDP27 +#define LEASCCMDP28 LEACMDP28 +#define LEASCCMDP29 LEACMDP29 +#define LEASCCMDP30 LEACMDP30 +#define LEASCCMDP31 LEACMDP31 + +#define LEASCCMAE LEACMAE +#define LEASCCMAE_0 LEACMAE_0 +#define LEASCCMAE_1 LEACMAE_1 +#define LEASCINC LEAINC +#define LEASCDEC LEADEC +#define LEASCCROFF LEACROFF +#define LEASCCROFF0 LEACROFF0 +#define LEASCCROFF1 LEACROFF1 +#define LEASCCROFF_0 LEACROFF_0 +#define LEASCCROFF_1 LEACROFF_1 +#define LEASCCROFF_2 LEACROFF_2 +#define LEASCCROFF_3 LEACROFF_3 + +#define LEASCCRACTION LEACRACTION +#define LEASCCMAP LEACMAP +#define LEASCCMAP0 LEACMAP0 +#define LEASCCMAP1 LEACMAP1 +#define LEASCCMAP2 LEACMAP2 +#define LEASCCMAP3 LEACMAP3 +#define LEASCCMAP4 LEACMAP4 +#define LEASCCMAP5 LEACMAP5 +#define LEASCCMAP6 LEACMAP6 +#define LEASCCMAP7 LEACMAP7 +#define LEASCCMAP8 LEACMAP8 +#define LEASCCMAP9 LEACMAP9 +#define LEASCCMAP10 LEACMAP10 +#define LEASCCMAP11 LEACMAP11 +#define LEASCCMAP12 LEACMAP12 +#define LEASCCMAP13 LEACMAP13 +#define LEASCCMAP14 LEACMAP14 +#define LEASCCMAP15 LEACMAP15 + +#define LEASCITFLG LEAITFLG +#define LEASCITFLG0 LEAITFLG0 +#define LEASCITFLG1 LEAITFLG1 +#define LEASCITFLG_0 LEAITFLG_0 +#define LEASCITFLG_1 LEAITFLG_1 +#define LEASCITFLG_2 LEAITFLG_2 +#define LEASCITFLG_3 LEAITFLG_3 +#define LEASCCMD LEACMD +#define LEASCCMD0 LEACMD0 +#define LEASCCMD1 LEACMD1 +#define LEASCCMD2 LEACMD2 +#define LEASCCMD3 LEACMD3 +#define LEASCCMD4 LEACMD4 +#define LEASCCMD5 LEACMD5 +#define LEASCCMD6 LEACMD6 +#define LEASCCMD7 LEACMD7 +#define LEASCCMD_0 LEACMD_0 +#define LEASCCMD_2 LEACMD_2 +#define LEASCCMD_4 LEACMD_4 +#define LEASCCMD_6 LEACMD_6 +#define LEASCCMD_8 LEACMD_8 +#define LEASCCMD_10 LEACMD_10 +#define LEASCCMD_12 LEACMD_12 +#define LEASCCMD_13 LEACMD_13 +#define LEASCCMD_15 LEACMD_15 +#define LEASCCMD_16 LEACMD_16 +#define LEASCCMD_17 LEACMD_17 +#define LEASCCMD_18 LEACMD_18 +#define LEASCCMD_19 LEACMD_19 +#define LEASCCMD_21 LEACMD_21 +#define LEASCCMD_22 LEACMD_22 +#define LEASCCMD_23 LEACMD_23 +#define LEASCCMD_24 LEACMD_24 +#define LEASCCMD_25 LEACMD_25 +#define LEASCCMD_26 LEACMD_26 +#define LEASCCMD_27 LEACMD_27 +#define LEASCCMD_28 LEACMD_28 +#define LEASCCMD_29 LEACMD_29 +#define LEASCCMD_30 LEACMD_30 +#define LEASCCMD_31 LEACMD_31 +#define LEASCCMD_32 LEACMD_32 +#define LEASCCMD_33 LEACMD_33 +#define LEASCCMD_34 LEACMD_34 +#define LEASCCMD_36 LEACMD_36 +#define LEASCCMD_39 LEACMD_39 +#define LEASCCMD_41 LEACMD_41 +#define LEASCCMD_43 LEACMD_43 +#define LEASCCMD_45 LEACMD_45 +#define LEASCCMD_47 LEACMD_47 +#define LEASCCMD_48 LEACMD_48 +#define LEASCCMD_50 LEACMD_50 +#define LEASCCMD_52 LEACMD_52 +#define LEASCCMD_53 LEACMD_53 +#define LEASCCMD_54 LEACMD_54 +#define LEASCCMD_55 LEACMD_55 +#define LEASCCMD_56 LEACMD_56 +#define LEASCCMD_58 LEACMD_58 +#define LEASCCMD_59 LEACMD_59 +#define LEASCCMD_64 LEACMD_64 +#define LEASCCMD_65 LEACMD_65 +#define LEASCCMD_66 LEACMD_66 +#define LEASCCMD_67 LEACMD_67 +#define LEASCCMD_68 LEACMD_68 +#define LEASCCMD_69 LEACMD_69 +#define LEASCCMD_70 LEACMD_70 +#define LEASCCMD_71 LEACMD_71 +#define LEASCCMD_73 LEACMD_73 +#define LEASCCMD_75 LEACMD_75 +#define LEASCCMD_76 LEACMD_76 +#define LEASCCMD_77 LEACMD_77 +#define LEASCCMD_78 LEACMD_78 +#define LEASCCMD_79 LEACMD_79 +#define LEASCCMD__SUSPEND LEACMD__SUSPEND +#define LEASCCMD__RESUME LEACMD__RESUME +#define LEASCCMD__FFTCOMPLEXFIXEDSCALING LEACMD__FFTCOMPLEXFIXEDSCALING +#define LEASCCMD__FIR LEACMD__FIR +#define LEASCCMD__POLYNOMIAL LEACMD__POLYNOMIAL +#define LEASCCMD__FFT LEACMD__FFT +#define LEASCCMD__POLYNOMIALLONG LEACMD__POLYNOMIALLONG +#define LEASCCMD__MPYMATRIXROW LEACMD__MPYMATRIXROW +#define LEASCCMD__MPYMATRIX LEACMD__MPYMATRIX +#define LEASCCMD__ADDMATRIX LEACMD__ADDMATRIX +#define LEASCCMD__MAXMATRIX LEACMD__MAXMATRIX +#define LEASCCMD__MINMATRIX LEACMD__MINMATRIX +#define LEASCCMD__IIRBQ1 LEACMD__IIRBQ1 +#define LEASCCMD__MAC LEACMD__MAC +#define LEASCCMD__DEINTERLEAVEEVENEVEN LEACMD__DEINTERLEAVEEVENEVEN +#define LEASCCMD__DEINTERLEAVEEVENODD LEACMD__DEINTERLEAVEEVENODD +#define LEASCCMD__DEINTERLEAVEODDEVEN LEACMD__DEINTERLEAVEODDEVEN +#define LEASCCMD__DEINTERLEAVEODDODD LEACMD__DEINTERLEAVEODDODD +#define LEASCCMD__MACCOMPLEXMATRIX LEACMD__MACCOMPLEXMATRIX +#define LEASCCMD__MACCOMPLEXCONJUGATEMATRIX LEACMD__MACCOMPLEXCONJUGATEMATRIX +#define LEASCCMD__SUBMATRIX LEACMD__SUBMATRIX +#define LEASCCMD__MPYLONGMATRIX LEACMD__MPYLONGMATRIX +#define LEASCCMD__MPYCOMPLEXMATRIX LEACMD__MPYCOMPLEXMATRIX +#define LEASCCMD__ADDLONGMATRIX LEACMD__ADDLONGMATRIX +#define LEASCCMD__MOVELONGLIST LEACMD__MOVELONGLIST +#define LEASCCMD__BITREVERSECOMPLEXEVEN LEACMD__BITREVERSECOMPLEXEVEN +#define LEASCCMD__BITREVERSECOMPLEXODD LEACMD__BITREVERSECOMPLEXODD +#define LEASCCMD__IIRBQ2EXTENDED LEACMD__IIRBQ2EXTENDED +#define LEASCCMD__FFTCOMPLEXLONG LEACMD__FFTCOMPLEXLONG +#define LEASCCMD__FFTLONG LEACMD__FFTLONG +#define LEASCCMD__BITREVERSECOMPLEXLONGEVEN LEACMD__BITREVERSECOMPLEXLONGEVEN +#define LEASCCMD__BITREVERSECOMPLEXLONGODD LEACMD__BITREVERSECOMPLEXLONGODD +#define LEASCCMD__POLYNOMIALSCALAR LEACMD__POLYNOMIALSCALAR +#define LEASCCMD__FFTCOMPLEXAUTOSCALING LEACMD__FFTCOMPLEXAUTOSCALING +#define LEASCCMD__FIRLONG LEACMD__FIRLONG +#define LEASCCMD__MACLONGMATRIX LEACMD__MACLONGMATRIX +#define LEASCCMD__SUBLONGMATRIX LEACMD__SUBLONGMATRIX +#define LEASCCMD__MAXLONGMATRIX LEACMD__MAXLONGMATRIX +#define LEASCCMD__MINLONGMATRIX LEACMD__MINLONGMATRIX +#define LEASCCMD__FIRCOMPLEX LEACMD__FIRCOMPLEX +#define LEASCCMD__MAXUNSIGNEDMATRIX LEACMD__MAXUNSIGNEDMATRIX +#define LEASCCMD__MINUNSIGNEDMATRIX LEACMD__MINUNSIGNEDMATRIX +#define LEASCCMD__MACMATRIX LEACMD__MACMATRIX +#define LEASCCMD__MAX LEACMD__MAX +#define LEASCCMD__MIN LEACMD__MIN +#define LEASCCMD__MAXUNSIGNED LEACMD__MAXUNSIGNED +#define LEASCCMD__MINUNSIGNED LEACMD__MINUNSIGNED +#define LEASCCMD__MAXUNSIGNEDLONGMATRIX LEACMD__MAXUNSIGNEDLONGMATRIX +#define LEASCCMD__MINUNSIGNEDLONGMATRIX LEACMD__MINUNSIGNEDLONGMATRIX +#define LEASCCMD__IIRBQ2 LEACMD__IIRBQ2 +#define LEASCCMD__FIRCOMPLEXLONG LEACMD__FIRCOMPLEXLONG +#define LEASCCMD__DEINTERLEAVELONG LEACMD__DEINTERLEAVELONG +#define LEASCCMD__WINDOW LEACMD__WINDOW +#define LEASCCMD__MAC3 LEACMD__MAC3 +#define LEASCCMD__SCALEDMAC LEACMD__SCALEDMAC +#define LEASCCMD__SCALEDFIR LEACMD__SCALEDFIR + +#define LEASCS1VAL LEAS1VAL +#define LEASCS1VAL0 LEAS1VAL0 +#define LEASCS1VAL1 LEAS1VAL1 +#define LEASCS1VAL2 LEAS1VAL2 +#define LEASCS1VAL3 LEAS1VAL3 +#define LEASCS1VAL4 LEAS1VAL4 +#define LEASCS1VAL5 LEAS1VAL5 +#define LEASCS1VAL6 LEAS1VAL6 +#define LEASCS1VAL7 LEAS1VAL7 +#define LEASCS1VAL8 LEAS1VAL8 +#define LEASCS1VAL9 LEAS1VAL9 +#define LEASCS1VAL10 LEAS1VAL10 +#define LEASCS1VAL11 LEAS1VAL11 +#define LEASCS1VAL12 LEAS1VAL12 +#define LEASCS1VAL13 LEAS1VAL13 +#define LEASCS1VAL14 LEAS1VAL14 +#define LEASCS1VAL15 LEAS1VAL15 +#define LEASCS1VAL16 LEAS1VAL16 +#define LEASCS1VAL17 LEAS1VAL17 +#define LEASCS1VAL18 LEAS1VAL18 +#define LEASCS1VAL19 LEAS1VAL19 +#define LEASCS1VAL20 LEAS1VAL20 +#define LEASCS1VAL21 LEAS1VAL21 +#define LEASCS1VAL22 LEAS1VAL22 +#define LEASCS1VAL23 LEAS1VAL23 +#define LEASCS1VAL24 LEAS1VAL24 +#define LEASCS1VAL25 LEAS1VAL25 +#define LEASCS1VAL26 LEAS1VAL26 +#define LEASCS1VAL27 LEAS1VAL27 +#define LEASCS1VAL28 LEAS1VAL28 +#define LEASCS1VAL29 LEAS1VAL29 +#define LEASCS1VAL30 LEAS1VAL30 +#define LEASCS1VAL31 LEAS1VAL31 + +#define LEASCS0VAL LEAS0VAL +#define LEASCS0VAL0 LEAS0VAL0 +#define LEASCS0VAL1 LEAS0VAL1 +#define LEASCS0VAL2 LEAS0VAL2 +#define LEASCS0VAL3 LEAS0VAL3 +#define LEASCS0VAL4 LEAS0VAL4 +#define LEASCS0VAL5 LEAS0VAL5 +#define LEASCS0VAL6 LEAS0VAL6 +#define LEASCS0VAL7 LEAS0VAL7 +#define LEASCS0VAL8 LEAS0VAL8 +#define LEASCS0VAL9 LEAS0VAL9 +#define LEASCS0VAL10 LEAS0VAL10 +#define LEASCS0VAL11 LEAS0VAL11 +#define LEASCS0VAL12 LEAS0VAL12 +#define LEASCS0VAL13 LEAS0VAL13 +#define LEASCS0VAL14 LEAS0VAL14 +#define LEASCS0VAL15 LEAS0VAL15 +#define LEASCS0VAL16 LEAS0VAL16 +#define LEASCS0VAL17 LEAS0VAL17 +#define LEASCS0VAL18 LEAS0VAL18 +#define LEASCS0VAL19 LEAS0VAL19 +#define LEASCS0VAL20 LEAS0VAL20 +#define LEASCS0VAL21 LEAS0VAL21 +#define LEASCS0VAL22 LEAS0VAL22 +#define LEASCS0VAL23 LEAS0VAL23 +#define LEASCS0VAL24 LEAS0VAL24 +#define LEASCS0VAL25 LEAS0VAL25 +#define LEASCS0VAL26 LEAS0VAL26 +#define LEASCS0VAL27 LEAS0VAL27 +#define LEASCS0VAL28 LEAS0VAL28 +#define LEASCS0VAL29 LEAS0VAL29 +#define LEASCS0VAL30 LEAS0VAL30 +#define LEASCS0VAL31 LEAS0VAL31 + +#define LEASCCMDEN LEACMDEN +#define LEASCCMDEN_0 LEACMDEN_0 +#define LEASCCMDEN_1 LEACMDEN_1 +#define LEASCTRG LEATRG + +#define LEASCCTX LEACTX +#define LEASCCTX0 LEACTX0 +#define LEASCCTX1 LEACTX1 +#define LEASCCTX2 LEACTX2 +#define LEASCCTX3 LEACTX3 +#define LEASCCTX4 LEACTX4 +#define LEASCCTX5 LEACTX5 +#define LEASCCTX6 LEACTX6 +#define LEASCCTX7 LEACTX7 +#define LEASCCTX8 LEACTX8 +#define LEASCCTX9 LEACTX9 +#define LEASCCTX10 LEACTX10 +#define LEASCCTX11 LEACTX11 + +#define LEASCCOVLIS LEACOVLIS +#define LEASCCOVLIS_0 LEACOVLIS_0 +#define LEASCCOVLIS_1 LEACOVLIS_1 +#define LEASCTIS LEATIS +#define LEASCTIS_0 LEATIS_0 +#define LEASCTIS_1 LEATIS_1 +#define LEASCOORIS LEAOORIS +#define LEASCOORIS_0 LEAOORIS_0 +#define LEASCOORIS_1 LEAOORIS_1 +#define LEASCSDIIS LEASDIIS +#define LEASCSDIIS_0 LEASDIIS_0 +#define LEASCSDIIS_1 LEASDIIS_1 +#define LEASCPMCMDIS LEAPMCMDIS +#define LEASCPMCMDIS_0 LEAPMCMDIS_0 +#define LEASCPMCMDIS_1 LEAPMCMDIS_1 + +#define LEASCCOVLIE LEACOVLIE +#define LEASCCOVLIE_0 LEACOVLIE_0 +#define LEASCCOVLIE_1 LEACOVLIE_1 +#define LEASCTIE LEATIE +#define LEASCTIE_0 LEATIE_0 +#define LEASCTIE_1 LEATIE_1 +#define LEASCOORIE LEAOORIE +#define LEASCOORIE_0 LEAOORIE_0 +#define LEASCOORIE_1 LEAOORIE_1 +#define LEASCSDIIE LEASDIIE +#define LEASCSDIIE_0 LEASDIIE_0 +#define LEASCSDIIE_1 LEASDIIE_1 +#define LEASCPMCMDIE LEAPMCMDIE +#define LEASCPMCMDIE_0 LEAPMCMDIE_0 +#define LEASCPMCMDIE_1 LEAPMCMDIE_1 + +#define LEASCCOVLIFG LEACOVLIFG +#define LEASCCOVLIFG_0 LEACOVLIFG_0 +#define LEASCCOVLIFG_1 LEACOVLIFG_1 +#define LEASCTIFG LEATIFG +#define LEASCTIFG_0 LEATIFG_0 +#define LEASCTIFG_1 LEATIFG_1 +#define LEASCOORIFG LEAOORIFG +#define LEASCOORIFG_0 LEAOORIFG_0 +#define LEASCOORIFG_1 LEAOORIFG_1 +#define LEASCSDIIFG LEASDIIFG +#define LEASCSDIIFG_0 LEASDIIFG_0 +#define LEASCSDIIFG_1 LEASDIIFG_1 +#define LEASCPMCMDIFG LEAPMCMDIFG +#define LEASCPMCMDIFG_0 LEAPMCMDIFG_0 +#define LEASCPMCMDIFG_1 LEAPMCMDIFG_1 + +#define LEASCIV0 LEAIV0 +#define LEASCIV1 LEAIV1 +#define LEASCIV2 LEAIV2 +#define LEASCIV3 LEAIV3 +#define LEASCIV4 LEAIV4 +#define LEASCIV5 LEAIV5 +#define LEASCIV6 LEAIV6 +#define LEASCIV7 LEAIV7 +#define LEASCIV_0 LEAIV_0 +#define LEASCIV_2 LEAIV_2 +#define LEASCIV_4 LEAIV_4 +#define LEASCIV_6 LEAIV_6 +#define LEASCIV_8 LEAIV_8 +#define LEASCIV_10 LEAIV_10 +#define LEASCIV__NONE LEAIV__NONE +#define LEASCIV__COVLIFG LEAIV__COVLIFG +#define LEASCIV__TIFG LEAIV__TIFG +#define LEASCIV__OORIFG LEAIV__OORIFG +#define LEASCIV__SDIIFG LEAIV__SDIIFG +#define LEASCIV__PMCMDIFG LEAIV__PMCMDIFG + +#ifdef LEA_VECTOR +#define LEA_SC_VECTOR LEA_VECTOR +#endif + +#endif + +/************************************************************ +* MPY32 +************************************************************/ + +#ifdef __MSP430_HAS_MPY32__ + +#define OP1_32 MPYOP1_32 +#define OP1_32_L MPYOP1_32_L +#define OP2_32 MPYOP2_32 +#define OP2_32_L MPYOP1_32_L + +#define MPY_B MPY_L +#define MPYS_B MPYS_L +#define MAC_B MAC_L +#define MACS_B MACS_L +#define OP2_B OP2_L +#define MPY32L_B MPY32L_L +#define MPY32H_B MPY32H_L +#define MPYS32L_B MPYS32L_L +#define MPYS32H_B MPYS32H_L +#define MAC32L_B MAC32L_L +#define MAC32H_B MAC32H_L +#define MACS32L_B MACS32L_L +#define MACS32H_B MACS32H_L +#define OP2L_B OP2L_L +#define OP2H_B OP2H_L + +#endif + +/************************************************************ +* PMM +************************************************************/ + +#ifdef __MSP430_HAS_PMM__ +#define __MSP430_HAS_PMM_FRAM__ +#endif + +/************************************************************ +* RAMCTL +************************************************************/ + +#ifdef __MSP430_HAS_RAMCTL__ +#define RAM_BASE RAMCTL_BASE +#define __MSP430_BASEADDRESS_RC_FRAM__ RAMCTL_BASE +#define __MSP430_HAS_RC_FRAM__ +#endif + +/************************************************************ +* RTC +************************************************************/ + +#ifdef __MSP430_HAS_RTC__ + +#define RTCIV_NONE RTCIV__NONE +#define RTCIV_RTCIF RTCIV__RTCIFG + +#define RTCIF RTCIFG +#define RTCIF_L RTCIFG_L + +#endif + +/************************************************************ +* RTC_C +************************************************************/ + +#ifdef __MSP430_HAS_RTC_C__ + +#define RTCPWD RTCCTL0_H +#define RTCCTL1 RTCCTL13_L +#define RTCCTL3 RTCCTL13_H + +#define RTC_VECTOR RTC_C_VECTOR + +#define RTC_NONE RTCIV__NONE +#define RTC_RTCOFIFG RTCIV__RTCOFIFG +#define RTC_RTCRDYIFG RTCIV__RTCRDYIFG +#define RTC_RTCTEVIFG RTCIV__RTCTEVIFG +#define RTC_RTCAIFG RTCIV__RTCAIFG +#define RTC_RT0PSIFG RTCIV__RT0PSIFG +#define RTC_RT1PSIFG RTCIV__RT1PSIFG + +#define RTCIV_NONE RTCIV__NONE +#define RTCIV_RTCOFIFG RTCIV__RTCOFIFG +#define RTCIV_RTCRDYIFG RTCIV__RTCRDYIFG +#define RTCIV_RTCTEVIFG RTCIV__RTCTEVIFG +#define RTCIV_RTCIF RTCIV__RTCIFG +#define RTCIV_RTCAIFG RTCIV__RTCAIFG +#define RTCIV_RT0PSIFG RTCIV__RT0PSIFG +#define RTCIV_RT1PSIFG RTCIV__RT1PSIFG + +#define RTCCLKSEL RTCCKSEL +#define RTCCLKSEL_H RTCCKSEL_H + +#define RTCAE (0x0080) + +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L +#define RTCAHOUR RTCAMINHR_H +#define RTCADOW RTCADOWDAY_L +#define RTCADAY RTCADOWDAY_H + +#endif + +/************************************************************ +* SAPH_A +************************************************************/ + +#ifdef __MSP430_HAS_SAPH_A__ + +#define SAPHIIDX SAPH_AIIDX +#define SAPHIIDX_L SAPH_AIIDX_L +#define SAPHIIDX_H SAPH_AIIDX_H +#define SAPHMIS SAPH_AMIS +#define SAPHMIS_L SAPH_AMIS_L +#define SAPHMIS_H SAPH_AMIS_H +#define SAPHRIS SAPH_ARIS +#define SAPHRIS_L SAPH_ARIS_L +#define SAPHRIS_H SAPH_ARIS_H +#define SAPHIMSC SAPH_AIMSC +#define SAPHIMSC_L SAPH_AIMSC_L +#define SAPHIMSC_H SAPH_AIMSC_H +#define SAPHICR SAPH_AICR +#define SAPHICR_L SAPH_AICR_L +#define SAPHICR_H SAPH_AICR_H +#define SAPHISR SAPH_AISR +#define SAPHISR_L SAPH_AISR_L +#define SAPHISR_H SAPH_AISR_H +#define SAPHDESCLO SAPH_ADESCLO +#define SAPHDESCLO_L SAPH_ADESCLO_L +#define SAPHDESCLO_H SAPH_ADESCLO_H +#define SAPHDESCHI SAPH_ADESCHI +#define SAPHDESCHI_L SAPH_ADESCHI_L +#define SAPHDESCHI_H SAPH_ADESCHI_H +#define SAPHKEY SAPH_AKEY +#define SAPHKEY_L SAPH_AKEY_L +#define SAPHKEY_H SAPH_AKEY_H +#define SAPHOCTL0 SAPH_AOCTL0 +#define SAPHOCTL0_L SAPH_AOCTL0_L +#define SAPHOCTL0_H SAPH_AOCTL0_H +#define SAPHOCTL1 SAPH_AOCTL1 +#define SAPHOCTL1_L SAPH_AOCTL1_L +#define SAPHOCTL1_H SAPH_AOCTL1_H +#define SAPHOSEL SAPH_AOSEL +#define SAPHOSEL_L SAPH_AOSEL_L +#define SAPHOSEL_H SAPH_AOSEL_H +#define SAPHCH0PUT SAPH_ACH0PUT +#define SAPHCH0PUT_L SAPH_ACH0PUT_L +#define SAPHCH0PUT_H SAPH_ACH0PUT_H +#define SAPHCH0PDT SAPH_ACH0PDT +#define SAPHCH0PDT_L SAPH_ACH0PDT_L +#define SAPHCH0PDT_H SAPH_ACH0PDT_H +#define SAPHCH0TT SAPH_ACH0TT +#define SAPHCH0TT_L SAPH_ACH0TT_L +#define SAPHCH0TT_H SAPH_ACH0TT_H +#define SAPHCH1PUT SAPH_ACH1PUT +#define SAPHCH1PUT_L SAPH_ACH1PUT_L +#define SAPHCH1PUT_H SAPH_ACH1PUT_H +#define SAPHCH1PDT SAPH_ACH1PDT +#define SAPHCH1PDT_L SAPH_ACH1PDT_L +#define SAPHCH1PDT_H SAPH_ACH1PDT_H +#define SAPHCH1TT SAPH_ACH1TT +#define SAPHCH1TT_L SAPH_ACH1TT_L +#define SAPHCH1TT_H SAPH_ACH1TT_H +#define SAPHMCNF SAPH_AMCNF +#define SAPHMCNF_L SAPH_AMCNF_L +#define SAPHMCNF_H SAPH_AMCNF_H +#define SAPHTACTL SAPH_ATACTL +#define SAPHTACTL_L SAPH_ATACTL_L +#define SAPHTACTL_H SAPH_ATACTL_H +#define SAPHICTL0 SAPH_AICTL0 +#define SAPHICTL0_L SAPH_AICTL0_L +#define SAPHICTL0_H SAPH_AICTL0_H +#define SAPHBCTL SAPH_ABCTL +#define SAPHBCTL_L SAPH_ABCTL_L +#define SAPHBCTL_H SAPH_ABCTL_H +#define SAPHPGC SAPH_APGC +#define SAPHPGC_L SAPH_APGC_L +#define SAPHPGC_H SAPH_APGC_H +#define SAPHPGLPER SAPH_APGLPER +#define SAPHPGLPER_L SAPH_APGLPER_L +#define SAPHPGLPER_H SAPH_APGLPER_H +#define SAPHPGHPER SAPH_APGHPER +#define SAPHPGHPER_L SAPH_APGHPER_L +#define SAPHPGHPER_H SAPH_APGHPER_H +#define SAPHPGCTL SAPH_APGCTL +#define SAPHPGCTL_L SAPH_APGCTL_L +#define SAPHPGCTL_H SAPH_APGCTL_H +#define SAPHPPGTRIG SAPH_APPGTRIG +#define SAPHPPGTRIG_L SAPH_APPGTRIG_L +#define SAPHPPGTRIG_H SAPH_APPGTRIG_H +#define SAPHXPGCTL SAPH_AXPGCTL +#define SAPHXPGCTL_L SAPH_AXPGCTL_L +#define SAPHXPGCTL_H SAPH_AXPGCTL_H +#define SAPHXPGLPER SAPH_AXPGLPER +#define SAPHXPGLPER_L SAPH_AXPGLPER_L +#define SAPHXPGLPER_H SAPH_AXPGLPER_H +#define SAPHXPGHPER SAPH_AXPGHPER +#define SAPHXPGHPER_L SAPH_AXPGHPER_L +#define SAPHXPGHPER_H SAPH_AXPGHPER_H +#define SAPHASCTL0 SAPH_AASCTL0 +#define SAPHASCTL0_L SAPH_AASCTL0_L +#define SAPHASCTL0_H SAPH_AASCTL0_H +#define SAPHASCTL1 SAPH_AASCTL1 +#define SAPHASCTL1_L SAPH_AASCTL1_L +#define SAPHASCTL1_H SAPH_AASCTL1_H +#define SAPHASQTRIG SAPH_AASQTRIG +#define SAPHAPOL SAPH_AAPOL +#define SAPHAPOL_L SAPH_AAPOL_L +#define SAPHAPOL_H SAPH_AAPOL_H +#define SAPHAPLEV SAPH_AAPLEV +#define SAPHAPLEV_L SAPH_AAPLEV_L +#define SAPHAPLEV_H SAPH_AAPLEV_H +#define SAPHAPHIZ SAPH_AAPHIZ +#define SAPHAPHIZ_L SAPH_AAPHIZ_L +#define SAPHAPHIZ_H SAPH_AAPHIZ_H +#define SAPHATM_A SAPH_AATM_A +#define SAPHATM_A_L SAPH_AATM_A_L +#define SAPHATM_A_H SAPH_AATM_A_H +#define SAPHATM_B SAPH_AATM_B +#define SAPHATM_B_L SAPH_AATM_B_L +#define SAPHATM_B_H SAPH_AATM_B_H +#define SAPHATM_C SAPH_AATM_C +#define SAPHATM_C_L SAPH_AATM_C_L +#define SAPHATM_C_H SAPH_AATM_C_H +#define SAPHATM_D SAPH_AATM_D +#define SAPHATM_D_L SAPH_AATM_D_L +#define SAPHATM_D_H SAPH_AATM_D_H +#define SAPHATM_E SAPH_AATM_E +#define SAPHATM_E_L SAPH_AATM_E_L +#define SAPHATM_E_H SAPH_AATM_E_H +#define SAPHATM_F SAPH_AATM_F +#define SAPHATM_F_L SAPH_AATM_F_L +#define SAPHATM_F_H SAPH_AATM_F_H +#define SAPHTBCTL SAPH_ATBCTL +#define SAPHTBCTL_L SAPH_ATBCTL_L +#define SAPHTBCTL_H SAPH_ATBCTL_H +#define SAPHATIMLO SAPH_AATIMLO +#define SAPHATIMLO_L SAPH_AATIMLO_L +#define SAPHATIMLO_H SAPH_AATIMLO_H +#define SAPHATIMHI SAPH_AATIMHI +#define SAPHATIMHI_L SAPH_AATIMHI_L +#define SAPHATIMHI_H SAPH_AATIMHI_H + +#define OFS_SAPHIIDX OFS_SAPH_AIIDX +#define OFS_SAPHIIDX_L OFS_SAPH_AIIDX +#define OFS_SAPHIIDX_H OFS_SAPH_AIIDX+1 +#define OFS_SAPHMIS OFS_SAPH_AMIS +#define OFS_SAPHMIS_L OFS_SAPH_AMIS +#define OFS_SAPHMIS_H OFS_SAPH_AMIS+1 +#define OFS_SAPHRIS OFS_SAPH_ARIS +#define OFS_SAPHRIS_L OFS_SAPH_ARIS +#define OFS_SAPHRIS_H OFS_SAPH_ARIS+1 +#define OFS_SAPHIMSC OFS_SAPH_AIMSC +#define OFS_SAPHIMSC_L OFS_SAPH_AIMSC +#define OFS_SAPHIMSC_H OFS_SAPH_AIMSC+1 +#define OFS_SAPHICR OFS_SAPH_AICR +#define OFS_SAPHICR_L OFS_SAPH_AICR +#define OFS_SAPHICR_H OFS_SAPH_AICR+1 +#define OFS_SAPHISR OFS_SAPH_AISR +#define OFS_SAPHISR_L OFS_SAPH_AISR +#define OFS_SAPHISR_H OFS_SAPH_AISR+1 +#define OFS_SAPHDESCLO OFS_SAPH_ADESCLO +#define OFS_SAPHDESCLO_L OFS_SAPH_ADESCLO +#define OFS_SAPHDESCLO_H OFS_SAPH_ADESCLO+1 +#define OFS_SAPHDESCHI OFS_SAPH_ADESCHI +#define OFS_SAPHDESCHI_L OFS_SAPH_ADESCHI +#define OFS_SAPHDESCHI_H OFS_SAPH_ADESCHI+1 +#define OFS_SAPHKEY OFS_SAPH_AKEY +#define OFS_SAPHKEY_L OFS_SAPH_AKEY +#define OFS_SAPHKEY_H OFS_SAPH_AKEY+1 +#define OFS_SAPHOCTL0 OFS_SAPH_AOCTL0 +#define OFS_SAPHOCTL0_L OFS_SAPH_AOCTL0 +#define OFS_SAPHOCTL0_H OFS_SAPH_AOCTL0+1 +#define OFS_SAPHOCTL1 OFS_SAPH_AOCTL1 +#define OFS_SAPHOCTL1_L OFS_SAPH_AOCTL1 +#define OFS_SAPHOCTL1_H OFS_SAPH_AOCTL1+1 +#define OFS_SAPHOSEL OFS_SAPH_AOSEL +#define OFS_SAPHOSEL_L OFS_SAPH_AOSEL +#define OFS_SAPHOSEL_H OFS_SAPH_AOSEL+1 +#define OFS_SAPHCH0PUT OFS_SAPH_ACH0PUT +#define OFS_SAPHCH0PUT_L OFS_SAPH_ACH0PUT +#define OFS_SAPHCH0PUT_H OFS_SAPH_ACH0PUT+1 +#define OFS_SAPHCH0PDT OFS_SAPH_ACH0PDT +#define OFS_SAPHCH0PDT_L OFS_SAPH_ACH0PDT +#define OFS_SAPHCH0PDT_H OFS_SAPH_ACH0PDT+1 +#define OFS_SAPHCH0TT OFS_SAPH_ACH0TT +#define OFS_SAPHCH0TT_L OFS_SAPH_ACH0TT +#define OFS_SAPHCH0TT_H OFS_SAPH_ACH0TT+1 +#define OFS_SAPHCH1PUT OFS_SAPH_ACH1PUT +#define OFS_SAPHCH1PUT_L OFS_SAPH_ACH1PUT +#define OFS_SAPHCH1PUT_H OFS_SAPH_ACH1PUT+1 +#define OFS_SAPHCH1PDT OFS_SAPH_ACH1PDT +#define OFS_SAPHCH1PDT_L OFS_SAPH_ACH1PDT +#define OFS_SAPHCH1PDT_H OFS_SAPH_ACH1PDT+1 +#define OFS_SAPHCH1TT OFS_SAPH_ACH1TT +#define OFS_SAPHCH1TT_L OFS_SAPH_ACH1TT +#define OFS_SAPHCH1TT_H OFS_SAPH_ACH1TT+1 +#define OFS_SAPHTACTL OFS_SAPH_ATACTL +#define OFS_SAPHTACTL_L OFS_SAPH_ATACTL +#define OFS_SAPHTACTL_H OFS_SAPH_ATACTL+1 +#define OFS_SAPHICTL0 OFS_SAPH_AICTL0 +#define OFS_SAPHICTL0_L OFS_SAPH_AICTL0 +#define OFS_SAPHICTL0_H OFS_SAPH_AICTL0+1 +#define OFS_SAPHBCTL OFS_SAPH_ABCTL +#define OFS_SAPHBCTL_L OFS_SAPH_ABCTL +#define OFS_SAPHBCTL_H OFS_SAPH_ABCTL+1 +#define OFS_SAPHPGC OFS_SAPH_APGC +#define OFS_SAPHPGC_L OFS_SAPH_APGC +#define OFS_SAPHPGC_H OFS_SAPH_APGC+1 +#define OFS_SAPHPGLPER OFS_SAPH_APGLPER +#define OFS_SAPHPGLPER_L OFS_SAPH_APGLPER +#define OFS_SAPHPGLPER_H OFS_SAPH_APGLPER+1 +#define OFS_SAPHPGHPER OFS_SAPH_APGHPER +#define OFS_SAPHPGHPER_L OFS_SAPH_APGHPER +#define OFS_SAPHPGHPER_H OFS_SAPH_APGHPER+1 +#define OFS_SAPHPGCTL OFS_SAPH_APGCTL +#define OFS_SAPHPGCTL_L OFS_SAPH_APGCTL +#define OFS_SAPHPGCTL_H OFS_SAPH_APGCTL+1 +#define OFS_SAPHPPGTRIG OFS_SAPH_APPGTRIG +#define OFS_SAPHPPGTRIG_L OFS_SAPH_APPGTRIG +#define OFS_SAPHPPGTRIG_H OFS_SAPH_APPGTRIG+1 +#define OFS_SAPHXPGCTL OFS_SAPH_AXPGCTL +#define OFS_SAPHXPGCTL_L OFS_SAPH_AXPGCTL +#define OFS_SAPHXPGCTL_H OFS_SAPH_AXPGCTL+1 +#define OFS_SAPHXPGLPER OFS_SAPH_AXPGLPER +#define OFS_SAPHXPGLPER_L OFS_SAPH_AXPGLPER +#define OFS_SAPHXPGLPER_H OFS_SAPH_AXPGLPER+1 +#define OFS_SAPHXPGHPER OFS_SAPH_AXPGHPER +#define OFS_SAPHXPGHPER_L OFS_SAPH_AXPGHPER +#define OFS_SAPHXPGHPER_H OFS_SAPH_AXPGHPER+1 +#define OFS_SAPHASCTL0 OFS_SAPH_AASCTL0 +#define OFS_SAPHASCTL0_L OFS_SAPH_AASCTL0 +#define OFS_SAPHASCTL0_H OFS_SAPH_AASCTL0+1 +#define OFS_SAPHASCTL1 OFS_SAPH_AASCTL1 +#define OFS_SAPHASCTL1_L OFS_SAPH_AASCTL1 +#define OFS_SAPHASCTL1_H OFS_SAPH_AASCTL1+1 +#define OFS_SAPHASQTRIG OFS_SAPH_AASQTRIG +#define OFS_SAPHAPOL OFS_SAPH_AAPOL +#define OFS_SAPHAPOL_L OFS_SAPH_AAPOL +#define OFS_SAPHAPOL_H OFS_SAPH_AAPOL+1 +#define OFS_SAPHAPLEV OFS_SAPH_AAPLEV +#define OFS_SAPHAPLEV_L OFS_SAPH_AAPLEV +#define OFS_SAPHAPLEV_H OFS_SAPH_AAPLEV+1 +#define OFS_SAPHAPHIZ OFS_SAPH_AAPHIZ +#define OFS_SAPHAPHIZ_L OFS_SAPH_AAPHIZ +#define OFS_SAPHAPHIZ_H OFS_SAPH_AAPHIZ+1 +#define OFS_SAPHATM_A OFS_SAPH_AATM_A +#define OFS_SAPHATM_A_L OFS_SAPH_AATM_A +#define OFS_SAPHATM_A_H OFS_SAPH_AATM_A+1 +#define OFS_SAPHATM_B OFS_SAPH_AATM_B +#define OFS_SAPHATM_B_L OFS_SAPH_AATM_B +#define OFS_SAPHATM_B_H OFS_SAPH_AATM_B+1 +#define OFS_SAPHATM_C OFS_SAPH_AATM_C +#define OFS_SAPHATM_C_L OFS_SAPH_AATM_C +#define OFS_SAPHATM_C_H OFS_SAPH_AATM_C+1 +#define OFS_SAPHATM_D OFS_SAPH_AATM_D +#define OFS_SAPHATM_D_L OFS_SAPH_AATM_D +#define OFS_SAPHATM_D_H OFS_SAPH_AATM_D+1 +#define OFS_SAPHATM_E OFS_SAPH_AATM_E +#define OFS_SAPHATM_E_L OFS_SAPH_AATM_E +#define OFS_SAPHATM_E_H OFS_SAPH_AATM_E+1 +#define OFS_SAPHATM_F OFS_SAPH_AATM_F +#define OFS_SAPHATM_F_L OFS_SAPH_AATM_F +#define OFS_SAPHATM_F_H OFS_SAPH_AATM_F+1 +#define OFS_SAPHTBCTL OFS_SAPH_ATBCTL +#define OFS_SAPHTBCTL_L OFS_SAPH_ATBCTL +#define OFS_SAPHTBCTL_H OFS_SAPH_ATBCTL+1 +#define OFS_SAPHATIMLO OFS_SAPH_AATIMLO +#define OFS_SAPHATIMLO_L OFS_SAPH_AATIMLO +#define OFS_SAPHATIMLO_H OFS_SAPH_AATIMLO+1 +#define OFS_SAPHATIMHI OFS_SAPH_AATIMHI +#define OFS_SAPHATIMHI_L OFS_SAPH_AATIMHI +#define OFS_SAPHATIMHI_H OFS_SAPH_AATIMHI+1 + +#define SAPH_VECTOR SAPH_A_VECTOR + +#endif + +/************************************************************ +* SYS +************************************************************/ + +#ifdef __MSP430_HAS_SYS__ + +#define SYSRSTIV_NONE SYSRSTIV__NONE +#define SYSRSTIV_BOR SYSRSTIV__BOR +#define SYSRSTIV_CSPW SYSRSTIV__CSPW +#define SYSRSTIV_DOBOR SYSRSTIV__PMMSWBOR +#define SYSRSTIV_DOPOR SYSRSTIV__PMMSWPOR +#define SYSRSTIV_FLLUL SYSRSTIV__FLLUL +#define SYSRSTIV_FRCTLPW SYSRSTIV__FRCTLPW +#define SYSRSTIV_LPM5WU SYSRSTIV__LPM5WU +#define SYSRSTIV_MPUPW SYSRSTIV__MPUPW +#define SYSRSTIV_MPUSEG1IFG SYSRSTIV__MPUSEG1IFG +#define SYSRSTIV_MPUSEG2IFG SYSRSTIV__MPUSEG2IFG +#define SYSRSTIV_MPUSEG3IFG SYSRSTIV__MPUSEG3IFG +#define SYSRSTIV_MPUSEGIIFG SYSRSTIV__MPUSEGIIFG +#define SYSRSTIV_MPUSEGPIFG SYSRSTIV__MPUSEGPIFG +#define SYSRSTIV_PERF SYSRSTIV__PERF +#define SYSRSTIV_PMMPW SYSRSTIV__PMMPW +#define SYSRSTIV_RSTNMI SYSRSTIV__RSTNMI +#define SYSRSTIV_SECYV SYSRSTIV__SECYV +#define SYSRSTIV_SVSHIFG SYSRSTIV__SVSHIFG +#define SYSRSTIV_UBDIFG SYSRSTIV__UBDIFG +#define SYSRSTIV_WDTKEY SYSRSTIV__WDTPW +#define SYSRSTIV_WDTPW SYSRSTIV__WDTPW +#define SYSRSTIV_WDTTO SYSRSTIV__WDTIFG + +#define SYSSNIV_NONE SYSSNIV__NONE +#define SYSSNIV_ACCTEIFG SYSSNIV__ACCTEIFG +#define SYSSNIV_CBDIFG SYSSNIV__CBDIFG +#define SYSSNIV_JMBINIFG SYSSNIV__JMBINIFG +#define SYSSNIV_JMBOUTIFG SYSSNIV__JMBOUTIFG +#define SYSSNIV_LEASCCMD SYSSNIV__LEACMD +#define SYSSNIV_LEASCTO SYSSNIV__LEATO +#define SYSSNIV_MPUSEG1IFG SYSSNIV__MPUSEG1IFG +#define SYSSNIV_MPUSEG2IFG SYSSNIV__MPUSEG2IFG +#define SYSSNIV_MPUSEG3IFG SYSSNIV__MPUSEG3IFG +#define SYSSNIV_MPUSEGIIFG SYSSNIV__MPUSEGIIFG +#define SYSSNIV_MPUSEGPIFG SYSSNIV__MPUSEGPIFG +#define SYSSNIV_SVSLIFG SYSSNIV__SVSLIFG +#define SYSSNIV_UBDIFG SYSSNIV__UBDIFG +#define SYSSNIV_VMAIFG SYSSNIV__VMAIFG +#define SYSSNIV_WPROT SYSSNIV__WPROT + +#define SYSUNIV_NONE SYSUNIV__NONE +#define SYSUNIV_NMIIFG SYSUNIV__NMIIFG +#define SYSUNIV_OFIFG SYSUNIV__OFIFG + +#ifdef __MSP430_HAS_LEA__ + +#define SYSSNIV__LEASCTO SYSSNIV__LEATO +#define SYSSNIV__LEASCTO_L SYSSNIV__LEATO_L +#define SYSSNIV__LEASCCMD SYSSNIV__LEACMD +#define SYSSNIV__LEASCCMD_L SYSSNIV__LEACMD_L + +#endif + +#endif + +/************************************************************ +* Timer A +************************************************************/ + +#ifdef __MSP430_HAS_TAx__ /* Definition to show that Module is available */ +#define __MSP430_HAS_TxA7__ + +#define OFS_TAxCTL OFS_TA0CTL +#define OFS_TAxCCTL0 OFS_TA0CCTL0 +#define OFS_TAxCCTL1 OFS_TA0CCTL1 +#define OFS_TAxCCTL2 OFS_TA0CCTL2 +#define OFS_TAxCCTL3 OFS_TA0CCTL3 +#define OFS_TAxCCTL4 OFS_TA0CCTL4 +#define OFS_TAxCCTL5 OFS_TA0CCTL5 +#define OFS_TAxCCTL6 OFS_TA0CCTL6 +#define OFS_TAxR OFS_TA0R +#define OFS_TAxCCR0 OFS_TA0CCR0 +#define OFS_TAxCCR1 OFS_TA0CCR1 +#define OFS_TAxCCR2 OFS_TA0CCR2 +#define OFS_TAxCCR3 OFS_TA0CCR3 +#define OFS_TAxCCR4 OFS_TA0CCR4 +#define OFS_TAxCCR5 OFS_TA0CCR5 +#define OFS_TAxCCR6 OFS_TA0CCR6 +#define OFS_TAxIV OFS_TA0IV +#define OFS_TAxEX0 OFS_TA0EX0 + +/* TAxIV Definitions */ +#define TAxIV_NONE (0x0000) /* No Interrupt pending */ +#define TAxIV_TACCR1 (0x0002) /* TAxCCR1_CCIFG */ +#define TAxIV_TACCR2 (0x0004) /* TAxCCR2_CCIFG */ +#define TAxIV_TACCR3 (0x0006) /* TAxCCR3_CCIFG */ +#define TAxIV_TACCR4 (0x0008) /* TAxCCR4_CCIFG */ +#define TAxIV_TACCR5 (0x000A) /* TAxCCR5_CCIFG */ +#define TAxIV_TACCR6 (0x000C) /* TAxCCR6_CCIFG */ +#define TAxIV_TAIFG (0x000E) /* TAxIFG */ + +/* Legacy Defines */ +#define TAxIV_TAxCCR1 (0x0002) /* TAxCCR1_CCIFG */ +#define TAxIV_TAxCCR2 (0x0004) /* TAxCCR2_CCIFG */ +#define TAxIV_TAxCCR3 (0x0006) /* TAxCCR3_CCIFG */ +#define TAxIV_TAxCCR4 (0x0008) /* TAxCCR4_CCIFG */ +#define TAxIV_TAxCCR5 (0x000A) /* TAxCCR5_CCIFG */ +#define TAxIV_TAxCCR6 (0x000C) /* TAxCCR6_CCIFG */ +#define TAxIV_TAxIFG (0x000E) /* TAxIFG */ + +#ifndef MC__CONTINOUS +#define MC__CONTINOUS MC__CONTINUOUS +#endif + +#endif + +#ifdef __MSP430_HAS_TA0__ +#if (__MSP430_HAS_TA0__ == 3) + #define __MSP430_BASEADDRESS_T0A3__ TA0_BASE + #define __MSP430_HAS_T0A3__ +#endif +#define TIMER_A0_BASE TA0_BASE + +#define TA0IV_TA0CCR1 TAIV__TACCR1 +#define TA0IV_TA0CCR2 TAIV__TACCR2 +#define TA0IV_TA0IFG TAIV__TAIFG +#define TA0IV_NONE TAIV__NONE +#define TA0IV_TACCR1 TAIV__TACCR1 +#define TA0IV_TACCR2 TAIV__TACCR2 +#define TA0IV_3 TAIV__TACCR3 +#define TA0IV_4 TAIV__TACCR4 +#define TA0IV_5 TAIV__TACCR5 +#define TA0IV_6 TAIV__TACCR6 +#define TA0IV_TAIFG TAIV__TAIFG +#endif + +#ifdef __MSP430_HAS_TA1__ +#if (__MSP430_HAS_TA1__ == 3) + #define __MSP430_BASEADDRESS_T1A3__ TA1_BASE + #define __MSP430_HAS_T1A3__ +#endif +#define TIMER_A1_BASE TA1_BASE + +#define TA1IV_TA1CCR1 TAIV__TACCR1 +#define TA1IV_TA1CCR2 TAIV__TACCR2 +#define TA1IV_TA1IFG TAIV__TAIFG +#define TA1IV_NONE TAIV__NONE +#define TA1IV_TACCR1 TAIV__TACCR1 +#define TA1IV_TACCR2 TAIV__TACCR2 +#define TA1IV_3 TAIV__TACCR3 +#define TA1IV_4 TAIV__TACCR4 +#define TA1IV_5 TAIV__TACCR5 +#define TA1IV_6 TAIV__TACCR6 +#define TA1IV_TAIFG TAIV__TAIFG +#endif + +#ifdef __MSP430_HAS_TA2__ +#if (__MSP430_HAS_TA2__ == 2) + #define __MSP430_BASEADDRESS_T2A2__ TA2_BASE + #define __MSP430_HAS_T2A2__ +#endif +#define TIMER_A2_BASE TA2_BASE + +#define TA2IV_TA2CCR1 TAIV__TACCR1 +#define TA2IV_TA2IFG TAIV__TAIFG +#define TA2IV_NONE TAIV__NONE +#define TA2IV_TACCR1 TAIV__TACCR1 +#define TA2IV_TACCR2 TAIV__TACCR2 +#define TA2IV_3 TAIV__TACCR3 +#define TA2IV_4 TAIV__TACCR4 +#define TA2IV_5 TAIV__TACCR5 +#define TA2IV_6 TAIV__TACCR6 +#define TA2IV_TAIFG TAIV__TAIFG +#endif + +#ifdef __MSP430_HAS_TA3__ +#if (__MSP430_HAS_TA3__ == 2) + #define __MSP430_BASEADDRESS_T3A2__ TA3_BASE + #define __MSP430_HAS_T3A2__ +#endif +#define TIMER_A3_BASE TA3_BASE + +#define TA3IV_TA3CCR1 TAIV__TACCR1 +#define TA3IV_TA3IFG TAIV__TAIFG +#define TA3IV_NONE TAIV__NONE +#define TA3IV_TACCR1 TAIV__TACCR1 +#define TA3IV_TACCR2 TAIV__TACCR2 +#define TA3IV_3 TAIV__TACCR3 +#define TA3IV_4 TAIV__TACCR4 +#define TA3IV_5 TAIV__TACCR5 +#define TA3IV_6 TAIV__TACCR6 +#define TA3IV_TAIFG TAIV__TAIFG +#endif + +#ifdef __MSP430_HAS_TA4__ +#if (__MSP430_HAS_TA4__ == 3) + #define __MSP430_BASEADDRESS_T4A3__ TA4_BASE + #define __MSP430_HAS_T4A3__ +#endif +#define TIMER_A4_BASE TA4_BASE + +#define TA4IV_TA4CCR1 TAIV__TACCR1 +#define TA4IV_TA4IFG TAIV__TAIFG +#define TA4IV_NONE TAIV__NONE +#define TA4IV_TACCR1 TAIV__TACCR1 +#define TA4IV_TACCR2 TAIV__TACCR2 +#define TA4IV_3 TAIV__TACCR3 +#define TA4IV_4 TAIV__TACCR4 +#define TA4IV_5 TAIV__TACCR5 +#define TA4IV_6 TAIV__TACCR6 +#define TA4IV_TAIFG TAIV__TAIFG +#endif + +/************************************************************ +* Timer B +************************************************************/ + +#ifdef __MSP430_HAS_TBx__ +#define __MSP430_HAS_TxB7__ + +#define OFS_TBxCTL OFS_TB0CTL +#define OFS_TBxCCTL0 OFS_TB0CCTL0 +#define OFS_TBxCCTL1 OFS_TB0CCTL1 +#define OFS_TBxCCTL2 OFS_TB0CCTL2 +#define OFS_TBxCCTL3 OFS_TB0CCTL3 +#define OFS_TBxCCTL4 OFS_TB0CCTL4 +#define OFS_TBxCCTL5 OFS_TB0CCTL5 +#define OFS_TBxCCTL6 OFS_TB0CCTL6 +#define OFS_TBxR OFS_TB0R +#define OFS_TBxCCR0 OFS_TB0CCR0 +#define OFS_TBxCCR1 OFS_TB0CCR1 +#define OFS_TBxCCR2 OFS_TB0CCR2 +#define OFS_TBxCCR3 OFS_TB0CCR3 +#define OFS_TBxCCR4 OFS_TB0CCR4 +#define OFS_TBxCCR5 OFS_TB0CCR5 +#define OFS_TBxCCR6 OFS_TB0CCR6 +#define OFS_TBxIV OFS_TB0IV +#define OFS_TBxEX0 OFS_TB0EX0 + +/* TBxIV Definitions */ +#define TBxIV_NONE (0x0000) /* No Interrupt pending */ +#define TBxIV_TBCCR1 (0x0002) /* TBxCCR1_CCIFG */ +#define TBxIV_TBCCR2 (0x0004) /* TBxCCR2_CCIFG */ +#define TBxIV_TBCCR3 (0x0006) /* TBxCCR3_CCIFG */ +#define TBxIV_TBCCR4 (0x0008) /* TBxCCR4_CCIFG */ +#define TBxIV_TBCCR5 (0x000A) /* TBxCCR5_CCIFG */ +#define TBxIV_TBCCR6 (0x000C) /* TBxCCR6_CCIFG */ +#define TBxIV_TBIFG (0x000E) /* TBxIFG */ + +/* Legacy Defines */ +#define TBxIV_TBxCCR1 (0x0002) /* TBxCCR1_CCIFG */ +#define TBxIV_TBxCCR2 (0x0004) /* TBxCCR2_CCIFG */ +#define TBxIV_TBxCCR3 (0x0006) /* TBxCCR3_CCIFG */ +#define TBxIV_TBxCCR4 (0x0008) /* TBxCCR4_CCIFG */ +#define TBxIV_TBxCCR5 (0x000A) /* TBxCCR5_CCIFG */ +#define TBxIV_TBxCCR6 (0x000C) /* TBxCCR6_CCIFG */ +#define TBxIV_TBxIFG (0x000E) /* TBxIFG */ + +#ifndef MC__CONTINOUS +#define MC__CONTINOUS MC__CONTINUOUS +#endif + +#define SHR0 TBCLGRP0 +#define SHR1 TBCLGRP1 +#define SHR_0 TBCLGRP_0 +#define SHR_1 TBCLGRP_1 +#define SHR_2 TBCLGRP_2 +#define SHR_3 TBCLGRP_3 + +#define SLSHR0 CLLD0 +#define SLSHR1 CLLD1 +#define SLSHR_0 CLLD_0 +#define SLSHR_1 CLLD_1 +#define SLSHR_2 CLLD_2 +#define SLSHR_3 CLLD_3 + +#endif + +#ifdef __MSP430_HAS_TB0__ +#if (__MSP430_HAS_TB0__ == 3) + #define __MSP430_BASEADDRESS_T0B3__ TB0_BASE + #define __MSP430_HAS_T0B3__ +#endif +#if (__MSP430_HAS_TB0__ == 7) + #define __MSP430_BASEADDRESS_T0B7__ TB0_BASE + #define __MSP430_HAS_T0B7__ +#endif +#define TIMER_B0_BASE TB0_BASE +#define TIMERB0_VECTOR TIMER0_B0_VECTOR + +#define TBCTL TB0CTL /* Control Register */ +#define TBCCTL0 TB0CCTL0 /* Capture/Compare Control 0 */ +#define TBCCTL1 TB0CCTL1 /* Capture/Compare Control 1 */ +#define TBCCTL2 TB0CCTL2 /* Capture/Compare Control 2 */ +#define TBCCTL3 TB0CCTL3 /* Capture/Compare Control 3 */ +#define TBCCTL4 TB0CCTL4 /* Capture/Compare Control 4 */ +#define TBCCTL5 TB0CCTL5 /* Capture/Compare Control 5 */ +#define TBCCTL6 TB0CCTL6 /* Capture/Compare Control 6 */ +#define TBR TB0R +#define TBCCR0 TB0CCR0 /* Capture/Compare 0 */ +#define TBCCR1 TB0CCR1 /* Capture/Compare 1 */ +#define TBCCR2 TB0CCR2 /* Capture/Compare 2 */ +#define TBCCR3 TB0CCR3 /* Capture/Compare 3 */ +#define TBCCR4 TB0CCR4 /* Capture/Compare 4 */ +#define TBCCR5 TB0CCR5 /* Capture/Compare 5 */ +#define TBCCR6 TB0CCR6 /* Capture/Compare 6 */ +#define TBEX0 TB0EX0 /* Expansion Register 0 */ + +#define TBSSEL__TACLK TBSSEL__TBCLK + +#define TB0IV_NONE TBIV__NONE +#define TB0IV_TB0CCR1 TBIV__TBCCR1 +#define TB0IV_TB0CCR2 TBIV__TBCCR2 +#define TB0IV_TB0CCR3 TBIV__TBCCR3 +#define TB0IV_TB0CCR4 TBIV__TBCCR4 +#define TB0IV_TB0CCR5 TBIV__TBCCR5 +#define TB0IV_TB0CCR6 TBIV__TBCCR6 +#define TB0IV_TB0IFG TBIV__TBIFG + +#define TB0IV_TBCCR1 TBIV__TBCCR1 +#define TB0IV_TBCCR2 TBIV__TBCCR2 +#define TB0IV_TBCCR3 TBIV__TBCCR3 +#define TB0IV_TBCCR4 TBIV__TBCCR4 +#define TB0IV_TBCCR5 TBIV__TBCCR5 +#define TB0IV_TBCCR6 TBIV__TBCCR6 +#define TB0IV_TBIFG TBIV__TBIFG + +#endif + +#ifdef __MSP430_HAS_TB1__ +#if (__MSP430_HAS_TB1__ == 3) + #define __MSP430_HAS_T1B3__ + #define __MSP430_BASEADDRESS_T1B3__ TB1_BASE +#endif +#define TIMER_B1_BASE TB1_BASE +#define TIMERB1_VECTOR TIMER0_B1_VECTOR + +#define TB1IV_NONE TBIV__NONE +#define TB1IV_TB1CCR1 TBIV__TBCCR1 +#define TB1IV_TB1CCR2 TBIV__TBCCR2 +#define TB1IV_TB1IFG TBIV__TBIFG +#define TB1IV_TBCCR1 TBIV__TBCCR1 +#define TB1IV_TBCCR2 TBIV__TBCCR2 +#define TB1IV_TBIFG TBIV__TBIFG + +#endif + +/************************************************************ +* USCI +************************************************************/ + +#if defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__) + +#define UCADDMASK0 ADDMASK0 +#define UCADDMASK0_L ADDMASK0_L +#define UCADDMASK1 ADDMASK1 +#define UCADDMASK1_L ADDMASK1_L +#define UCADDMASK2 ADDMASK2 +#define UCADDMASK2_L ADDMASK2_L +#define UCADDMASK3 ADDMASK3 +#define UCADDMASK3_L ADDMASK3_L +#define UCADDMASK4 ADDMASK4 +#define UCADDMASK4_L ADDMASK4_L +#define UCADDMASK5 ADDMASK5 +#define UCADDMASK5_L ADDMASK5_L +#define UCADDMASK6 ADDMASK6 +#define UCADDMASK6_L ADDMASK6_L +#define UCADDMASK7 ADDMASK7 +#define UCADDMASK7_L ADDMASK7_L +#define UCADDMASK8 ADDMASK8 +#define UCADDMASK8_H ADDMASK8_H +#define UCADDMASK9 ADDMASK9 +#define UCADDMASK9_H ADDMASK9_H + +#define UCADDR UCADDR_UCIDLE +#define UCIDLE UCADDR_UCIDLE + +#define UCADDRX0 ADDRX0 +#define UCADDRX0_L ADDRX0_L +#define UCADDRX1 ADDRX1 +#define UCADDRX1_L ADDRX1_L +#define UCADDRX2 ADDRX2 +#define UCADDRX2_L ADDRX2_L +#define UCADDRX3 ADDRX3 +#define UCADDRX3_L ADDRX3_L +#define UCADDRX4 ADDRX4 +#define UCADDRX4_L ADDRX4_L +#define UCADDRX5 ADDRX5 +#define UCADDRX5_L ADDRX5_L +#define UCADDRX6 ADDRX6 +#define UCADDRX6_L ADDRX6_L +#define UCADDRX7 ADDRX7 +#define UCADDRX7_L ADDRX7_L +#define UCADDRX8 ADDRX8 +#define UCADDRX8_H ADDRX8_H +#define UCADDRX9 ADDRX9 +#define UCADDRX9_H ADDRX9_H + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +#define UCOA0 I2COA00 +#define UCOA0_L I2COA00_L +#define UCOA1 I2COA01 +#define UCOA1_L I2COA01_L +#define UCOA2 I2COA02 +#define UCOA2_L I2COA02_L +#define UCOA3 I2COA03 +#define UCOA3_L I2COA03_L +#define UCOA4 I2COA04 +#define UCOA4_L I2COA04_L +#define UCOA5 I2COA05 +#define UCOA5_L I2COA05_L +#define UCOA6 I2COA06 +#define UCOA6_L I2COA06_L +#define UCOA7 I2COA07 +#define UCOA7_L I2COA07_L +#define UCOA8 I2COA08 +#define UCOA8_H I2COA08_H +#define UCOA9 I2COA09 +#define UCOA9_H I2COA09_H + +#define UCSA0 I2CSA0 +#define UCSA0_L I2CSA0_L +#define UCSA1 I2CSA1 +#define UCSA1_L I2CSA1_L +#define UCSA2 I2CSA2 +#define UCSA2_L I2CSA2_L +#define UCSA3 I2CSA3 +#define UCSA3_L I2CSA3_L +#define UCSA4 I2CSA4 +#define UCSA4_L I2CSA4_L +#define UCSA5 I2CSA5 +#define UCSA5_L I2CSA5_L +#define UCSA6 I2CSA6 +#define UCSA6_L I2CSA6_L +#define UCSA7 I2CSA7 +#define UCSA7_L I2CSA7_L +#define UCSA8 I2CSA8 +#define UCSA8_H I2CSA8_H +#define UCSA9 I2CSA9 +#define UCSA9_H I2CSA9_H + +#define USCI_NONE UCIV__NONE +#define USCI_I2C_UCALIFG UCIV__UCALIFG +#define USCI_I2C_UCBCNTIFG UCIV__UCBCNTIFG +#define USCI_I2C_UCBIT9IFG UCIV__UCBIT9IFG +#define USCI_I2C_UCCLTOIFG UCIV__UCCLTOIFG +#define USCI_I2C_UCNACKIFG UCIV__UCNACKIFG +#define USCI_I2C_UCRXIFG0 UCIV__UCRXIFG0 +#define USCI_I2C_UCRXIFG1 UCIV__UCRXIFG1 +#define USCI_I2C_UCRXIFG2 UCIV__UCRXIFG2 +#define USCI_I2C_UCRXIFG3 UCIV__UCRXIFG3 +#define USCI_I2C_UCSTPIFG UCIV__UCSTPIFG +#define USCI_I2C_UCSTTIFG UCIV__UCSTTIFG +#define USCI_I2C_UCTXIFG0 UCIV__UCTXIFG0 +#define USCI_I2C_UCTXIFG1 UCIV__UCTXIFG1 +#define USCI_I2C_UCTXIFG2 UCIV__UCTXIFG2 +#define USCI_I2C_UCTXIFG3 UCIV__UCTXIFG3 +#define USCI_SPI_UCRXIFG UCIV__UCRXIFG +#define USCI_SPI_UCTXIFG UCIV__UCTXIFG +#define USCI_UART_UCRXIFG UCIV__UCRXIFG +#define USCI_UART_UCSTTIFG UCIV__UCSTTIFG +#define USCI_UART_UCTXCPTIFG UCIV__UCTXCPTIFG +#define USCI_UART_UCTXIFG UCIV__UCTXIFG + +#endif + +/************************************************************ +* USCI Ax +************************************************************/ + +#ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */ +#define __MSP430_HAS_USCI_Ax__ + +#define UCAxCTL1 UCA0CTLW0_L +#define UCAxCTL0 UCA0CTLW0_H +#define UCAxBR0 UCA0BRW_L +#define UCAxBR1 UCA0BRW_H +#define UCAxIRTCTL UCA0IRCTL_L +#define UCAxIRRCTL UCA0IRCTL_H + +#define OFS_UCAxCTLW0 (0x0000) /* USCI Ax Control Word Register 0 */ +#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0 +#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1 +#define OFS_UCAxCTL0 (0x0001) +#define OFS_UCAxCTL1 (0x0000) +#define OFS_UCAxCTLW1 (0x0002) /* USCI Ax Control Word Register 1 */ +#define OFS_UCAxCTLW1_L OFS_UCAxCTLW1 +#define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1 +#define OFS_UCAxBRW (0x0006) /* USCI Ax Baud Word Rate 0 */ +#define OFS_UCAxBRW_L OFS_UCAxBRW +#define OFS_UCAxBRW_H OFS_UCAxBRW+1 +#define OFS_UCAxBR0 (0x0006) +#define OFS_UCAxBR1 (0x0007) +#define OFS_UCAxMCTLW (0x0008) /* USCI Ax Modulation Control */ +#define OFS_UCAxMCTLW_L OFS_UCAxMCTLW +#define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1 +#define OFS_UCAxSTATW (0x000A) /* USCI Ax Status Register */ +#define OFS_UCAxRXBUF (0x000C) /* USCI Ax Receive Buffer */ +#define OFS_UCAxRXBUF_L OFS_UCAxRXBUF +#define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1 +#define OFS_UCAxTXBUF (0x000E) /* USCI Ax Transmit Buffer */ +#define OFS_UCAxTXBUF_L OFS_UCAxTXBUF +#define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1 +#define OFS_UCAxABCTL (0x0010) /* USCI Ax LIN Control */ +#define OFS_UCAxIRCTL (0x0012) /* USCI Ax IrDA Transmit Control */ +#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL +#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1 +#define OFS_UCAxIRTCTL (0x0012) +#define OFS_UCAxIRRCTL (0x0013) +#define OFS_UCAxIE (0x001A) /* USCI Ax Interrupt Enable Register */ +#define OFS_UCAxIE_L OFS_UCAxIE +#define OFS_UCAxIE_H OFS_UCAxIE+1 +#define OFS_UCAxIFG (0x001C) /* USCI Ax Interrupt Flags Register */ +#define OFS_UCAxIFG_L OFS_UCAxIFG +#define OFS_UCAxIFG_H OFS_UCAxIFG+1 +#define OFS_UCAxIE__UART (0x001A) +#define OFS_UCAxIE__UART_L OFS_UCAxIE__UART +#define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1 +#define OFS_UCAxIFG__UART (0x001C) +#define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART +#define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1 +#define OFS_UCAxIV (0x001E) /* USCI Ax Interrupt Vector Register */ + +#define OFS_UCAxCTLW0__SPI (0x0000) +#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI +#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1 +#define OFS_UCAxCTL0__SPI (0x0001) +#define OFS_UCAxCTL1__SPI (0x0000) +#define OFS_UCAxBRW__SPI (0x0006) +#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI +#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1 +#define OFS_UCAxBR0__SPI (0x0006) +#define OFS_UCAxBR1__SPI (0x0007) +#define OFS_UCAxSTATW__SPI (0x000A) +#define OFS_UCAxRXBUF__SPI (0x000C) +#define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI +#define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1 +#define OFS_UCAxTXBUF__SPI (0x000E) +#define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI +#define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1 +#define OFS_UCAxIE__SPI (0x001A) +#define OFS_UCAxIFG__SPI (0x001C) +#define OFS_UCAxIV__SPI (0x001E) + +#ifdef __MSP430_HAS_EUSCI_A0__ +#define USCI_A0_VECTOR EUSCI_A0_VECTOR + +#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */ +#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */ +#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */ +#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */ +#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */ +#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */ + +#endif + +#ifdef __MSP430_HAS_EUSCI_A1__ +#define USCI_A1_VECTOR EUSCI_A1_VECTOR + +#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */ +#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */ +#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */ +#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */ +#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */ +#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */ + +#endif + +#ifdef __MSP430_HAS_EUSCI_A2__ +#define USCI_A2_VECTOR EUSCI_A2_VECTOR + +#define UCA2CTL1 UCA2CTLW0_L /* USCI A2 Control Register 1 */ +#define UCA2CTL0 UCA2CTLW0_H /* USCI A2 Control Register 0 */ +#define UCA2BR0 UCA2BRW_L /* USCI A2 Baud Rate 0 */ +#define UCA2BR1 UCA2BRW_H /* USCI A2 Baud Rate 1 */ +#define UCA2IRTCTL UCA2IRCTL_L /* USCI A2 IrDA Transmit Control */ +#define UCA2IRRCTL UCA2IRCTL_H /* USCI A2 IrDA Receive Control */ + +#endif + +#ifdef __MSP430_HAS_EUSCI_A3__ +#define USCI_A3_VECTOR EUSCI_A3_VECTOR + +#define UCA3CTL1 UCA3CTLW0_L /* USCI A3 Control Register 1 */ +#define UCA3CTL0 UCA3CTLW0_H /* USCI A3 Control Register 0 */ +#define UCA3BR0 UCA3BRW_L /* USCI A3 Baud Rate 0 */ +#define UCA3BR1 UCA3BRW_H /* USCI A3 Baud Rate 1 */ +#define UCA3IRTCTL UCA3IRCTL_L /* USCI A3 IrDA Transmit Control */ +#define UCA3IRRCTL UCA3IRCTL_H /* USCI A3 IrDA Receive Control */ + +#endif + +#endif + +/************************************************************ +* USCI Bx +************************************************************/ + +#ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */ +#define __MSP430_HAS_USCI_Bx__ + +#define UCBxCTL1 UCB0CTLW0_L +#define UCBxCTL0 UCB0CTLW0_H +#define UCBxBR0 UCB0BRW_L +#define UCBxBR1 UCB0BRW_H +#define UCBxSTAT UCB0STATW_L +#define UCBxBCNT UCB0STATW_H + +#define OFS_UCBxCTLW0__SPI (0x0000) +#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI +#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1 +#define OFS_UCBxCTL0__SPI (0x0001) +#define OFS_UCBxCTL1__SPI (0x0000) +#define OFS_UCBxBRW__SPI (0x0006) +#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI +#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1 +#define OFS_UCBxBR0__SPI (0x0006) +#define OFS_UCBxBR1__SPI (0x0007) +#define OFS_UCBxSTATW__SPI (0x0008) +#define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI +#define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1 +#define OFS_UCBxRXBUF__SPI (0x000C) +#define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI +#define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1 +#define OFS_UCBxTXBUF__SPI (0x000E) +#define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI +#define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1 +#define OFS_UCBxIE__SPI (0x002A) +#define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI +#define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1 +#define OFS_UCBxIFG__SPI (0x002C) +#define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI +#define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1 +#define OFS_UCBxIV__SPI (0x002E) + +#define OFS_UCBxCTLW0 (0x0000) /* USCI Bx Control Word Register 0 */ +#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0 +#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1 +#define OFS_UCBxCTL0 (0x0001) +#define OFS_UCBxCTL1 (0x0000) +#define OFS_UCBxCTLW1 (0x0002) /* USCI Bx Control Word Register 1 */ +#define OFS_UCBxCTLW1_L OFS_UCBxCTLW1 +#define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1 +#define OFS_UCBxBRW (0x0006) /* USCI Bx Baud Word Rate 0 */ +#define OFS_UCBxBRW_L OFS_UCBxBRW +#define OFS_UCBxBRW_H OFS_UCBxBRW+1 +#define OFS_UCBxBR0 (0x0006) +#define OFS_UCBxBR1 (0x0007) +#define OFS_UCBxSTATW (0x0008) /* USCI Bx Status Word Register */ +#define OFS_UCBxSTATW_L OFS_UCBxSTATW +#define OFS_UCBxSTATW_H OFS_UCBxSTATW+1 +#define OFS_UCBxSTATW__I2C (0x0008) +#define OFS_UCBxSTAT__I2C (0x0008) +#define OFS_UCBxBCNT__I2C (0x0009) +#define OFS_UCBxTBCNT (0x000A) /* USCI Bx Byte Counter Threshold Register */ +#define OFS_UCBxTBCNT_L OFS_UCBxTBCNT +#define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1 +#define OFS_UCBxRXBUF (0x000C) /* USCI Bx Receive Buffer */ +#define OFS_UCBxRXBUF_L OFS_UCBxRXBUF +#define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1 +#define OFS_UCBxTXBUF (0x000E) /* USCI Bx Transmit Buffer */ +#define OFS_UCBxTXBUF_L OFS_UCBxTXBUF +#define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1 +#define OFS_UCBxI2COA0 (0x0014) /* USCI Bx I2C Own Address 0 */ +#define OFS_UCBxI2COA0_L OFS_UCBxI2COA0 +#define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1 +#define OFS_UCBxI2COA1 (0x0016) /* USCI Bx I2C Own Address 1 */ +#define OFS_UCBxI2COA1_L OFS_UCBxI2COA1 +#define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1 +#define OFS_UCBxI2COA2 (0x0018) /* USCI Bx I2C Own Address 2 */ +#define OFS_UCBxI2COA2_L OFS_UCBxI2COA2 +#define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1 +#define OFS_UCBxI2COA3 (0x001A) /* USCI Bx I2C Own Address 3 */ +#define OFS_UCBxI2COA3_L OFS_UCBxI2COA3 +#define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1 +#define OFS_UCBxADDRX (0x001C) /* USCI Bx Received Address Register */ +#define OFS_UCBxADDRX_L OFS_UCBxADDRX +#define OFS_UCBxADDRX_H OFS_UCBxADDRX+1 +#define OFS_UCBxADDMASK (0x001E) /* USCI Bx Address Mask Register */ +#define OFS_UCBxADDMASK_L OFS_UCBxADDMASK +#define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1 +#define OFS_UCBxI2CSA (0x0020) /* USCI Bx I2C Slave Address */ +#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA +#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1 +#define OFS_UCBxIE (0x002A) /* USCI Bx Interrupt Enable Register */ +#define OFS_UCBxIE_L OFS_UCBxIE +#define OFS_UCBxIE_H OFS_UCBxIE+1 +#define OFS_UCBxIFG (0x002C) /* USCI Bx Interrupt Flags Register */ +#define OFS_UCBxIFG_L OFS_UCBxIFG +#define OFS_UCBxIFG_H OFS_UCBxIFG+1 +#define OFS_UCBxIE__I2C (0x002A) +#define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C +#define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1 +#define OFS_UCBxIFG__I2C (0x002C) +#define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C +#define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1 +#define OFS_UCBxIV (0x002E) /* USCI Bx Interrupt Vector Register */ + +#ifndef UCASTP_3 +#define UCASTP_3 UCASTP +#endif + +#ifdef __MSP430_HAS_EUSCI_B0__ +#define USCI_B0_VECTOR EUSCI_B0_VECTOR + +#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */ +#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */ +#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */ +#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */ +#define UCB0STAT UCB0STATW_L /* USCI B0 Status Register */ +#define UCB0BCNT UCB0STATW_H /* USCI B0 Byte Counter Register */ + +#endif + +#ifdef __MSP430_HAS_EUSCI_B1__ +#define USCI_B1_VECTOR EUSCI_B1_VECTOR + +#define UCB1CTL1 UCB1CTLW0_L /* USCI B1 Control Register 1 */ +#define UCB1CTL0 UCB1CTLW0_H /* USCI B1 Control Register 0 */ +#define UCB1BR0 UCB1BRW_L /* USCI B1 Baud Rate 0 */ +#define UCB1BR1 UCB1BRW_H /* USCI B1 Baud Rate 1 */ +#define UCB1STAT UCB1STATW_L /* USCI B1 Status Register */ +#define UCB1BCNT UCB1STATW_H /* USCI B1 Byte Counter Register */ + +#endif + +#ifdef __MSP430_HAS_EUSCI_B2__ +#define USCI_B2_VECTOR EUSCI_B2_VECTOR + +#define UCB2CTL1 UCB2CTLW0_L /* USCI B2 Control Register 1 */ +#define UCB2CTL0 UCB2CTLW0_H /* USCI B2 Control Register 0 */ +#define UCB2BR0 UCB2BRW_L /* USCI B2 Baud Rate 0 */ +#define UCB2BR1 UCB2BRW_H /* USCI B2 Baud Rate 1 */ +#define UCB2STAT UCB2STATW_L /* USCI B2 Status Register */ +#define UCB2BCNT UCB2STATW_H /* USCI B2 Byte Counter Register */ + +#endif + +#ifdef __MSP430_HAS_EUSCI_B3__ +#define USCI_B3_VECTOR EUSCI_B3_VECTOR + +#define UCB3CTL1 UCB3CTLW0_L /* USCI B3 Control Register 1 */ +#define UCB3CTL0 UCB3CTLW0_H /* USCI B3 Control Register 0 */ +#define UCB3BR0 UCB3BRW_L /* USCI B3 Baud Rate 0 */ +#define UCB3BR1 UCB3BRW_H /* USCI B3 Baud Rate 1 */ +#define UCB3STAT UCB3STATW_L /* USCI B3 Status Register */ +#define UCB3BCNT UCB3STATW_H /* USCI B3 Byte Counter Register */ + +#endif + +#endif + +/************************************************************ +* WDT +************************************************************/ + +#ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */ + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ + +#define WDTSSEL__VLO WDTSSEL__VLOCLK + +#endif diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430.h b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430.h new file mode 100644 index 0000000000..fb5b610491 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430.h @@ -0,0 +1,1920 @@ +/******************************************************************* +* * +* This file is a generic include file controlled by * +* compiler/assembler IDE generated defines * +* * +*******************************************************************/ + +#ifndef __msp430 +#define __msp430 + + +#if defined (__MSP430C111__) +#include "msp430c111.h" + +#elif defined (__MSP430C1111__) +#include "msp430c1111.h" + +#elif defined (__MSP430C112__) +#include "msp430c112.h" + +#elif defined (__MSP430C1121__) +#include "msp430c1121.h" + +#elif defined (__MSP430C1331__) +#include "msp430c1331.h" + +#elif defined (__MSP430C1351__) +#include "msp430c1351.h" + +#elif defined (__MSP430C311S__) +#include "msp430c311s.h" + +#elif defined (__MSP430C312__) +#include "msp430c312.h" + +#elif defined (__MSP430C313__) +#include "msp430c313.h" + +#elif defined (__MSP430C314__) +#include "msp430c314.h" + +#elif defined (__MSP430C315__) +#include "msp430c315.h" + +#elif defined (__MSP430C323__) +#include "msp430c323.h" + +#elif defined (__MSP430C325__) +#include "msp430c325.h" + +#elif defined (__MSP430C336__) +#include "msp430c336.h" + +#elif defined (__MSP430C337__) +#include "msp430c337.h" + +#elif defined (__MSP430C412__) +#include "msp430c412.h" + +#elif defined (__MSP430C413__) +#include "msp430c413.h" + +#elif defined (__MSP430CG4616__) +#include "msp430cg4616.h" + +#elif defined (__MSP430CG4617__) +#include "msp430cg4617.h" + +#elif defined (__MSP430CG4618__) +#include "msp430cg4618.h" + +#elif defined (__MSP430CG4619__) +#include "msp430cg4619.h" + +#elif defined (__MSP430E112__) +#include "msp430e112.h" + +#elif defined (__MSP430E313__) +#include "msp430e313.h" + +#elif defined (__MSP430E315__) +#include "msp430e315.h" + +#elif defined (__MSP430E325__) +#include "msp430e325.h" + +#elif defined (__MSP430E337__) +#include "msp430e337.h" + +#elif defined (__MSP430F110__) +#include "msp430f110.h" + +#elif defined (__MSP430F1101__) +#include "msp430f1101.h" + +#elif defined (__MSP430F1101A__) +#include "msp430f1101a.h" + +#elif defined (__MSP430F1111__) +#include "msp430f1111.h" + +#elif defined (__MSP430F1111A__) +#include "msp430f1111a.h" + +#elif defined (__MSP430F112__) +#include "msp430f112.h" + +#elif defined (__MSP430F1121__) +#include "msp430f1121.h" + +#elif defined (__MSP430F1121A__) +#include "msp430f1121a.h" + +#elif defined (__MSP430F1122__) +#include "msp430f1122.h" + +#elif defined (__MSP430F1132__) +#include "msp430f1132.h" + +#elif defined (__MSP430F122__) +#include "msp430f122.h" + +#elif defined (__MSP430F1222__) +#include "msp430f1222.h" + +#elif defined (__MSP430F123__) +#include "msp430f123.h" + +#elif defined (__MSP430F1232__) +#include "msp430f1232.h" + +#elif defined (__MSP430F133__) +#include "msp430f133.h" + +#elif defined (__MSP430F135__) +#include "msp430f135.h" + +#elif defined (__MSP430F147__) +#include "msp430f147.h" + +#elif defined (__MSP430F148__) +#include "msp430f148.h" + +#elif defined (__MSP430F149__) +#include "msp430f149.h" + +#elif defined (__MSP430F1471__) +#include "msp430f1471.h" + +#elif defined (__MSP430F1481__) +#include "msp430f1481.h" + +#elif defined (__MSP430F1491__) +#include "msp430f1491.h" + +#elif defined (__MSP430F155__) +#include "msp430f155.h" + +#elif defined (__MSP430F156__) +#include "msp430f156.h" + +#elif defined (__MSP430F157__) +#include "msp430f157.h" + +#elif defined (__MSP430F167__) +#include "msp430f167.h" + +#elif defined (__MSP430F168__) +#include "msp430f168.h" + +#elif defined (__MSP430F169__) +#include "msp430f169.h" + +#elif defined (__MSP430F1610__) +#include "msp430f1610.h" + +#elif defined (__MSP430F1611__) +#include "msp430f1611.h" + +#elif defined (__MSP430F1612__) +#include "msp430f1612.h" + +#elif defined (__MSP430F2001__) +#include "msp430f2001.h" + +#elif defined (__MSP430F2011__) +#include "msp430f2011.h" + +#elif defined (__MSP430F2002__) +#include "msp430f2002.h" + +#elif defined (__MSP430F2012__) +#include "msp430f2012.h" + +#elif defined (__MSP430F2003__) +#include "msp430f2003.h" + +#elif defined (__MSP430F2013__) +#include "msp430f2013.h" + +#elif defined (__MSP430F2101__) +#include "msp430f2101.h" + +#elif defined (__MSP430F2111__) +#include "msp430f2111.h" + +#elif defined (__MSP430F2121__) +#include "msp430f2121.h" + +#elif defined (__MSP430F2131__) +#include "msp430f2131.h" + +#elif defined (__MSP430F2112__) +#include "msp430f2112.h" + +#elif defined (__MSP430F2122__) +#include "msp430f2122.h" + +#elif defined (__MSP430F2132__) +#include "msp430f2132.h" + +#elif defined (__MSP430F2232__) +#include "msp430f2232.h" + +#elif defined (__MSP430F2252__) +#include "msp430f2252.h" + +#elif defined (__MSP430F2272__) +#include "msp430f2272.h" + +#elif defined (__MSP430F2234__) +#include "msp430f2234.h" + +#elif defined (__MSP430F2254__) +#include "msp430f2254.h" + +#elif defined (__MSP430F2274__) +#include "msp430f2274.h" + +#elif defined (__MSP430F2330__) +#include "msp430f2330.h" + +#elif defined (__MSP430F2350__) +#include "msp430f2350.h" + +#elif defined (__MSP430F2370__) +#include "msp430f2370.h" + +#elif defined (__MSP430F233__) +#include "msp430f233.h" + +#elif defined (__MSP430F235__) +#include "msp430f235.h" + +#elif defined (__MSP430F247__) +#include "msp430f247.h" + +#elif defined (__MSP430F248__) +#include "msp430f248.h" + +#elif defined (__MSP430F249__) +#include "msp430f249.h" + +#elif defined (__MSP430F2410__) +#include "msp430f2410.h" + +#elif defined (__MSP430F2471__) +#include "msp430f2471.h" + +#elif defined (__MSP430F2481__) +#include "msp430f2481.h" + +#elif defined (__MSP430F2491__) +#include "msp430f2491.h" + +#elif defined (__MSP430F2416__) +#include "msp430f2416.h" + +#elif defined (__MSP430F2417__) +#include "msp430f2417.h" + +#elif defined (__MSP430F2418__) +#include "msp430f2418.h" + +#elif defined (__MSP430F2419__) +#include "msp430f2419.h" + +#elif defined (__MSP430F2616__) +#include "msp430f2616.h" + +#elif defined (__MSP430F2617__) +#include "msp430f2617.h" + +#elif defined (__MSP430F2618__) +#include "msp430f2618.h" + +#elif defined (__MSP430F2619__) +#include "msp430f2619.h" + +#elif defined (__MSP430F412__) +#include "msp430f412.h" + +#elif defined (__MSP430F413__) +#include "msp430f413.h" + +#elif defined (__MSP430F415__) +#include "msp430f415.h" + +#elif defined (__MSP430F417__) +#include "msp430f417.h" + +#elif defined (__MSP430F4132__) +#include "msp430f4132.h" + +#elif defined (__MSP430F4152__) +#include "msp430f4152.h" + +#elif defined (__MSP430F423__) +#include "msp430f423.h" + +#elif defined (__MSP430F425__) +#include "msp430f425.h" + +#elif defined (__MSP430F427__) +#include "msp430f427.h" + +#elif defined (__MSP430F423A__) +#include "msp430f423a.h" + +#elif defined (__MSP430F425A__) +#include "msp430f425a.h" + +#elif defined (__MSP430F427A__) +#include "msp430f427a.h" + +#elif defined (__MSP430F435__) +#include "msp430f435.h" + +#elif defined (__MSP430F436__) +#include "msp430f436.h" + +#elif defined (__MSP430F437__) +#include "msp430f437.h" + +#elif defined (__MSP430F4351__) +#include "msp430f4351.h" + +#elif defined (__MSP430F4361__) +#include "msp430f4361.h" + +#elif defined (__MSP430F4371__) +#include "msp430f4371.h" + +#elif defined (__MSP430F4481__) +#include "msp430f4481.h" + +#elif defined (__MSP430F4491__) +#include "msp430f4491.h" + +#elif defined (__MSP430F447__) +#include "msp430f447.h" + +#elif defined (__MSP430F448__) +#include "msp430f448.h" + +#elif defined (__MSP430F449__) +#include "msp430f449.h" + +#elif defined (__MSP430FE423__) +#include "msp430fe423.h" + +#elif defined (__MSP430FE425__) +#include "msp430fe425.h" + +#elif defined (__MSP430FE427__) +#include "msp430fe427.h" + +#elif defined (__MSP430FE423A__) +#include "msp430fe423a.h" + +#elif defined (__MSP430FE425A__) +#include "msp430fe425a.h" + +#elif defined (__MSP430FE427A__) +#include "msp430fe427a.h" + +#elif defined (__MSP430FE4232__) +#include "msp430fe4232.h" + +#elif defined (__MSP430FE4242__) +#include "msp430fe4242.h" + +#elif defined (__MSP430FE4252__) +#include "msp430fe4252.h" + +#elif defined (__MSP430FE4272__) +#include "msp430fe4272.h" + +#elif defined (__MSP430F4783__) +#include "msp430f4783.h" + +#elif defined (__MSP430F4793__) +#include "msp430f4793.h" + +#elif defined (__MSP430F4784__) +#include "msp430f4784.h" + +#elif defined (__MSP430F4794__) +#include "msp430f4794.h" + +#elif defined (__MSP430F47126__) +#include "msp430f47126.h" + +#elif defined (__MSP430F47127__) +#include "msp430f47127.h" + +#elif defined (__MSP430F47163__) +#include "msp430f47163.h" + +#elif defined (__MSP430F47173__) +#include "msp430f47173.h" + +#elif defined (__MSP430F47183__) +#include "msp430f47183.h" + +#elif defined (__MSP430F47193__) +#include "msp430f47193.h" + +#elif defined (__MSP430F47166__) +#include "msp430f47166.h" + +#elif defined (__MSP430F47176__) +#include "msp430f47176.h" + +#elif defined (__MSP430F47186__) +#include "msp430f47186.h" + +#elif defined (__MSP430F47196__) +#include "msp430f47196.h" + +#elif defined (__MSP430F47167__) +#include "msp430f47167.h" + +#elif defined (__MSP430F47177__) +#include "msp430f47177.h" + +#elif defined (__MSP430F47187__) +#include "msp430f47187.h" + +#elif defined (__MSP430F47197__) +#include "msp430f47197.h" + +#elif defined (__MSP430F4250__) +#include "msp430f4250.h" + +#elif defined (__MSP430F4260__) +#include "msp430f4260.h" + +#elif defined (__MSP430F4270__) +#include "msp430f4270.h" + +#elif defined (__MSP430FG4250__) +#include "msp430fg4250.h" + +#elif defined (__MSP430FG4260__) +#include "msp430fg4260.h" + +#elif defined (__MSP430FG4270__) +#include "msp430fg4270.h" + +#elif defined (__MSP430FW423__) +#include "msp430fw423.h" + +#elif defined (__MSP430FW425__) +#include "msp430fw425.h" + +#elif defined (__MSP430FW427__) +#include "msp430fw427.h" + +#elif defined (__MSP430FW428__) +#include "msp430fw428.h" + +#elif defined (__MSP430FW429__) +#include "msp430fw429.h" + +#elif defined (__MSP430FG437__) +#include "msp430fg437.h" + +#elif defined (__MSP430FG438__) +#include "msp430fg438.h" + +#elif defined (__MSP430FG439__) +#include "msp430fg439.h" + +#elif defined (__MSP430F438__) +#include "msp430f438.h" + +#elif defined (__MSP430F439__) +#include "msp430f439.h" + +#elif defined (__MSP430F477__) +#include "msp430f477.h" + +#elif defined (__MSP430F478__) +#include "msp430f478.h" + +#elif defined (__MSP430F479__) +#include "msp430f479.h" + +#elif defined (__MSP430FG477__) +#include "msp430fg477.h" + +#elif defined (__MSP430FG478__) +#include "msp430fg478.h" + +#elif defined (__MSP430FG479__) +#include "msp430fg479.h" + +#elif defined (__MSP430F46161__) +#include "msp430f46161.h" + +#elif defined (__MSP430F46171__) +#include "msp430f46171.h" + +#elif defined (__MSP430F46181__) +#include "msp430f46181.h" + +#elif defined (__MSP430F46191__) +#include "msp430f46191.h" + +#elif defined (__MSP430F4616__) +#include "msp430f4616.h" + +#elif defined (__MSP430F4617__) +#include "msp430f4617.h" + +#elif defined (__MSP430F4618__) +#include "msp430f4618.h" + +#elif defined (__MSP430F4619__) +#include "msp430f4619.h" + +#elif defined (__MSP430FG4616__) +#include "msp430fg4616.h" + +#elif defined (__MSP430FG4617__) +#include "msp430fg4617.h" + +#elif defined (__MSP430FG4618__) +#include "msp430fg4618.h" + +#elif defined (__MSP430FG4619__) +#include "msp430fg4619.h" + +#elif defined (__MSP430F5418__) +#include "msp430f5418.h" + +#elif defined (__MSP430F5419__) +#include "msp430f5419.h" + +#elif defined (__MSP430F5435__) +#include "msp430f5435.h" + +#elif defined (__MSP430F5436__) +#include "msp430f5436.h" + +#elif defined (__MSP430F5437__) +#include "msp430f5437.h" + +#elif defined (__MSP430F5438__) +#include "msp430f5438.h" + +#elif defined (__MSP430F5418A__) +#include "msp430f5418a.h" + +#elif defined (__MSP430F5419A__) +#include "msp430f5419a.h" + +#elif defined (__MSP430F5435A__) +#include "msp430f5435a.h" + +#elif defined (__MSP430F5436A__) +#include "msp430f5436a.h" + +#elif defined (__MSP430F5437A__) +#include "msp430f5437a.h" + +#elif defined (__MSP430F5438A__) +#include "msp430f5438a.h" + +#elif defined (__MSP430F5212__) +#include "msp430f5212.h" + +#elif defined (__MSP430F5213__) +#include "msp430f5213.h" + +#elif defined (__MSP430F5214__) +#include "msp430f5214.h" + +#elif defined (__MSP430F5217__) +#include "msp430f5217.h" + +#elif defined (__MSP430F5218__) +#include "msp430f5218.h" + +#elif defined (__MSP430F5219__) +#include "msp430f5219.h" + +#elif defined (__MSP430F5222__) +#include "msp430f5222.h" + +#elif defined (__MSP430F5223__) +#include "msp430f5223.h" + +#elif defined (__MSP430F5224__) +#include "msp430f5224.h" + +#elif defined (__MSP430F5227__) +#include "msp430f5227.h" + +#elif defined (__MSP430F5228__) +#include "msp430f5228.h" + +#elif defined (__MSP430F5229__) +#include "msp430f5229.h" + +#elif defined (__MSP430F5232__) +#include "msp430f5232.h" + +#elif defined (__MSP430F5234__) +#include "msp430f5234.h" + +#elif defined (__MSP430F5237__) +#include "msp430f5237.h" + +#elif defined (__MSP430F5239__) +#include "msp430f5239.h" + +#elif defined (__MSP430F5242__) +#include "msp430f5242.h" + +#elif defined (__MSP430F5244__) +#include "msp430f5244.h" + +#elif defined (__MSP430F5247__) +#include "msp430f5247.h" + +#elif defined (__MSP430F5249__) +#include "msp430f5249.h" + +#elif defined (__MSP430F5304__) +#include "msp430f5304.h" + +#elif defined (__MSP430F5308__) +#include "msp430f5308.h" + +#elif defined (__MSP430F5309__) +#include "msp430f5309.h" + +#elif defined (__MSP430F5310__) +#include "msp430f5310.h" + +#elif defined (__MSP430F5340__) +#include "msp430f5340.h" + +#elif defined (__MSP430F5341__) +#include "msp430f5341.h" + +#elif defined (__MSP430F5342__) +#include "msp430f5342.h" + +#elif defined (__MSP430F5324__) +#include "msp430f5324.h" + +#elif defined (__MSP430F5325__) +#include "msp430f5325.h" + +#elif defined (__MSP430F5326__) +#include "msp430f5326.h" + +#elif defined (__MSP430F5327__) +#include "msp430f5327.h" + +#elif defined (__MSP430F5328__) +#include "msp430f5328.h" + +#elif defined (__MSP430F5329__) +#include "msp430f5329.h" + +#elif defined (__MSP430F5500__) +#include "msp430f5500.h" + +#elif defined (__MSP430F5501__) +#include "msp430f5501.h" + +#elif defined (__MSP430F5502__) +#include "msp430f5502.h" + +#elif defined (__MSP430F5503__) +#include "msp430f5503.h" + +#elif defined (__MSP430F5504__) +#include "msp430f5504.h" + +#elif defined (__MSP430F5505__) +#include "msp430f5505.h" + +#elif defined (__MSP430F5506__) +#include "msp430f5506.h" + +#elif defined (__MSP430F5507__) +#include "msp430f5507.h" + +#elif defined (__MSP430F5508__) +#include "msp430f5508.h" + +#elif defined (__MSP430F5509__) +#include "msp430f5509.h" + +#elif defined (__MSP430F5510__) +#include "msp430f5510.h" + +#elif defined (__MSP430F5513__) +#include "msp430f5513.h" + +#elif defined (__MSP430F5514__) +#include "msp430f5514.h" + +#elif defined (__MSP430F5515__) +#include "msp430f5515.h" + +#elif defined (__MSP430F5517__) +#include "msp430f5517.h" + +#elif defined (__MSP430F5519__) +#include "msp430f5519.h" + +#elif defined (__MSP430F5521__) +#include "msp430f5521.h" + +#elif defined (__MSP430F5522__) +#include "msp430f5522.h" + +#elif defined (__MSP430F5524__) +#include "msp430f5524.h" + +#elif defined (__MSP430F5525__) +#include "msp430f5525.h" + +#elif defined (__MSP430F5526__) +#include "msp430f5526.h" + +#elif defined (__MSP430F5527__) +#include "msp430f5527.h" + +#elif defined (__MSP430F5528__) +#include "msp430f5528.h" + +#elif defined (__MSP430F5529__) +#include "msp430f5529.h" + +#elif defined (__MSP430P112__) +#include "msp430p112.h" + +#elif defined (__MSP430P313__) +#include "msp430p313.h" + +#elif defined (__MSP430P315__) +#include "msp430p315.h" + +#elif defined (__MSP430P315S__) +#include "msp430p315s.h" + +#elif defined (__MSP430P325__) +#include "msp430p325.h" + +#elif defined (__MSP430P337__) +#include "msp430p337.h" + +#elif defined (__CC430F5133__) +#include "cc430f5133.h" + +#elif defined (__CC430F5135__) +#include "cc430f5135.h" + +#elif defined (__CC430F5137__) +#include "cc430f5137.h" + +#elif defined (__CC430F6125__) +#include "cc430f6125.h" + +#elif defined (__CC430F6126__) +#include "cc430f6126.h" + +#elif defined (__CC430F6127__) +#include "cc430f6127.h" + +#elif defined (__CC430F6135__) +#include "cc430f6135.h" + +#elif defined (__CC430F6137__) +#include "cc430f6137.h" + +#elif defined (__CC430F5123__) +#include "cc430f5123.h" + +#elif defined (__CC430F5125__) +#include "cc430f5125.h" + +#elif defined (__CC430F5143__) +#include "cc430f5143.h" + +#elif defined (__CC430F5145__) +#include "cc430f5145.h" + +#elif defined (__CC430F5147__) +#include "cc430f5147.h" + +#elif defined (__CC430F6143__) +#include "cc430f6143.h" + +#elif defined (__CC430F6145__) +#include "cc430f6145.h" + +#elif defined (__CC430F6147__) +#include "cc430f6147.h" + +#elif defined (__MSP430F5333__) +#include "msp430f5333.h" + +#elif defined (__MSP430F5335__) +#include "msp430f5335.h" + +#elif defined (__MSP430F5336__) +#include "msp430f5336.h" + +#elif defined (__MSP430F5338__) +#include "msp430f5338.h" + +#elif defined (__MSP430F5630__) +#include "msp430f5630.h" + +#elif defined (__MSP430F5631__) +#include "msp430f5631.h" + +#elif defined (__MSP430F5632__) +#include "msp430f5632.h" + +#elif defined (__MSP430F5633__) +#include "msp430f5633.h" + +#elif defined (__MSP430F5634__) +#include "msp430f5634.h" + +#elif defined (__MSP430F5635__) +#include "msp430f5635.h" + +#elif defined (__MSP430F5636__) +#include "msp430f5636.h" + +#elif defined (__MSP430F5637__) +#include "msp430f5637.h" + +#elif defined (__MSP430F5638__) +#include "msp430f5638.h" + +#elif defined (__MSP430F6433__) +#include "msp430f6433.h" + +#elif defined (__MSP430F6435__) +#include "msp430f6435.h" + +#elif defined (__MSP430F6436__) +#include "msp430f6436.h" + +#elif defined (__MSP430F6438__) +#include "msp430f6438.h" + +#elif defined (__MSP430F6630__) +#include "msp430f6630.h" + +#elif defined (__MSP430F6631__) +#include "msp430f6631.h" + +#elif defined (__MSP430F6632__) +#include "msp430f6632.h" + +#elif defined (__MSP430F6633__) +#include "msp430f6633.h" + +#elif defined (__MSP430F6634__) +#include "msp430f6634.h" + +#elif defined (__MSP430F6635__) +#include "msp430f6635.h" + +#elif defined (__MSP430F6636__) +#include "msp430f6636.h" + +#elif defined (__MSP430F6637__) +#include "msp430f6637.h" + +#elif defined (__MSP430F6638__) +#include "msp430f6638.h" + +#elif defined (__MSP430F5358__) +#include "msp430f5358.h" + +#elif defined (__MSP430F5359__) +#include "msp430f5359.h" + +#elif defined (__MSP430F5658__) +#include "msp430f5658.h" + +#elif defined (__MSP430F5659__) +#include "msp430f5659.h" + +#elif defined (__MSP430F6458__) +#include "msp430f6458.h" + +#elif defined (__MSP430F6459__) +#include "msp430f6459.h" + +#elif defined (__MSP430F6658__) +#include "msp430f6658.h" + +#elif defined (__MSP430F6659__) +#include "msp430f6659.h" + +#elif defined (__MSP430FG6425__) +#include "msp430fg6425.h" + +#elif defined (__MSP430FG6426__) +#include "msp430fg6426.h" + +#elif defined (__MSP430FG6625__) +#include "msp430fg6625.h" + +#elif defined (__MSP430FG6626__) +#include "msp430fg6626.h" + +#elif defined (__MSP430L092__) +#include "msp430l092.h" + +#elif defined (__MSP430C091__) +#include "msp430c091.h" + +#elif defined (__MSP430C092__) +#include "msp430c092.h" + +#elif defined (__MSP430F5131__) +#include "msp430f5131.h" + +#elif defined (__MSP430F5151__) +#include "msp430f5151.h" + +#elif defined (__MSP430F5171__) +#include "msp430f5171.h" + +#elif defined (__MSP430F5132__) +#include "msp430f5132.h" + +#elif defined (__MSP430F5152__) +#include "msp430f5152.h" + +#elif defined (__MSP430F5172__) +#include "msp430f5172.h" + +#elif defined (__MSP430F6720__) +#include "msp430f6720.h" + +#elif defined (__MSP430F6721__) +#include "msp430f6721.h" + +#elif defined (__MSP430F6723__) +#include "msp430f6723.h" + +#elif defined (__MSP430F6724__) +#include "msp430f6724.h" + +#elif defined (__MSP430F6725__) +#include "msp430f6725.h" + +#elif defined (__MSP430F6726__) +#include "msp430f6726.h" + +#elif defined (__MSP430F6730__) +#include "msp430f6730.h" + +#elif defined (__MSP430F6731__) +#include "msp430f6731.h" + +#elif defined (__MSP430F6733__) +#include "msp430f6733.h" + +#elif defined (__MSP430F6734__) +#include "msp430f6734.h" + +#elif defined (__MSP430F6735__) +#include "msp430f6735.h" + +#elif defined (__MSP430F6736__) +#include "msp430f6736.h" + +#elif defined (__MSP430F67621__) +#include "msp430f67621.h" + +#elif defined (__MSP430F67641__) +#include "msp430f67641.h" + +#elif defined (__MSP430F6720A__) +#include "msp430f6720a.h" + +#elif defined (__MSP430F6721A__) +#include "msp430f6721a.h" + +#elif defined (__MSP430F6723A__) +#include "msp430f6723a.h" + +#elif defined (__MSP430F6724A__) +#include "msp430f6724a.h" + +#elif defined (__MSP430F6725A__) +#include "msp430f6725a.h" + +#elif defined (__MSP430F6726A__) +#include "msp430f6726a.h" + +#elif defined (__MSP430F6730A__) +#include "msp430f6730a.h" + +#elif defined (__MSP430F6731A__) +#include "msp430f6731a.h" + +#elif defined (__MSP430F6733A__) +#include "msp430f6733a.h" + +#elif defined (__MSP430F6734A__) +#include "msp430f6734a.h" + +#elif defined (__MSP430F6735A__) +#include "msp430f6735a.h" + +#elif defined (__MSP430F6736A__) +#include "msp430f6736a.h" + +#elif defined (__MSP430F67621A__) +#include "msp430f67621a.h" + +#elif defined (__MSP430F67641A__) +#include "msp430f67641a.h" + +#elif defined (__MSP430F67451__) +#include "msp430f67451.h" + +#elif defined (__MSP430F67651__) +#include "msp430f67651.h" + +#elif defined (__MSP430F67751__) +#include "msp430f67751.h" + +#elif defined (__MSP430F67461__) +#include "msp430f67461.h" + +#elif defined (__MSP430F67661__) +#include "msp430f67661.h" + +#elif defined (__MSP430F67761__) +#include "msp430f67761.h" + +#elif defined (__MSP430F67471__) +#include "msp430f67471.h" + +#elif defined (__MSP430F67671__) +#include "msp430f67671.h" + +#elif defined (__MSP430F67771__) +#include "msp430f67771.h" + +#elif defined (__MSP430F67481__) +#include "msp430f67481.h" + +#elif defined (__MSP430F67681__) +#include "msp430f67681.h" + +#elif defined (__MSP430F67781__) +#include "msp430f67781.h" + +#elif defined (__MSP430F67491__) +#include "msp430f67491.h" + +#elif defined (__MSP430F67691__) +#include "msp430f67691.h" + +#elif defined (__MSP430F67791__) +#include "msp430f67791.h" + +#elif defined (__MSP430F6745__) +#include "msp430f6745.h" + +#elif defined (__MSP430F6765__) +#include "msp430f6765.h" + +#elif defined (__MSP430F6775__) +#include "msp430f6775.h" + +#elif defined (__MSP430F6746__) +#include "msp430f6746.h" + +#elif defined (__MSP430F6766__) +#include "msp430f6766.h" + +#elif defined (__MSP430F6776__) +#include "msp430f6776.h" + +#elif defined (__MSP430F6747__) +#include "msp430f6747.h" + +#elif defined (__MSP430F6767__) +#include "msp430f6767.h" + +#elif defined (__MSP430F6777__) +#include "msp430f6777.h" + +#elif defined (__MSP430F6748__) +#include "msp430f6748.h" + +#elif defined (__MSP430F6768__) +#include "msp430f6768.h" + +#elif defined (__MSP430F6778__) +#include "msp430f6778.h" + +#elif defined (__MSP430F6749__) +#include "msp430f6749.h" + +#elif defined (__MSP430F6769__) +#include "msp430f6769.h" + +#elif defined (__MSP430F6779__) +#include "msp430f6779.h" + +#elif defined (__MSP430F67451A__) +#include "msp430f67451a.h" + +#elif defined (__MSP430F67651A__) +#include "msp430f67651a.h" + +#elif defined (__MSP430F67751A__) +#include "msp430f67751a.h" + +#elif defined (__MSP430F67461A__) +#include "msp430f67461a.h" + +#elif defined (__MSP430F67661A__) +#include "msp430f67661a.h" + +#elif defined (__MSP430F67761A__) +#include "msp430f67761a.h" + +#elif defined (__MSP430F67471A__) +#include "msp430f67471a.h" + +#elif defined (__MSP430F67671A__) +#include "msp430f67671a.h" + +#elif defined (__MSP430F67771A__) +#include "msp430f67771a.h" + +#elif defined (__MSP430F67481A__) +#include "msp430f67481a.h" + +#elif defined (__MSP430F67681A__) +#include "msp430f67681a.h" + +#elif defined (__MSP430F67781A__) +#include "msp430f67781a.h" + +#elif defined (__MSP430F67491A__) +#include "msp430f67491a.h" + +#elif defined (__MSP430F67691A__) +#include "msp430f67691a.h" + +#elif defined (__MSP430F67791A__) +#include "msp430f67791a.h" + +#elif defined (__MSP430F6745A__) +#include "msp430f6745a.h" + +#elif defined (__MSP430F6765A__) +#include "msp430f6765a.h" + +#elif defined (__MSP430F6775A__) +#include "msp430f6775a.h" + +#elif defined (__MSP430F6746A__) +#include "msp430f6746a.h" + +#elif defined (__MSP430F6766A__) +#include "msp430f6766a.h" + +#elif defined (__MSP430F6776A__) +#include "msp430f6776a.h" + +#elif defined (__MSP430F6747A__) +#include "msp430f6747a.h" + +#elif defined (__MSP430F6767A__) +#include "msp430f6767a.h" + +#elif defined (__MSP430F6777A__) +#include "msp430f6777a.h" + +#elif defined (__MSP430F6748A__) +#include "msp430f6748a.h" + +#elif defined (__MSP430F6768A__) +#include "msp430f6768a.h" + +#elif defined (__MSP430F6778A__) +#include "msp430f6778a.h" + +#elif defined (__MSP430F6749A__) +#include "msp430f6749a.h" + +#elif defined (__MSP430F6769A__) +#include "msp430f6769a.h" + +#elif defined (__MSP430F6779A__) +#include "msp430f6779a.h" + +#elif defined (__MSP430FR5720__) +#include "msp430fr5720.h" + +#elif defined (__MSP430FR5721__) +#include "msp430fr5721.h" + +#elif defined (__MSP430FR5722__) +#include "msp430fr5722.h" + +#elif defined (__MSP430FR5723__) +#include "msp430fr5723.h" + +#elif defined (__MSP430FR5724__) +#include "msp430fr5724.h" + +#elif defined (__MSP430FR5725__) +#include "msp430fr5725.h" + +#elif defined (__MSP430FR5726__) +#include "msp430fr5726.h" + +#elif defined (__MSP430FR5727__) +#include "msp430fr5727.h" + +#elif defined (__MSP430FR5728__) +#include "msp430fr5728.h" + +#elif defined (__MSP430FR5729__) +#include "msp430fr5729.h" + +#elif defined (__MSP430FR5730__) +#include "msp430fr5730.h" + +#elif defined (__MSP430FR5731__) +#include "msp430fr5731.h" + +#elif defined (__MSP430FR5732__) +#include "msp430fr5732.h" + +#elif defined (__MSP430FR5733__) +#include "msp430fr5733.h" + +#elif defined (__MSP430FR5734__) +#include "msp430fr5734.h" + +#elif defined (__MSP430FR5735__) +#include "msp430fr5735.h" + +#elif defined (__MSP430FR5736__) +#include "msp430fr5736.h" + +#elif defined (__MSP430FR5737__) +#include "msp430fr5737.h" + +#elif defined (__MSP430FR5738__) +#include "msp430fr5738.h" + +#elif defined (__MSP430FR5739__) +#include "msp430fr5739.h" + +#elif defined (__MSP430G2211__) +#include "msp430g2211.h" + +#elif defined (__MSP430G2201__) +#include "msp430g2201.h" + +#elif defined (__MSP430G2111__) +#include "msp430g2111.h" + +#elif defined (__MSP430G2101__) +#include "msp430g2101.h" + +#elif defined (__MSP430G2001__) +#include "msp430g2001.h" + +#elif defined (__MSP430G2231__) +#include "msp430g2231.h" + +#elif defined (__MSP430G2221__) +#include "msp430g2221.h" + +#elif defined (__MSP430G2131__) +#include "msp430g2131.h" + +#elif defined (__MSP430G2121__) +#include "msp430g2121.h" + +#elif defined (__MSP430AFE221__) +#include "msp430afe221.h" + +#elif defined (__MSP430AFE231__) +#include "msp430afe231.h" + +#elif defined (__MSP430AFE251__) +#include "msp430afe251.h" + +#elif defined (__MSP430AFE222__) +#include "msp430afe222.h" + +#elif defined (__MSP430AFE232__) +#include "msp430afe232.h" + +#elif defined (__MSP430AFE252__) +#include "msp430afe252.h" + +#elif defined (__MSP430AFE223__) +#include "msp430afe223.h" + +#elif defined (__MSP430AFE233__) +#include "msp430afe233.h" + +#elif defined (__MSP430AFE253__) +#include "msp430afe253.h" + +#elif defined (__MSP430G2102__) +#include "msp430g2102.h" + +#elif defined (__MSP430G2202__) +#include "msp430g2202.h" + +#elif defined (__MSP430G2302__) +#include "msp430g2302.h" + +#elif defined (__MSP430G2402__) +#include "msp430g2402.h" + +#elif defined (__MSP430G2132__) +#include "msp430g2132.h" + +#elif defined (__MSP430G2232__) +#include "msp430g2232.h" + +#elif defined (__MSP430G2332__) +#include "msp430g2332.h" + +#elif defined (__MSP430G2432__) +#include "msp430g2432.h" + +#elif defined (__MSP430G2112__) +#include "msp430g2112.h" + +#elif defined (__MSP430G2212__) +#include "msp430g2212.h" + +#elif defined (__MSP430G2312__) +#include "msp430g2312.h" + +#elif defined (__MSP430G2412__) +#include "msp430g2412.h" + +#elif defined (__MSP430G2152__) +#include "msp430g2152.h" + +#elif defined (__MSP430G2252__) +#include "msp430g2252.h" + +#elif defined (__MSP430G2352__) +#include "msp430g2352.h" + +#elif defined (__MSP430G2452__) +#include "msp430g2452.h" + +#elif defined (__MSP430G2113__) +#include "msp430g2113.h" + +#elif defined (__MSP430G2213__) +#include "msp430g2213.h" + +#elif defined (__MSP430G2313__) +#include "msp430g2313.h" + +#elif defined (__MSP430G2413__) +#include "msp430g2413.h" + +#elif defined (__MSP430G2513__) +#include "msp430g2513.h" + +#elif defined (__MSP430G2153__) +#include "msp430g2153.h" + +#elif defined (__MSP430G2253__) +#include "msp430g2253.h" + +#elif defined (__MSP430G2353__) +#include "msp430g2353.h" + +#elif defined (__MSP430G2453__) +#include "msp430g2453.h" + +#elif defined (__MSP430G2553__) +#include "msp430g2553.h" + +#elif defined (__MSP430G2203__) +#include "msp430g2203.h" + +#elif defined (__MSP430G2303__) +#include "msp430g2303.h" + +#elif defined (__MSP430G2403__) +#include "msp430g2403.h" + +#elif defined (__MSP430G2233__) +#include "msp430g2233.h" + +#elif defined (__MSP430G2333__) +#include "msp430g2333.h" + +#elif defined (__MSP430G2433__) +#include "msp430g2433.h" + +#elif defined (__MSP430G2533__) +#include "msp430g2533.h" + +#elif defined (__MSP430TCH5E__) +#include "msp430tch5e.h" + +#elif defined (__MSP430G2444__) +#include "msp430g2444.h" + +#elif defined (__MSP430G2544__) +#include "msp430g2544.h" + +#elif defined (__MSP430G2744__) +#include "msp430g2744.h" + +#elif defined (__MSP430G2755__) +#include "msp430g2755.h" + +#elif defined (__MSP430G2855__) +#include "msp430g2855.h" + +#elif defined (__MSP430G2955__) +#include "msp430g2955.h" + +#elif defined (__MSP430G2230__) +#include "msp430g2230.h" + +#elif defined (__MSP430G2210__) +#include "msp430g2210.h" + +#elif defined (__MSP430BT5190__) +#include "msp430bt5190.h" + +#elif defined (__MSP430FR5857__) +#include "msp430fr5857.h" + +#elif defined (__MSP430FR5858__) +#include "msp430fr5858.h" + +#elif defined (__MSP430FR5859__) +#include "msp430fr5859.h" + +#elif defined (__MSP430FR5847__) +#include "msp430fr5847.h" + +#elif defined (__MSP430FR58471__) +#include "msp430fr58471.h" + +#elif defined (__MSP430FR5848__) +#include "msp430fr5848.h" + +#elif defined (__MSP430FR5849__) +#include "msp430fr5849.h" + +#elif defined (__MSP430FR5867__) +#include "msp430fr5867.h" + +#elif defined (__MSP430FR58671__) +#include "msp430fr58671.h" + +#elif defined (__MSP430FR5868__) +#include "msp430fr5868.h" + +#elif defined (__MSP430FR5869__) +#include "msp430fr5869.h" + +#elif defined (__MSP430FR5957__) +#include "msp430fr5957.h" + +#elif defined (__MSP430FR5958__) +#include "msp430fr5958.h" + +#elif defined (__MSP430FR5959__) +#include "msp430fr5959.h" + +#elif defined (__MSP430FR5947__) +#include "msp430fr5947.h" + +#elif defined (__MSP430FR59471__) +#include "msp430fr59471.h" + +#elif defined (__MSP430FR5948__) +#include "msp430fr5948.h" + +#elif defined (__MSP430FR5949__) +#include "msp430fr5949.h" + +#elif defined (__MSP430FR5967__) +#include "msp430fr5967.h" + +#elif defined (__MSP430FR5968__) +#include "msp430fr5968.h" + +#elif defined (__MSP430FR5969__) +#include "msp430fr5969.h" + +#elif defined (__MSP430FR59691__) +#include "msp430fr59691.h" + +#elif defined (__MSP430FR5962__) +#include "msp430fr5962.h" + +#elif defined (__MSP430FR5964__) +#include "msp430fr5964.h" + +#elif defined (__MSP430FR5992__) +#include "msp430fr5992.h" + +#elif defined (__MSP430FR5994__) +#include "msp430fr5994.h" + +#elif defined (__MSP430FR59941__) +#include "msp430fr59941.h" + +#elif defined (__MSP430i2020__) +#include "msp430i2020.h" + +#elif defined (__MSP430i2021__) +#include "msp430i2021.h" + +#elif defined (__MSP430i2030__) +#include "msp430i2030.h" + +#elif defined (__MSP430i2031__) +#include "msp430i2031.h" + +#elif defined (__MSP430i2040__) +#include "msp430i2040.h" + +#elif defined (__MSP430i2041__) +#include "msp430i2041.h" + +#elif defined (__RF430FRL152H__) +#include "rf430frl152h.h" + +#elif defined (__RF430FRL153H__) +#include "rf430frl153h.h" + +#elif defined (__RF430FRL154H__) +#include "rf430frl154h.h" + +#elif defined (__RF430FRL152H_ROM__) +#include "rf430frl152h_rom.h" + +#elif defined (__RF430FRL153H_ROM__) +#include "rf430frl153h_rom.h" + +#elif defined (__RF430FRL154H_ROM__) +#include "rf430frl154h_rom.h" + +#elif defined (__RF430F5175__) +#include "rf430f5175.h" + +#elif defined (__RF430F5155__) +#include "rf430f5155.h" + +#elif defined (__RF430F5144__) +#include "rf430f5144.h" + +#elif defined (__MSP430FR69271__) +#include "msp430fr69271.h" + +#elif defined (__MSP430FR68791__) +#include "msp430fr68791.h" + +#elif defined (__MSP430FR69791__) +#include "msp430fr69791.h" + +#elif defined (__MSP430FR6927__) +#include "msp430fr6927.h" + +#elif defined (__MSP430FR6928__) +#include "msp430fr6928.h" + +#elif defined (__MSP430FR6877__) +#include "msp430fr6877.h" + +#elif defined (__MSP430FR6977__) +#include "msp430fr6977.h" + +#elif defined (__MSP430FR6879__) +#include "msp430fr6879.h" + +#elif defined (__MSP430FR6979__) +#include "msp430fr6979.h" + +#elif defined (__MSP430FR58891__) +#include "msp430fr58891.h" + +#elif defined (__MSP430FR68891__) +#include "msp430fr68891.h" + +#elif defined (__MSP430FR59891__) +#include "msp430fr59891.h" + +#elif defined (__MSP430FR69891__) +#include "msp430fr69891.h" + +#elif defined (__MSP430FR5887__) +#include "msp430fr5887.h" + +#elif defined (__MSP430FR5888__) +#include "msp430fr5888.h" + +#elif defined (__MSP430FR5889__) +#include "msp430fr5889.h" + +#elif defined (__MSP430FR6887__) +#include "msp430fr6887.h" + +#elif defined (__MSP430FR6888__) +#include "msp430fr6888.h" + +#elif defined (__MSP430FR6889__) +#include "msp430fr6889.h" + +#elif defined (__MSP430FR5986__) +#include "msp430fr5986.h" + +#elif defined (__MSP430FR5987__) +#include "msp430fr5987.h" + +#elif defined (__MSP430FR5988__) +#include "msp430fr5988.h" + +#elif defined (__MSP430FR5989__) +#include "msp430fr5989.h" + +#elif defined (__MSP430FR6987__) +#include "msp430fr6987.h" + +#elif defined (__MSP430FR6988__) +#include "msp430fr6988.h" + +#elif defined (__MSP430FR6989__) +#include "msp430fr6989.h" + +#elif defined (__MSP430FR5922__) +#include "msp430fr5922.h" + +#elif defined (__MSP430FR5870__) +#include "msp430fr5870.h" + +#elif defined (__MSP430FR5970__) +#include "msp430fr5970.h" + +#elif defined (__MSP430FR5872__) +#include "msp430fr5872.h" + +#elif defined (__MSP430FR5972__) +#include "msp430fr5972.h" + +#elif defined (__MSP430FR6820__) +#include "msp430fr6820.h" + +#elif defined (__MSP430FR6920__) +#include "msp430fr6920.h" + +#elif defined (__MSP430FR6822__) +#include "msp430fr6822.h" + +#elif defined (__MSP430FR6922__) +#include "msp430fr6922.h" + +#elif defined (__MSP430FR6870__) +#include "msp430fr6870.h" + +#elif defined (__MSP430FR6970__) +#include "msp430fr6970.h" + +#elif defined (__MSP430FR6872__) +#include "msp430fr6872.h" + +#elif defined (__MSP430FR6972__) +#include "msp430fr6972.h" + +#elif defined (__MSP430FR59221__) +#include "msp430fr59221.h" + +#elif defined (__MSP430FR58721__) +#include "msp430fr58721.h" + +#elif defined (__MSP430FR59721__) +#include "msp430fr59721.h" + +#elif defined (__MSP430FR68221__) +#include "msp430fr68221.h" + +#elif defined (__MSP430FR69221__) +#include "msp430fr69221.h" + +#elif defined (__MSP430FR68721__) +#include "msp430fr68721.h" + +#elif defined (__MSP430FR69721__) +#include "msp430fr69721.h" + +#elif defined (__MSP430SL5438A__) +#include "msp430sl5438a.h" + +#elif defined (__MSP430FR4131__) +#include "msp430fr4131.h" + +#elif defined (__MSP430FR4132__) +#include "msp430fr4132.h" + +#elif defined (__MSP430FR4133__) +#include "msp430fr4133.h" + +#elif defined (__MSP430FR2032__) +#include "msp430fr2032.h" + +#elif defined (__MSP430FR2033__) +#include "msp430fr2033.h" + +#elif defined (__MSP430FR2000__) +#include "msp430fr2000.h" + +#elif defined (__MSP430FR2100__) +#include "msp430fr2100.h" + +#elif defined (__MSP430FR2110__) +#include "msp430fr2110.h" + +#elif defined (__MSP430FR2111__) +#include "msp430fr2111.h" + +#elif defined (__MSP430FR2310__) +#include "msp430fr2310.h" + +#elif defined (__MSP430FR2311__) +#include "msp430fr2311.h" + +#elif defined (__MSP430FR2422__) +#include "msp430fr2422.h" + +#elif defined (__MSP430FR2433__) +#include "msp430fr2433.h" + +#elif defined (__MSP430FR2512__) +#include "msp430fr2512.h" + +#elif defined (__MSP430FR2522__) +#include "msp430fr2522.h" + +#elif defined (__MSP430FR2532__) +#include "msp430fr2532.h" + +#elif defined (__MSP430FR2533__) +#include "msp430fr2533.h" + +#elif defined (__MSP430FR2632__) +#include "msp430fr2632.h" + +#elif defined (__MSP430FR2633__) +#include "msp430fr2633.h" + +#elif defined (__MSP430F5252__) +#include "msp430f5252.h" + +#elif defined (__MSP430F5253__) +#include "msp430f5253.h" + +#elif defined (__MSP430F5254__) +#include "msp430f5254.h" + +#elif defined (__MSP430F5255__) +#include "msp430f5255.h" + +#elif defined (__MSP430F5256__) +#include "msp430f5256.h" + +#elif defined (__MSP430F5257__) +#include "msp430f5257.h" + +#elif defined (__MSP430F5258__) +#include "msp430f5258.h" + +#elif defined (__MSP430F5259__) +#include "msp430f5259.h" + +#elif defined (__MSP430FR6035__) +#include "msp430fr6035.h" + +#elif defined (__MSP430FR6037__) +#include "msp430fr6037.h" + +#elif defined (__MSP430FR60371__) +#include "msp430fr60371.h" + +#elif defined (__MSP430FR6045__) +#include "msp430fr6045.h" + +#elif defined (__MSP430FR6047__) +#include "msp430fr6047.h" + +#elif defined (__MSP430FR60471__) +#include "msp430fr60471.h" + +#elif defined (__MSP430FR5041__) +#include "msp430fr5041.h" + +#elif defined (__MSP430FR5043__) +#include "msp430fr5043.h" + +#elif defined (__MSP430FR50431__) +#include "msp430fr50431.h" + +#elif defined (__MSP430FR6041__) +#include "msp430fr6041.h" + +#elif defined (__MSP430FR6043__) +#include "msp430fr6043.h" + +#elif defined (__MSP430FR60431__) +#include "msp430fr60431.h" + +#elif defined (__MSP430FR2153__) +#include "msp430fr2153.h" + +#elif defined (__MSP430FR2155__) +#include "msp430fr2155.h" + +#elif defined (__MSP430FR2353__) +#include "msp430fr2353.h" + +#elif defined (__MSP430FR2355__) +#include "msp430fr2355.h" + +#elif defined (__MSP430FR2475__) +#include "msp430fr2475.h" + +#elif defined (__MSP430FR2476__) +#include "msp430fr2476.h" + +#elif defined (__MSP430FR2675__) +#include "msp430fr2675.h" + +#elif defined (__MSP430FR2676__) +#include "msp430fr2676.h" + +#elif defined (__MSP430XGENERIC__) +#include "msp430xgeneric.h" + +#elif defined (__MSP430F5XX_6XXGENERIC__) +#include "msp430f5xx_6xxgeneric.h" + +#elif defined (__MSP430FR5XX_6XXGENERIC__) +#include "msp430fr5xx_6xxgeneric.h" + +#elif defined (__MSP430FR2XX_4XXGENERIC__) +#include "msp430fr2xx_4xxgeneric.h" + +#elif defined (__MSP430FR57XXGENERIC__) +#include "msp430fr57xxgeneric.h" + +#elif defined (__MSP430I2XXGENERIC__) +#include "msp430i2xxgeneric.h" + +/******************************************************************** + * msp430 generic + ********************************************************************/ +#elif defined (__MSP430GENERIC__) +#error "msp430 generic device does not have a default include file" + +#elif defined (__MSP430XGENERIC__) +#error "msp430X generic device does not have a default include file" + + +/******************************************************************** + * + ********************************************************************/ +#else +#error "Failed to match a default include file" +#endif + +#endif /* #ifndef __msp430 */ + diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611.h b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611.h new file mode 100644 index 0000000000..dc50dff4b2 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611.h @@ -0,0 +1,1361 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430x16x devices. +* +* Texas Instruments, Version 2.7 +* +* Rev. 2.0, Fixed definitions for DMA +* Rev. 2.1, Alignment of defintions in Users Guide and of version numbers +* Rev. 2.2, Fixed definitions for I2C +* Rev. 2.21,Fixed definitions for I2C for assembler +* Rev. 2.3, Fixed type in ADC12 bit definitions (replaced ADC10 with ADC12) +* Added SVS +* Added DMA request definitions +* Rev. 2.4, Removed unused def of TASSEL2 / TBSSEL2 +* Rev. 2.5, Added VLD bits in SVS module +* Rev. 2.6, Fixed incorrect bits in I2C STT (wrong:SST) and I2C prefix was missing at some bits +* Rev. 2.7, added definitions for Interrupt Vectors xxIV +* +********************************************************************/ + +#ifndef __msp430x16x +#define __msp430x16x + +#define __MSP430_HEADER_VERSION__ 1208 + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------*/ +/* PERIPHERAL FILE MAP */ +/*----------------------------------------------------------------------------*/ + +#define __MSP430_TI_HEADERS__ + +#include + + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __STDC__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" + +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif /* End #defines for C */ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + +/************************************************************ +* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS +************************************************************/ + +sfr_b(IE1); /* Interrupt Enable 1 */ +#define U0IE IE1 /* UART0 Interrupt Enable Register */ +#define WDTIE (0x01) +#define OFIE (0x02) +#define NMIIE (0x10) +#define ACCVIE (0x20) +#define URXIE0 (0x40) +#define UTXIE0 (0x80) + +sfr_b(IFG1); /* Interrupt Flag 1 */ +#define U0IFG IFG1 /* UART0 Interrupt Flag Register */ +#define WDTIFG (0x01) +#define OFIFG (0x02) +#define NMIIFG (0x10) +#define URXIFG0 (0x40) +#define UTXIFG0 (0x80) + +sfr_b(ME1); /* Module Enable 1 */ +#define U0ME ME1 /* UART0 Module Enable Register */ +#define URXE0 (0x40) +#define UTXE0 (0x80) +#define USPIE0 (0x40) + +sfr_b(IE2); /* Interrupt Enable 2 */ +#define U1IE IE2 /* UART1 Interrupt Enable Register */ +#define URXIE1 (0x10) +#define UTXIE1 (0x20) + +sfr_b(IFG2); /* Interrupt Flag 2 */ +#define U1IFG IFG2 /* UART1 Interrupt Flag Register */ +#define URXIFG1 (0x10) +#define UTXIFG1 (0x20) + +sfr_b(ME2); /* Module Enable 2 */ +#define U1ME ME2 /* UART1 Module Enable Register */ +#define URXE1 (0x10) +#define UTXE1 (0x20) +#define USPIE1 (0x10) + +/************************************************************ +* WATCHDOG TIMER +************************************************************/ +#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */ + +sfr_w(WDTCTL); /* Watchdog Timer Control */ +/* The bit names have been prefixed with "WDT" */ +#define WDTIS0 (0x0001) +#define WDTIS1 (0x0002) +#define WDTSSEL (0x0004) +#define WDTCNTCL (0x0008) +#define WDTTMSEL (0x0010) +#define WDTNMI (0x0020) +#define WDTNMIES (0x0040) +#define WDTHOLD (0x0080) + +#define WDTPW (0x5A00) + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ + +/* INTERRUPT CONTROL */ +/* These two bits are defined in the Special Function Registers */ +/* #define WDTIE 0x01 */ +/* #define WDTIFG 0x01 */ + +/************************************************************ +* HARDWARE MULTIPLIER +************************************************************/ +#define __MSP430_HAS_MPY__ /* Definition to show that Module is available */ + +sfr_w(MPY); /* Multiply Unsigned/Operand 1 */ +sfr_w(MPYS); /* Multiply Signed/Operand 1 */ +sfr_w(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */ +sfr_w(MACS); /* Multiply Signed and Accumulate/Operand 1 */ +sfr_w(OP2); /* Operand 2 */ +sfr_w(RESLO); /* Result Low Word */ +sfr_w(RESHI); /* Result High Word */ +sfr_w(SUMEXT); /* Sum Extend */ + +/************************************************************ +* DIGITAL I/O Port1/2 +************************************************************/ +#define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P1SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P2SEL__ /* Define for DriverLib */ + +sfr_b(P1IN); /* Port 1 Input */ +sfr_b(P1OUT); /* Port 1 Output */ +sfr_b(P1DIR); /* Port 1 Direction */ +sfr_b(P1IFG); /* Port 1 Interrupt Flag */ +sfr_b(P1IES); /* Port 1 Interrupt Edge Select */ +sfr_b(P1IE); /* Port 1 Interrupt Enable */ +sfr_b(P1SEL); /* Port 1 Selection */ + +sfr_b(P2IN); /* Port 2 Input */ +sfr_b(P2OUT); /* Port 2 Output */ +sfr_b(P2DIR); /* Port 2 Direction */ +sfr_b(P2IFG); /* Port 2 Interrupt Flag */ +sfr_b(P2IES); /* Port 2 Interrupt Edge Select */ +sfr_b(P2IE); /* Port 2 Interrupt Enable */ +sfr_b(P2SEL); /* Port 2 Selection */ + +/************************************************************ +* DIGITAL I/O Port3/4 +************************************************************/ +#define __MSP430_HAS_PORT3__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT4__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P3SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P4SEL__ /* Define for DriverLib */ + +sfr_b(P3IN); /* Port 3 Input */ +sfr_b(P3OUT); /* Port 3 Output */ +sfr_b(P3DIR); /* Port 3 Direction */ +sfr_b(P3SEL); /* Port 3 Selection */ + +sfr_b(P4IN); /* Port 4 Input */ +sfr_b(P4OUT); /* Port 4 Output */ +sfr_b(P4DIR); /* Port 4 Direction */ +sfr_b(P4SEL); /* Port 4 Selection */ + +/************************************************************ +* DIGITAL I/O Port5/6 +************************************************************/ +#define __MSP430_HAS_PORT5__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT6__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P5SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P6SEL__ /* Define for DriverLib */ + +sfr_b(P5IN); /* Port 5 Input */ +sfr_b(P5OUT); /* Port 5 Output */ +sfr_b(P5DIR); /* Port 5 Direction */ +sfr_b(P5SEL); /* Port 5 Selection */ + +sfr_b(P6IN); /* Port 6 Input */ +sfr_b(P6OUT); /* Port 6 Output */ +sfr_b(P6DIR); /* Port 6 Direction */ +sfr_b(P6SEL); /* Port 6 Selection */ + +/************************************************************ +* USART +************************************************************/ + +/* UxCTL */ +#define PENA (0x80) /* Parity enable */ +#define PEV (0x40) /* Parity 0:odd / 1:even */ +#define SPB (0x20) /* Stop Bits 0:one / 1: two */ +#define CHAR (0x10) /* Data 0:7-bits / 1:8-bits */ +#define LISTEN (0x08) /* Listen mode */ +#define SYNC (0x04) /* UART / SPI mode */ +#define MM (0x02) /* Master Mode off/on */ +#define SWRST (0x01) /* USART Software Reset */ + +/* UxTCTL */ +#define CKPH (0x80) /* SPI: Clock Phase */ +#define CKPL (0x40) /* Clock Polarity */ +#define SSEL1 (0x20) /* Clock Source Select 1 */ +#define SSEL0 (0x10) /* Clock Source Select 0 */ +#define URXSE (0x08) /* Receive Start edge select */ +#define TXWAKE (0x04) /* TX Wake up mode */ +#define STC (0x02) /* SPI: STC enable 0:on / 1:off */ +#define TXEPT (0x01) /* TX Buffer empty */ + +/* UxRCTL */ +#define FE (0x80) /* Frame Error */ +#define PE (0x40) /* Parity Error */ +#define OE (0x20) /* Overrun Error */ +#define BRK (0x10) /* Break detected */ +#define URXEIE (0x08) /* RX Error interrupt enable */ +#define URXWIE (0x04) /* RX Wake up interrupt enable */ +#define RXWAKE (0x02) /* RX Wake up detect */ +#define RXERR (0x01) /* RX Error Error */ + +/************************************************************ +* USART 0 +************************************************************/ +#define __MSP430_HAS_UART0__ /* Definition to show that Module is available */ + +sfr_b(U0CTL); /* USART 0 Control */ +sfr_b(U0TCTL); /* USART 0 Transmit Control */ +sfr_b(U0RCTL); /* USART 0 Receive Control */ +sfr_b(U0MCTL); /* USART 0 Modulation Control */ +sfr_b(U0BR0); /* USART 0 Baud Rate 0 */ +sfr_b(U0BR1); /* USART 0 Baud Rate 1 */ +sfr_b(U0RXBUF); /* USART 0 Receive Buffer */ +sfr_b(U0TXBUF); /* USART 0 Transmit Buffer */ + +/* Alternate register names */ + +#define UCTL0 U0CTL /* USART 0 Control */ +#define UTCTL0 U0TCTL /* USART 0 Transmit Control */ +#define URCTL0 U0RCTL /* USART 0 Receive Control */ +#define UMCTL0 U0MCTL /* USART 0 Modulation Control */ +#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */ +#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */ +#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */ +#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */ +#define UCTL0_ U0CTL_ /* USART 0 Control */ +#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */ +#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */ +#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */ +#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */ +#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */ +#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */ +#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */ +#define UCTL_0 U0CTL /* USART 0 Control */ +#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */ +#define URCTL_0 U0RCTL /* USART 0 Receive Control */ +#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */ +#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */ +#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */ +#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */ +#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */ +#define UCTL_0_ U0CTL_ /* USART 0 Control */ +#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */ +#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */ +#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */ +#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */ +#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */ +#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */ +#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */ + +/************************************************************ +* USART 1 +************************************************************/ +#define __MSP430_HAS_UART1__ /* Definition to show that Module is available */ + +sfr_b(U1CTL); /* USART 1 Control */ +sfr_b(U1TCTL); /* USART 1 Transmit Control */ +sfr_b(U1RCTL); /* USART 1 Receive Control */ +sfr_b(U1MCTL); /* USART 1 Modulation Control */ +sfr_b(U1BR0); /* USART 1 Baud Rate 0 */ +sfr_b(U1BR1); /* USART 1 Baud Rate 1 */ +sfr_b(U1RXBUF); /* USART 1 Receive Buffer */ +sfr_b(U1TXBUF); /* USART 1 Transmit Buffer */ + +/* Alternate register names */ + +#define UCTL1 U1CTL /* USART 1 Control */ +#define UTCTL1 U1TCTL /* USART 1 Transmit Control */ +#define URCTL1 U1RCTL /* USART 1 Receive Control */ +#define UMCTL1 U1MCTL /* USART 1 Modulation Control */ +#define UBR01 U1BR0 /* USART 1 Baud Rate 0 */ +#define UBR11 U1BR1 /* USART 1 Baud Rate 1 */ +#define RXBUF1 U1RXBUF /* USART 1 Receive Buffer */ +#define TXBUF1 U1TXBUF /* USART 1 Transmit Buffer */ +#define UCTL1_ U1CTL_ /* USART 1 Control */ +#define UTCTL1_ U1TCTL_ /* USART 1 Transmit Control */ +#define URCTL1_ U1RCTL_ /* USART 1 Receive Control */ +#define UMCTL1_ U1MCTL_ /* USART 1 Modulation Control */ +#define UBR01_ U1BR0_ /* USART 1 Baud Rate 0 */ +#define UBR11_ U1BR1_ /* USART 1 Baud Rate 1 */ +#define RXBUF1_ U1RXBUF_ /* USART 1 Receive Buffer */ +#define TXBUF1_ U1TXBUF_ /* USART 1 Transmit Buffer */ +#define UCTL_1 U1CTL /* USART 1 Control */ +#define UTCTL_1 U1TCTL /* USART 1 Transmit Control */ +#define URCTL_1 U1RCTL /* USART 1 Receive Control */ +#define UMCTL_1 U1MCTL /* USART 1 Modulation Control */ +#define UBR0_1 U1BR0 /* USART 1 Baud Rate 0 */ +#define UBR1_1 U1BR1 /* USART 1 Baud Rate 1 */ +#define RXBUF_1 U1RXBUF /* USART 1 Receive Buffer */ +#define TXBUF_1 U1TXBUF /* USART 1 Transmit Buffer */ +#define UCTL_1_ U1CTL_ /* USART 1 Control */ +#define UTCTL_1_ U1TCTL_ /* USART 1 Transmit Control */ +#define URCTL_1_ U1RCTL_ /* USART 1 Receive Control */ +#define UMCTL_1_ U1MCTL_ /* USART 1 Modulation Control */ +#define UBR0_1_ U1BR0_ /* USART 1 Baud Rate 0 */ +#define UBR1_1_ U1BR1_ /* USART 1 Baud Rate 1 */ +#define RXBUF_1_ U1RXBUF_ /* USART 1 Receive Buffer */ +#define TXBUF_1_ U1TXBUF_ /* USART 1 Transmit Buffer */ + +/************************************************************ +* USART0 I2C +************************************************************/ +#define __MSP430_HAS_I2C__ /* Definition to show that Module is available */ + +sfr_b(I2CIE); /* I2C Interrupt Enable */ +#define ALIE (0x01) /* Arbitration lost */ +#define NACKIE (0x02) /* No acknowledge */ +#define OAIE (0x04) /* Own address */ +#define ARDYIE (0x08) /* Access ready (opeation complete) */ +#define RXRDYIE (0x10) /* Receive ready (data received) */ +#define TXRDYIE (0x20) /* Transmit ready (transmit register empty) */ +#define GCIE (0x40) /* General call */ +#define STTIE (0x80) /* Start condition */ + +sfr_b(I2CIFG); /* I2C Interrupt Flag */ +#define ALIFG (0x01) /* Arbitration lost */ +#define NACKIFG (0x02) /* No acknowledge */ +#define OAIFG (0x04) /* Own address */ +#define ARDYIFG (0x08) /* Access ready (opeation complete) */ +#define RXRDYIFG (0x10) /* Receive ready (data received) */ +#define TXRDYIFG (0x20) /* Transmit ready (transmit register empty) */ +#define GCIFG (0x40) /* General call */ +#define STTIFG (0x80) /* Start condition */ + +sfr_b(I2CNDAT); /* I2C Data Count */ + +/* USART 0 Control */ +#define I2CEN (0x01) /* I2C enable */ +#define MST (0x02) /* I2C master */ +#define XA (0x10) /* I2C extended addressing */ +#define I2C (0x20) /* USART I2C */ +#define TXDMAEN (0x40) /* Transmit DMA enable */ +#define RXDMAEN (0x80) /* Receive DMA enable */ + +sfr_b(I2CTCTL); /* I2C Transfer Control */ +#define I2CSTT (0x01) /* Start bit */ +#define I2CSTP (0x02) /* Stop bit */ +#define I2CSTB (0x04) /* Start byte mode */ +#define I2CTRX (0x08) /* Transmit */ +#define I2CSSEL0 (0x10) /* Clock select bit 0 */ +#define I2CSSEL1 (0x20) /* Clock select bit 1 */ +#define I2CRM (0x40) /* Repeat mode */ +#define I2CWORD (0x80) /* Word data mode */ + +#define I2CSSEL_0 (0x0000) /* I2C clock select 0: UCLK */ +#define I2CSSEL_1 (0x0010) /* I2C clock select 1: ACLK */ +#define I2CSSEL_2 (0x0020) /* I2C clock select 2: SMCLK */ +#define I2CSSEL_3 (0x0030) /* I2C clock select 3: SMCLK */ + +#define I2CMM_0 (0x00) /* Master mode 0 */ +#define I2CMM_1 (I2CSTT) /* Master mode 1 */ +#define I2CMM_2 (I2CSTP+I2CSTT) /* Master mode 2 */ +#define I2CMM_3 (I2CRM+I2CSTT) /* Master mode 3 */ +#define I2CMM_4 (I2CSTP) /* Master mode 4 */ + +sfr_b(I2CDCTL); /* I2C Data Control */ +#define I2CBB (0x01) /* Bus busy */ +#define I2CRXOVR (0x02) /* Receiver overrun */ +#define I2CTXUDF (0x04) /* Transmit underflow */ +#define I2CSBD (0x08) /* Received byte */ +#define I2CSCLLOW (0x10) /* SCL being held low */ +#define I2CBUSY (0x20) /* I2C Busy Flag */ + +sfr_b(I2CPSC); /* I2C Pre-scaler */ +sfr_b(I2CSCLH); /* I2C SCL High */ +sfr_b(I2CSCLL); /* I2C SCL Low */ +sfr_b(I2CDRB); /* I2C Data for Byte access */ +sfr_w(I2CDRW); /* I2C Data for Word access */ + +sfr_w(I2COA); /* I2C Own Address */ +sfr_w(I2CSA); /* I2C Slave Address */ + +sfr_w(I2CIV); /* I2C Interrupt Vector */ +#define I2CIV_NONE (0x0000) /* I2C interrupt vector: No interrupt pending */ +#define I2CIV_AL (0x0002) /* I2C interrupt vector: Arbitration lost (ALIFG) */ +#define I2CIV_NACK (0x0004) /* I2C interrupt vector: No acknowledge (NACKIFG) */ +#define I2CIV_OA (0x0006) /* I2C interrupt vector: Own address (OAIFG) */ +#define I2CIV_ARDY (0x0008) /* I2C interrupt vector: Access ready (ARDYIFG) */ +#define I2CIV_RXRDY (0x000A) /* I2C interrupt vector: Receive ready (RXRDYIFG) */ +#define I2CIV_TXRDY (0x000C) /* I2C interrupt vector: Transmit ready (TXRDYIFG) */ +#define I2CIV_GC (0x000E) /* I2C interrupt vector: General call (GCIFG) */ +#define I2CIV_STT (0x0010) /* I2C interrupt vector: Start condition (STTIFG) */ + +/************************************************************ +* Timer A3 +************************************************************/ +#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */ + +sfr_w(TAIV); /* Timer A Interrupt Vector Word */ +sfr_w(TACTL); /* Timer A Control */ +sfr_w(TACCTL0); /* Timer A Capture/Compare Control 0 */ +sfr_w(TACCTL1); /* Timer A Capture/Compare Control 1 */ +sfr_w(TACCTL2); /* Timer A Capture/Compare Control 2 */ +sfr_w(TAR); /* Timer A Counter Register */ +sfr_w(TACCR0); /* Timer A Capture/Compare 0 */ +sfr_w(TACCR1); /* Timer A Capture/Compare 1 */ +sfr_w(TACCR2); /* Timer A Capture/Compare 2 */ + +/* Alternate register names */ +#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ +#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ +#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ +#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */ +#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */ +#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */ +#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ +#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ +#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ +#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ +#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ +#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ +/* Alternate register names - 5xx style */ +#define TA0IV TAIV /* Timer A Interrupt Vector Word */ +#define TA0CTL TACTL /* Timer A Control */ +#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ +#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ +#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ +#define TA0R TAR /* Timer A Counter Register */ +#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */ +#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */ +#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */ +#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */ +#define TA0CTL_ TACTL_ /* Timer A Control */ +#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ +#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ +#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ +#define TA0R_ TAR_ /* Timer A Counter Register */ +#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ +#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ +#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ +#define TIMER0_A1_VECTOR TIMERA1_VECTOR /* Int. Vector: Timer A CC1-2, TA */ +#define TIMER0_A0_VECTOR TIMERA0_VECTOR /* Int. Vector: Timer A CC0 */ + +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (0x0020) /* Timer A mode control: 2 - Continous up */ +#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ + +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ +#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ +#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ +#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ +#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ +#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ + +/* TA3IV Definitions */ +#define TAIV_NONE (0x0000) /* No Interrupt pending */ +#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */ +#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */ +#define TAIV_6 (0x0006) /* Reserved */ +#define TAIV_8 (0x0008) /* Reserved */ +#define TAIV_TAIFG (0x000A) /* TAIFG */ + +/* Alternate register names - 5xx style */ +#define TA0IV_NONE (0x0000) /* No Interrupt pending */ +#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_6 (0x0006) /* Reserved */ +#define TA0IV_8 (0x0008) /* Reserved */ +#define TA0IV_TAIFG (0x000A) /* TA0IFG */ + +/************************************************************ +* Timer B7 +************************************************************/ +#define __MSP430_HAS_TB7__ /* Definition to show that Module is available */ + +sfr_w(TBIV); /* Timer B Interrupt Vector Word */ +sfr_w(TBCTL); /* Timer B Control */ +sfr_w(TBCCTL0); /* Timer B Capture/Compare Control 0 */ +sfr_w(TBCCTL1); /* Timer B Capture/Compare Control 1 */ +sfr_w(TBCCTL2); /* Timer B Capture/Compare Control 2 */ +sfr_w(TBCCTL3); /* Timer B Capture/Compare Control 3 */ +sfr_w(TBCCTL4); /* Timer B Capture/Compare Control 4 */ +sfr_w(TBCCTL5); /* Timer B Capture/Compare Control 5 */ +sfr_w(TBCCTL6); /* Timer B Capture/Compare Control 6 */ +sfr_w(TBR); /* Timer B Counter Register */ +sfr_w(TBCCR0); /* Timer B Capture/Compare 0 */ +sfr_w(TBCCR1); /* Timer B Capture/Compare 1 */ +sfr_w(TBCCR2); /* Timer B Capture/Compare 2 */ +sfr_w(TBCCR3); /* Timer B Capture/Compare 3 */ +sfr_w(TBCCR4); /* Timer B Capture/Compare 4 */ +sfr_w(TBCCR5); /* Timer B Capture/Compare 5 */ +sfr_w(TBCCR6); /* Timer B Capture/Compare 6 */ + +/* Alternate register names - 5xx style */ +#define TB0IV TBIV /* Timer B Interrupt Vector Word */ +#define TB0CTL TBCTL /* Timer B Control */ +#define TB0CCTL0 TBCCTL0 /* Timer B Capture/Compare Control 0 */ +#define TB0CCTL1 TBCCTL1 /* Timer B Capture/Compare Control 1 */ +#define TB0CCTL2 TBCCTL2 /* Timer B Capture/Compare Control 2 */ +#define TB0CCTL3 TBCCTL3 /* Timer B Capture/Compare Control 3 */ +#define TB0CCTL4 TBCCTL4 /* Timer B Capture/Compare Control 4 */ +#define TB0CCTL5 TBCCTL5 /* Timer B Capture/Compare Control 5 */ +#define TB0CCTL6 TBCCTL6 /* Timer B Capture/Compare Control 6 */ +#define TB0R TBR /* Timer B Counter Register */ +#define TB0CCR0 TBCCR0 /* Timer B Capture/Compare 0 */ +#define TB0CCR1 TBCCR1 /* Timer B Capture/Compare 1 */ +#define TB0CCR2 TBCCR2 /* Timer B Capture/Compare 2 */ +#define TB0CCR3 TBCCR3 /* Timer B Capture/Compare 3 */ +#define TB0CCR4 TBCCR4 /* Timer B Capture/Compare 4 */ +#define TB0CCR5 TBCCR5 /* Timer B Capture/Compare 5 */ +#define TB0CCR6 TBCCR6 /* Timer B Capture/Compare 6 */ +#define TB0IV_ TBIV_ /* Timer B Interrupt Vector Word */ +#define TB0CTL_ TBCTL_ /* Timer B Control */ +#define TB0CCTL0_ TBCCTL0_ /* Timer B Capture/Compare Control 0 */ +#define TB0CCTL1_ TBCCTL1_ /* Timer B Capture/Compare Control 1 */ +#define TB0CCTL2_ TBCCTL2_ /* Timer B Capture/Compare Control 2 */ +#define TB0CCTL3_ TBCCTL3_ /* Timer B Capture/Compare Control 3 */ +#define TB0CCTL4_ TBCCTL4_ /* Timer B Capture/Compare Control 4 */ +#define TB0CCTL5_ TBCCTL5_ /* Timer B Capture/Compare Control 5 */ +#define TB0CCTL6_ TBCCTL6_ /* Timer B Capture/Compare Control 6 */ +#define TB0R_ TBR_ /* Timer B Counter Register */ +#define TB0CCR0_ TBCCR0_ /* Timer B Capture/Compare 0 */ +#define TB0CCR1_ TBCCR1_ /* Timer B Capture/Compare 1 */ +#define TB0CCR2_ TBCCR2_ /* Timer B Capture/Compare 2 */ +#define TB0CCR3_ TBCCR3_ /* Timer B Capture/Compare 3 */ +#define TB0CCR4_ TBCCR4_ /* Timer B Capture/Compare 4 */ +#define TB0CCR5_ TBCCR5_ /* Timer B Capture/Compare 5 */ +#define TB0CCR6_ TBCCR6_ /* Timer B Capture/Compare 6 */ +#define TIMER0_B1_VECTOR TIMERB1_VECTOR /* Int. Vector: Timer B CC1-6, TB */ +#define TIMER0_B0_VECTOR TIMERB0_VECTOR /* Int. Vector: Timer B CC0 */ + +#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */ +#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */ +#define CNTL1 (0x1000) /* Counter lenght 1 */ +#define CNTL0 (0x0800) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200) /* Clock source 1 */ +#define TBSSEL0 (0x0100) /* Clock source 0 */ +#define TBCLR (0x0004) /* Timer B counter clear */ +#define TBIE (0x0002) /* Timer B interrupt enable */ +#define TBIFG (0x0001) /* Timer B interrupt flag */ + +#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */ +#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */ + +#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */ +#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */ +#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */ +#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */ +#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */ +#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */ +#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */ +#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */ +#define SHR_0 (0x0000) /* Timer B Group: 0 - individually */ +#define SHR_1 (0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (0x4000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (0x6000) /* Timer B Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0x0000) /* Timer B Group: 0 - individually */ +#define TBCLGRP_1 (0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (0x4000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (0x6000) /* Timer B Group: 3 - 1 group (all) */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +#define CLLD1 (0x0400) /* Compare latch load source 1 */ +#define CLLD0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TB7IV Definitions */ +#define TBIV_NONE (0x0000) /* No Interrupt pending */ +#define TBIV_TBCCR1 (0x0002) /* TBCCR1_CCIFG */ +#define TBIV_TBCCR2 (0x0004) /* TBCCR2_CCIFG */ +#define TBIV_TBCCR3 (0x0006) /* TBCCR3_CCIFG */ +#define TBIV_TBCCR4 (0x0008) /* TBCCR4_CCIFG */ +#define TBIV_TBCCR5 (0x000A) /* TBCCR3_CCIFG */ +#define TBIV_TBCCR6 (0x000C) /* TBCCR4_CCIFG */ +#define TBIV_TBIFG (0x000E) /* TBIFG */ + +/* Alternate register names - 5xx style */ +#define TB0IV_NONE (0x0000) /* No Interrupt pending */ +#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */ +#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */ +#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */ +#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */ +#define TB0IV_TBCCR5 (0x000A) /* TB0CCR3_CCIFG */ +#define TB0IV_TBCCR6 (0x000C) /* TB0CCR4_CCIFG */ +#define TB0IV_TBIFG (0x000E) /* TB0IFG */ + +/************************************************************ +* Basic Clock Module +************************************************************/ +#define __MSP430_HAS_BASIC_CLOCK__ /* Definition to show that Module is available */ + +sfr_b(DCOCTL); /* DCO Clock Frequency Control */ +sfr_b(BCSCTL1); /* Basic Clock System Control 1 */ +sfr_b(BCSCTL2); /* Basic Clock System Control 2 */ + +#define MOD0 (0x01) /* Modulation Bit 0 */ +#define MOD1 (0x02) /* Modulation Bit 1 */ +#define MOD2 (0x04) /* Modulation Bit 2 */ +#define MOD3 (0x08) /* Modulation Bit 3 */ +#define MOD4 (0x10) /* Modulation Bit 4 */ +#define DCO0 (0x20) /* DCO Select Bit 0 */ +#define DCO1 (0x40) /* DCO Select Bit 1 */ +#define DCO2 (0x80) /* DCO Select Bit 2 */ + +#define RSEL0 (0x01) /* Range Select Bit 0 */ +#define RSEL1 (0x02) /* Range Select Bit 1 */ +#define RSEL2 (0x04) /* Range Select Bit 2 */ +#define XT5V (0x08) /* XT5V should always be reset */ +#define DIVA0 (0x10) /* ACLK Divider 0 */ +#define DIVA1 (0x20) /* ACLK Divider 1 */ +#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ +#define XT2OFF (0x80) /* Enable XT2CLK */ + +#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */ +#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */ +#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */ +#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */ + +#define DCOR (0x01) /* Enable External Resistor : 1 */ +#define DIVS0 (0x02) /* SMCLK Divider 0 */ +#define DIVS1 (0x04) /* SMCLK Divider 1 */ +#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ +#define DIVM0 (0x10) /* MCLK Divider 0 */ +#define DIVM1 (0x20) /* MCLK Divider 1 */ +#define SELM0 (0x40) /* MCLK Source Select 0 */ +#define SELM1 (0x80) /* MCLK Source Select 1 */ + +#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */ +#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */ +#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */ +#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */ + +#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */ +#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */ +#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */ +#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */ + +#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */ +#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */ +#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */ +#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */ + +/************************************************************ +* Brown-Out, Supply Voltage Supervision (SVS) +************************************************************/ +#define __MSP430_HAS_SVS__ /* Definition to show that Module is available */ + +sfr_b(SVSCTL); /* SVS Control */ +#define SVSFG (0x01) /* SVS Flag */ +#define SVSOP (0x02) /* SVS output (read only) */ +#define SVSON (0x04) /* Switches the SVS on/off */ +#define PORON (0x08) /* Enable POR Generation if Low Voltage */ +#define VLD0 (0x10) +#define VLD1 (0x20) +#define VLD2 (0x40) +#define VLD3 (0x80) + +#define VLDON (0x10) +#define VLDOFF (0x00) +#define VLD_1_8V (0x10) + +/************************************************************* +* Flash Memory +*************************************************************/ +#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */ + +sfr_w(FCTL1); /* FLASH Control 1 */ +sfr_w(FCTL2); /* FLASH Control 2 */ +sfr_w(FCTL3); /* FLASH Control 3 */ + +#define FRKEY (0x9600) /* Flash key returned by read */ +#define FWKEY (0xA500) /* Flash key for write */ +#define FXKEY (0x3300) /* for use with XOR instruction */ + +#define ERASE (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004) /* Enable bit for Flash mass erase */ +#define WRT (0x0040) /* Enable bit for Flash write */ +#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ +#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */ + +#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */ +#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */ +#ifndef FN2 +#define FN2 (0x0004) +#endif +#ifndef FN3 +#define FN3 (0x0008) +#endif +#ifndef FN4 +#define FN4 (0x0010) +#endif +#define FN5 (0x0020) +#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */ +#define FSSEL1 (0x0080) /* Flash clock select 1 */ + +#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */ +#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */ +#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */ +#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */ + +#define BUSY (0x0001) /* Flash busy: 1 */ +#define KEYV (0x0002) /* Flash Key violation flag */ +#define ACCVIFG (0x0004) /* Flash Access violation flag */ +#define WAIT (0x0008) /* Wait flag for segment write */ +#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020) /* Flash Emergency Exit */ + +/************************************************************ +* Comparator A +************************************************************/ +#define __MSP430_HAS_COMPA__ /* Definition to show that Module is available */ + +sfr_b(CACTL1); /* Comparator A Control 1 */ +sfr_b(CACTL2); /* Comparator A Control 2 */ +sfr_b(CAPD); /* Comparator A Port Disable */ + +#define CAIFG (0x01) /* Comp. A Interrupt Flag */ +#define CAIE (0x02) /* Comp. A Interrupt Enable */ +#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */ +#define CAON (0x08) /* Comp. A enable */ +#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */ +#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */ +#define CARSEL (0x40) /* Comp. A Internal Reference Enable */ +#define CAEX (0x80) /* Comp. A Exchange Inputs */ + +#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */ +#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */ +#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */ +#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/ + +#define CAOUT (0x01) /* Comp. A Output */ +#define CAF (0x02) /* Comp. A Enable Output Filter */ +#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */ +#define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */ +#define CACTL24 (0x10) +#define CACTL25 (0x20) +#define CACTL26 (0x40) +#define CACTL27 (0x80) + +#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */ +#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */ +#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */ +#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */ +#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */ +#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */ +#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */ +#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */ + +/************************************************************ +* ADC12 +************************************************************/ +#define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */ + +sfr_w(ADC12CTL0); /* ADC12 Control 0 */ +sfr_w(ADC12CTL1); /* ADC12 Control 1 */ +sfr_w(ADC12IFG); /* ADC12 Interrupt Flag */ +sfr_w(ADC12IE); /* ADC12 Interrupt Enable */ +sfr_w(ADC12IV); /* ADC12 Interrupt Vector Word */ + +#define ADC12MEM_ (0x0140) /* ADC12 Conversion Memory */ +#ifndef __STDC__ +#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */ +#else +#define ADC12MEM ((volatile int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ +#endif +sfr_w(ADC12MEM0); /* ADC12 Conversion Memory 0 */ +sfr_w(ADC12MEM1); /* ADC12 Conversion Memory 1 */ +sfr_w(ADC12MEM2); /* ADC12 Conversion Memory 2 */ +sfr_w(ADC12MEM3); /* ADC12 Conversion Memory 3 */ +sfr_w(ADC12MEM4); /* ADC12 Conversion Memory 4 */ +sfr_w(ADC12MEM5); /* ADC12 Conversion Memory 5 */ +sfr_w(ADC12MEM6); /* ADC12 Conversion Memory 6 */ +sfr_w(ADC12MEM7); /* ADC12 Conversion Memory 7 */ +sfr_w(ADC12MEM8); /* ADC12 Conversion Memory 8 */ +sfr_w(ADC12MEM9); /* ADC12 Conversion Memory 9 */ +sfr_w(ADC12MEM10); /* ADC12 Conversion Memory 10 */ +sfr_w(ADC12MEM11); /* ADC12 Conversion Memory 11 */ +sfr_w(ADC12MEM12); /* ADC12 Conversion Memory 12 */ +sfr_w(ADC12MEM13); /* ADC12 Conversion Memory 13 */ +sfr_w(ADC12MEM14); /* ADC12 Conversion Memory 14 */ +sfr_w(ADC12MEM15); /* ADC12 Conversion Memory 15 */ + +#define ADC12MCTL_ (0x0080) /* ADC12 Memory Control */ +#ifndef __STDC__ +#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */ +#else +#define ADC12MCTL ((volatile char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ +#endif +sfr_b(ADC12MCTL0); /* ADC12 Memory Control 0 */ +sfr_b(ADC12MCTL1); /* ADC12 Memory Control 1 */ +sfr_b(ADC12MCTL2); /* ADC12 Memory Control 2 */ +sfr_b(ADC12MCTL3); /* ADC12 Memory Control 3 */ +sfr_b(ADC12MCTL4); /* ADC12 Memory Control 4 */ +sfr_b(ADC12MCTL5); /* ADC12 Memory Control 5 */ +sfr_b(ADC12MCTL6); /* ADC12 Memory Control 6 */ +sfr_b(ADC12MCTL7); /* ADC12 Memory Control 7 */ +sfr_b(ADC12MCTL8); /* ADC12 Memory Control 8 */ +sfr_b(ADC12MCTL9); /* ADC12 Memory Control 9 */ +sfr_b(ADC12MCTL10); /* ADC12 Memory Control 10 */ +sfr_b(ADC12MCTL11); /* ADC12 Memory Control 11 */ +sfr_b(ADC12MCTL12); /* ADC12 Memory Control 12 */ +sfr_b(ADC12MCTL13); /* ADC12 Memory Control 13 */ +sfr_b(ADC12MCTL14); /* ADC12 Memory Control 14 */ +sfr_b(ADC12MCTL15); /* ADC12 Memory Control 15 */ + +/* ADC12CTL0 */ +#define ADC12SC (0x001) /* ADC12 Start Conversion */ +#define ENC (0x002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON (0x010) /* ADC12 On/enable */ +#define REFON (0x020) /* ADC12 Reference on */ +#define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define MSC (0x080) /* ADC12 Multiple SampleConversion */ +#define SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */ +#define SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */ +#define SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */ +#define SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */ +#define SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */ +#define SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */ +#define SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */ +#define SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */ +#define MSH (0x080) + +#define SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 */ +#define ADC12BUSY (0x0001) /* ADC12 Busy */ +#define CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */ +#define CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */ +#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */ +#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */ +#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */ +#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */ +#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */ +#define ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ +#define SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ +#define SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */ +#define SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */ +#define CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */ +#define CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */ +#define CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */ +#define CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */ + +#define CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */ +#define CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */ +#define CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */ +#define CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */ +#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */ +#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */ +#define SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */ +#define SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */ +#define SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */ +#define SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */ +#define CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */ +#define CSTARTADD_1 (0x1000) /* ADC12 Conversion Start Address: 1 */ +#define CSTARTADD_2 (0x2000) /* ADC12 Conversion Start Address: 2 */ +#define CSTARTADD_3 (0x3000) /* ADC12 Conversion Start Address: 3 */ +#define CSTARTADD_4 (0x4000) /* ADC12 Conversion Start Address: 4 */ +#define CSTARTADD_5 (0x5000) /* ADC12 Conversion Start Address: 5 */ +#define CSTARTADD_6 (0x6000) /* ADC12 Conversion Start Address: 6 */ +#define CSTARTADD_7 (0x7000) /* ADC12 Conversion Start Address: 7 */ +#define CSTARTADD_8 (0x8000) /* ADC12 Conversion Start Address: 8 */ +#define CSTARTADD_9 (0x9000) /* ADC12 Conversion Start Address: 9 */ +#define CSTARTADD_10 (0xA000) /* ADC12 Conversion Start Address: 10 */ +#define CSTARTADD_11 (0xB000) /* ADC12 Conversion Start Address: 11 */ +#define CSTARTADD_12 (0xC000) /* ADC12 Conversion Start Address: 12 */ +#define CSTARTADD_13 (0xD000) /* ADC12 Conversion Start Address: 13 */ +#define CSTARTADD_14 (0xE000) /* ADC12 Conversion Start Address: 14 */ +#define CSTARTADD_15 (0xF000) /* ADC12 Conversion Start Address: 15 */ + +/* ADC12MCTLx */ +#define INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ +#define SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ +#define SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ +#define EOS (0x0080) /* ADC12 End of Sequence */ + +#define INCH_0 (0) /* ADC12 Input Channel 0 */ +#define INCH_1 (1) /* ADC12 Input Channel 1 */ +#define INCH_2 (2) /* ADC12 Input Channel 2 */ +#define INCH_3 (3) /* ADC12 Input Channel 3 */ +#define INCH_4 (4) /* ADC12 Input Channel 4 */ +#define INCH_5 (5) /* ADC12 Input Channel 5 */ +#define INCH_6 (6) /* ADC12 Input Channel 6 */ +#define INCH_7 (7) /* ADC12 Input Channel 7 */ +#define INCH_8 (8) /* ADC12 Input Channel 8 */ +#define INCH_9 (9) /* ADC12 Input Channel 9 */ +#define INCH_10 (10) /* ADC12 Input Channel 10 */ +#define INCH_11 (11) /* ADC12 Input Channel 11 */ +#define INCH_12 (12) /* ADC12 Input Channel 12 */ +#define INCH_13 (13) /* ADC12 Input Channel 13 */ +#define INCH_14 (14) /* ADC12 Input Channel 14 */ +#define INCH_15 (15) /* ADC12 Input Channel 15 */ + +#define SREF_0 (0x0000) /* ADC12 Select Reference 0 */ +#define SREF_1 (0x0010) /* ADC12 Select Reference 1 */ +#define SREF_2 (0x0020) /* ADC12 Select Reference 2 */ +#define SREF_3 (0x0030) /* ADC12 Select Reference 3 */ +#define SREF_4 (0x0040) /* ADC12 Select Reference 4 */ +#define SREF_5 (0x0050) /* ADC12 Select Reference 5 */ +#define SREF_6 (0x0060) /* ADC12 Select Reference 6 */ +#define SREF_7 (0x0070) /* ADC12 Select Reference 7 */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ +#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */ + +/************************************************************ +* DAC12 +************************************************************/ +#define __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */ + +sfr_w(DAC12_0CTL); /* DAC12_0 Control */ +sfr_w(DAC12_1CTL); /* DAC12_1 Control */ + +#define DAC12GRP (0x0001) /* DAC12 group */ +#define DAC12ENC (0x0002) /* DAC12 enable conversion */ +#define DAC12IFG (0x0004) /* DAC12 interrupt flag */ +#define DAC12IE (0x0008) /* DAC12 interrupt enable */ +#define DAC12DF (0x0010) /* DAC12 data format */ +#define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */ +#define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */ +#define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */ +#define DAC12IR (0x0100) /* DAC12 input reference and output range */ +#define DAC12CALON (0x0200) /* DAC12 calibration */ +#define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */ +#define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */ +#define DAC12RES (0x1000) /* DAC12 resolution */ +#define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */ +#define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */ + +#define DAC12AMP_0 (0x0000) /* DAC12 amplifier 0: off, 3-state */ +#define DAC12AMP_1 (0x0020) /* DAC12 amplifier 1: off, off */ +#define DAC12AMP_2 (0x0040) /* DAC12 amplifier 2: low, low */ +#define DAC12AMP_3 (0x0060) /* DAC12 amplifier 3: low, medium */ +#define DAC12AMP_4 (0x0080) /* DAC12 amplifier 4: low, high */ +#define DAC12AMP_5 (0x00A0) /* DAC12 amplifier 5: medium, medium */ +#define DAC12AMP_6 (0x00C0) /* DAC12 amplifier 6: medium, high */ +#define DAC12AMP_7 (0x00E0) /* DAC12 amplifier 7: high, high */ + +#define DAC12LSEL_0 (0x0000) /* DAC12 load select 0: direct */ +#define DAC12LSEL_1 (0x0400) /* DAC12 load select 1: latched with DAT */ +#define DAC12LSEL_2 (0x0800) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */ +#define DAC12LSEL_3 (0x0C00) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */ + +#define DAC12SREF_0 (0x0000) /* DAC12 reference 0: Vref+ */ +#define DAC12SREF_1 (0x2000) /* DAC12 reference 1: Vref+ */ +#define DAC12SREF_2 (0x4000) /* DAC12 reference 2: Veref+ */ +#define DAC12SREF_3 (0x6000) /* DAC12 reference 3: Veref+ */ + +sfr_w(DAC12_0DAT); /* DAC12_0 Data */ +sfr_w(DAC12_1DAT); /* DAC12_1 Data */ +/************************************************************ +* DMA +************************************************************/ +#define __MSP430_HAS_DMA_3__ /* Definition to show that Module is available */ + +sfr_w(DMACTL0); /* DMA Module Control 0 */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA1TSEL0 (0x0010) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0020) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0040) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0080) /* DMA channel 1 transfer select bit 3 */ +#define DMA2TSEL0 (0x0100) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0200) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0400) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0800) /* DMA channel 2 transfer select bit 3 */ + +#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw)*/ +#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: Timer_A (TACCR2.IFG) */ +#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: Timer_B (TBCCR2.IFG) */ +#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: UART0/I2C receive */ +#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: UART0/I2C transmit */ +#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: DAC12_0CTL.DAC12IFG */ +#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: UART1 receive */ +#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: UART1 transmit */ +#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: Multiplier ready */ +#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */ +#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */ + +#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ */ +#define DMA1TSEL_1 (0x0010) /* DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */ +#define DMA1TSEL_2 (0x0020) /* DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */ +#define DMA1TSEL_3 (0x0030) /* DMA channel 1 transfer select 3: UART0/I2C receive */ +#define DMA1TSEL_4 (0x0040) /* DMA channel 1 transfer select 4: UART0/I2C transmit */ +#define DMA1TSEL_5 (0x0050) /* DMA channel 1 transfer select 5: DAC12.0IFG */ +#define DMA1TSEL_6 (0x0060) /* DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA1TSEL_7 (0x0070) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA1TSEL_8 (0x0080) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA1TSEL_9 (0x0090) /* DMA channel 1 transfer select 9: UART1 receive */ +#define DMA1TSEL_10 (0x00A0) /* DMA channel 1 transfer select 10: UART1 transmit */ +#define DMA1TSEL_11 (0x00B0) /* DMA channel 1 transfer select 11: Multiplier ready */ +#define DMA1TSEL_14 (0x00E0) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */ +#define DMA1TSEL_15 (0x00F0) /* DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */ + +#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ */ +#define DMA2TSEL_1 (0x0100) /* DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */ +#define DMA2TSEL_2 (0x0200) /* DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */ +#define DMA2TSEL_3 (0x0300) /* DMA channel 2 transfer select 3: UART0/I2C receive */ +#define DMA2TSEL_4 (0x0400) /* DMA channel 2 transfer select 4: UART0/I2C transmit */ +#define DMA2TSEL_5 (0x0500) /* DMA channel 2 transfer select 5: DAC12.0IFG */ +#define DMA2TSEL_6 (0x0600) /* DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA2TSEL_7 (0x0700) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA2TSEL_8 (0x0800) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA2TSEL_9 (0x0900) /* DMA channel 2 transfer select 9: UART1 receive */ +#define DMA2TSEL_10 (0x0A00) /* DMA channel 2 transfer select 10: UART1 transmit */ +#define DMA2TSEL_11 (0x0B00) /* DMA channel 2 transfer select 11: Multiplier ready */ +#define DMA2TSEL_14 (0x0E00) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */ +#define DMA2TSEL_15 (0x0F00) /* DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */ + +sfr_w(DMACTL1); /* DMA Module Control 1 */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMAONFETCH (0x0004) /* DMA transfer on instruction fetch */ + +sfr_w(DMA0CTL); /* DMA Channel 0 Control */ +sfr_w(DMA1CTL); /* DMA Channel 1 Control */ +sfr_w(DMA2CTL); /* DMA Channel 2 Control */ + +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */ +#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */ +#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */ +#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0x0000) /* DMA transfer mode 0: single */ +#define DMADT_1 (0x1000) /* DMA transfer mode 1: block */ +#define DMADT_2 (0x2000) /* DMA transfer mode 2: interleaved */ +#define DMADT_3 (0x3000) /* DMA transfer mode 3: interleaved */ +#define DMADT_4 (0x4000) /* DMA transfer mode 4: single, repeat */ +#define DMADT_5 (0x5000) /* DMA transfer mode 5: block, repeat */ +#define DMADT_6 (0x6000) /* DMA transfer mode 6: interleaved, repeat */ +#define DMADT_7 (0x7000) /* DMA transfer mode 7: interleaved, repeat */ + +sfr_w(DMA0SA); /* DMA Channel 0 Source Address */ +sfr_w(DMA0DA); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0SZ); /* DMA Channel 0 Transfer Size */ +sfr_w(DMA1SA); /* DMA Channel 1 Source Address */ +sfr_w(DMA1DA); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1SZ); /* DMA Channel 1 Transfer Size */ +sfr_w(DMA2SA); /* DMA Channel 2 Source Address */ +sfr_w(DMA2DA); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2SZ); /* DMA Channel 2 Transfer Size */ + +/************************************************************ +* Interrupt Vectors (offset from 0xFFE0) +************************************************************/ + +#define DACDMA_VECTOR ( 1) /* 0xFFE0 DAC/DMA */ +#define PORT2_VECTOR ( 2) /* 0xFFE2 Port 2 */ +#define USART1TX_VECTOR ( 3) /* 0xFFE4 USART 1 Transmit */ +#define USART1RX_VECTOR ( 4) /* 0xFFE6 USART 1 Receive */ +#define PORT1_VECTOR ( 5) /* 0xFFE8 Port 1 */ +#define TIMERA1_VECTOR ( 6) /* 0xFFEA Timer A CC1-2, TA */ +#define TIMERA0_VECTOR ( 7) /* 0xFFEC Timer A CC0 */ +#define ADC12_VECTOR ( 8) /* 0xFFEE ADC */ +#define USART0TX_VECTOR ( 9) /* 0xFFF0 USART 0 Transmit */ +#define USART0RX_VECTOR (10) /* 0xFFF2 USART 0 Receive */ +#define WDT_VECTOR (11) /* 0xFFF4 Watchdog Timer */ +#define COMPARATORA_VECTOR (12) /* 0xFFF6 Comparator A */ +#define TIMERB1_VECTOR (13) /* 0xFFF8 Timer B CC1-6, TB */ +#define TIMERB0_VECTOR (14) /* 0xFFFA Timer B CC0 */ +#define NMI_VECTOR (15) /* 0xFFFC Non-maskable */ +#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ + + +/************************************************************ +* End of Modules +************************************************************/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* #ifndef __msp430x16x */ + diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611.ld b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611.ld new file mode 100644 index 0000000000..fdb3e93473 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611.ld @@ -0,0 +1,304 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430F1611 devices. */ +/* Version: 1.208 */ +/* Default linker script, for normal executables */ + +OUTPUT_ARCH(msp430) +ENTRY(_start) + +MEMORY { + SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ + RAM : ORIGIN = 0x1100, LENGTH = 0x2800 /* END=0x38FF, size 10240 */ + RAM_MIRROR : ORIGIN = 0x0200, LENGTH = 0x0800 + INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 2 128-byte segments */ + INFOA : ORIGIN = 0x1080, LENGTH = 0x0080 /* END=0x10FF, size 128 */ + INFOB : ORIGIN = 0x1000, LENGTH = 0x0080 /* END=0x107F, size 128 */ + ROM (rx) : ORIGIN = 0x4000, LENGTH = 0xBFE0 /* END=0xFFDF, size 49120 */ + VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002 + VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002 + VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002 + VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002 + VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002 + VECT6 : ORIGIN = 0xFFEA, LENGTH = 0x0002 + VECT7 : ORIGIN = 0xFFEC, LENGTH = 0x0002 + VECT8 : ORIGIN = 0xFFEE, LENGTH = 0x0002 + VECT9 : ORIGIN = 0xFFF0, LENGTH = 0x0002 + VECT10 : ORIGIN = 0xFFF2, LENGTH = 0x0002 + VECT11 : ORIGIN = 0xFFF4, LENGTH = 0x0002 + VECT12 : ORIGIN = 0xFFF6, LENGTH = 0x0002 + VECT13 : ORIGIN = 0xFFF8, LENGTH = 0x0002 + VECT14 : ORIGIN = 0xFFFA, LENGTH = 0x0002 + VECT15 : ORIGIN = 0xFFFC, LENGTH = 0x0002 + RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 +} + +SECTIONS +{ + __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) KEEP (*(__interrupt_vector_dacdma)) } > VECT1 + __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) KEEP (*(__interrupt_vector_port2)) } > VECT2 + __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_usart1tx)) } > VECT3 + __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_usart1rx)) } > VECT4 + __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) KEEP (*(__interrupt_vector_port1)) } > VECT5 + __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_timera1)) } > VECT6 + __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) KEEP (*(__interrupt_vector_timera0)) } > VECT7 + __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) KEEP (*(__interrupt_vector_adc12)) } > VECT8 + __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_usart0tx)) } > VECT9 + __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_usart0rx)) } > VECT10 + __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_wdt)) } > VECT11 + __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) KEEP (*(__interrupt_vector_comparatora)) } > VECT12 + __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) KEEP (*(__interrupt_vector_timerb1)) } > VECT13 + __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) KEEP (*(__interrupt_vector_timerb0)) } > VECT14 + __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_nmi)) } > VECT15 + __reset_vector : + { + KEEP (*(__interrupt_vector_16)) + KEEP (*(__interrupt_vector_reset)) + KEEP (*(.resetvec)) + } > RESETVEC + + .rodata : + { + . = ALIGN(2); + *(.plt) + *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) + *(.rodata1) + KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) + } > ROM + + /* Note: This is a separate .rodata section for sections which are + read only but which older linkers treat as read-write. + This prevents older linkers from marking the entire .rodata + section as read-write. */ + .rodata2 : + { + . = ALIGN(2); + PROVIDE (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + . = ALIGN(2); + PROVIDE (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE (__init_array_end = .); + . = ALIGN(2); + PROVIDE (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE (__fini_array_end = .); + . = ALIGN(2); + *(.eh_frame_hdr) + KEEP (*(.eh_frame)) + + /* gcc uses crtbegin.o to find the start of the constructors, so + we make sure it is first. Because this is a wildcard, it + doesn't matter if the user does not actually link against + crtbegin.o; the linker won't look for a file to match a + wildcard. The wildcard also means that it doesn't matter which + directory crtbegin.o is in. */ + KEEP (*crtbegin*.o(.ctors)) + + /* We don't want to include the .ctor section from from the + crtend.o file until after the sorted ctors. The .ctor section + from the crtend file contains the end of ctors marker and it + must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > ROM + + .text : + { + . = ALIGN(2); + PROVIDE (_start = .); + KEEP (*(SORT(.crt_*))) + *(.lowtext .text .stub .text.* .gnu.linkonce.t.* .text:*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.interp .hash .dynsym .dynstr .gnu.version*) + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + . = ALIGN(2); + KEEP (*(.init)) + KEEP (*(.fini)) + KEEP (*(.tm_clone_table)) + } > ROM + + .data : + { + . = ALIGN(2); + PROVIDE (__datastart = .); + + KEEP (*(.jcr)) + *(.data.rel.ro.local) *(.data.rel.ro*) + *(.dynamic) + + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + *(.data1) + *(.got.plt) *(.got) + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + . = ALIGN(2); + *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) + + . = ALIGN(2); + _edata = .; + PROVIDE (edata = .); + PROVIDE (__dataend = .); + } > RAM AT>ROM + + /* Note that crt0 assumes this is a multiple of two; all the + start/stop symbols are also assumed word-aligned. */ + PROVIDE(__romdatastart = LOADADDR(.data)); + PROVIDE (__romdatacopysize = SIZEOF(.data)); + + .bss : + { + . = ALIGN(2); + PROVIDE (__bssstart = .); + *(.dynbss) + *(.sbss .sbss.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(2); + *(COMMON) + PROVIDE (__bssend = .); + } > RAM + PROVIDE (__bsssize = SIZEOF(.bss)); + + /* This section contains data that is not initialised during load + or application reset. */ + .noinit (NOLOAD) : + { + . = ALIGN(2); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(2); + PROVIDE (__noinit_end = .); + end = .; + } > RAM + + /* We create this section so that "end" will always be in the + RAM region (matching .stack below), even if the .bss + section is empty. */ + .heap (NOLOAD) : + { + . = ALIGN(2); + __heap_start__ = .; + _end = __heap_start__; + PROVIDE (end = .); + KEEP (*(.heap)) + _end = .; + PROVIDE (end = .); + /* This word is here so that the section is not empty, and thus + not discarded by the linker. The actual value does not matter + and is ignored. */ + LONG(0); + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > RAM + /* WARNING: Do not place anything in RAM here. + The heap section must be the last section in RAM and the stack + section must be placed at the very end of the RAM region. */ + + .stack (ORIGIN (RAM) + LENGTH(RAM)) : + { + PROVIDE (__stack = .); + *(.stack) + } + + .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */ + .infoB : {} > INFOB + + .MSP430.attributes 0 : + { + KEEP (*(.MSP430.attributes)) + KEEP (*(.gnu.attributes)) + KEEP (*(__TI_build_attributes)) + } + + /* The rest are all not normally part of the runtime image. */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /DISCARD/ : { *(.note.GNU-stack) } +} + + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +INCLUDE msp430f1611_symbols.ld + diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611_symbols.ld b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611_symbols.ld new file mode 100644 index 0000000000..19823ffed5 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611_symbols.ld @@ -0,0 +1,272 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430F1611 devices. */ +/* Version: 1.208 */ + +/************************************************************ +* STANDARD BITS +************************************************************/ +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ +/************************************************************ +* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS +************************************************************/ +PROVIDE(IE1 = 0x0000); +PROVIDE(IFG1 = 0x0002); +PROVIDE(ME1 = 0x0004); +PROVIDE(IE2 = 0x0001); +PROVIDE(IFG2 = 0x0003); +PROVIDE(ME2 = 0x0005); +/************************************************************ +* WATCHDOG TIMER +************************************************************/ +PROVIDE(WDTCTL = 0x0120); +/************************************************************ +* HARDWARE MULTIPLIER +************************************************************/ +PROVIDE(MPY = 0x0130); +PROVIDE(MPYS = 0x0132); +PROVIDE(MAC = 0x0134); +PROVIDE(MACS = 0x0136); +PROVIDE(OP2 = 0x0138); +PROVIDE(RESLO = 0x013A); +PROVIDE(RESHI = 0x013C); +PROVIDE(SUMEXT = 0x013E); +/************************************************************ +* DIGITAL I/O Port1/2 +************************************************************/ +PROVIDE(P1IN = 0x0020); +PROVIDE(P1OUT = 0x0021); +PROVIDE(P1DIR = 0x0022); +PROVIDE(P1IFG = 0x0023); +PROVIDE(P1IES = 0x0024); +PROVIDE(P1IE = 0x0025); +PROVIDE(P1SEL = 0x0026); +PROVIDE(P2IN = 0x0028); +PROVIDE(P2OUT = 0x0029); +PROVIDE(P2DIR = 0x002A); +PROVIDE(P2IFG = 0x002B); +PROVIDE(P2IES = 0x002C); +PROVIDE(P2IE = 0x002D); +PROVIDE(P2SEL = 0x002E); +/************************************************************ +* DIGITAL I/O Port3/4 +************************************************************/ +PROVIDE(P3IN = 0x0018); +PROVIDE(P3OUT = 0x0019); +PROVIDE(P3DIR = 0x001A); +PROVIDE(P3SEL = 0x001B); +PROVIDE(P4IN = 0x001C); +PROVIDE(P4OUT = 0x001D); +PROVIDE(P4DIR = 0x001E); +PROVIDE(P4SEL = 0x001F); +/************************************************************ +* DIGITAL I/O Port5/6 +************************************************************/ +PROVIDE(P5IN = 0x0030); +PROVIDE(P5OUT = 0x0031); +PROVIDE(P5DIR = 0x0032); +PROVIDE(P5SEL = 0x0033); +PROVIDE(P6IN = 0x0034); +PROVIDE(P6OUT = 0x0035); +PROVIDE(P6DIR = 0x0036); +PROVIDE(P6SEL = 0x0037); +/************************************************************ +* USART +************************************************************/ +/************************************************************ +* USART 0 +************************************************************/ +PROVIDE(U0CTL = 0x0070); +PROVIDE(U0TCTL = 0x0071); +PROVIDE(U0RCTL = 0x0072); +PROVIDE(U0MCTL = 0x0073); +PROVIDE(U0BR0 = 0x0074); +PROVIDE(U0BR1 = 0x0075); +PROVIDE(U0RXBUF = 0x0076); +PROVIDE(U0TXBUF = 0x0077); +/************************************************************ +* USART 1 +************************************************************/ +PROVIDE(U1CTL = 0x0078); +PROVIDE(U1TCTL = 0x0079); +PROVIDE(U1RCTL = 0x007A); +PROVIDE(U1MCTL = 0x007B); +PROVIDE(U1BR0 = 0x007C); +PROVIDE(U1BR1 = 0x007D); +PROVIDE(U1RXBUF = 0x007E); +PROVIDE(U1TXBUF = 0x007F); +/************************************************************ +* USART0 I2C +************************************************************/ +PROVIDE(I2CIE = 0x0050); +PROVIDE(I2CIFG = 0x0051); +PROVIDE(I2CNDAT = 0x0052); +PROVIDE(I2CTCTL = 0x0071); +PROVIDE(I2CDCTL = 0x0072); +PROVIDE(I2CPSC = 0x0073); +PROVIDE(I2CSCLH = 0x0074); +PROVIDE(I2CSCLL = 0x0075); +PROVIDE(I2CDRB = 0x0076); +PROVIDE(I2CDRW = 0x0076); +PROVIDE(I2COA = 0x0118); +PROVIDE(I2CSA = 0x011A); +PROVIDE(I2CIV = 0x011C); +/************************************************************ +* Timer A3 +************************************************************/ +PROVIDE(TAIV = 0x012E); +PROVIDE(TACTL = 0x0160); +PROVIDE(TACCTL0 = 0x0162); +PROVIDE(TACCTL1 = 0x0164); +PROVIDE(TACCTL2 = 0x0166); +PROVIDE(TAR = 0x0170); +PROVIDE(TACCR0 = 0x0172); +PROVIDE(TACCR1 = 0x0174); +PROVIDE(TACCR2 = 0x0176); +/************************************************************ +* Timer B7 +************************************************************/ +PROVIDE(TBIV = 0x011E); +PROVIDE(TBCTL = 0x0180); +PROVIDE(TBCCTL0 = 0x0182); +PROVIDE(TBCCTL1 = 0x0184); +PROVIDE(TBCCTL2 = 0x0186); +PROVIDE(TBCCTL3 = 0x0188); +PROVIDE(TBCCTL4 = 0x018A); +PROVIDE(TBCCTL5 = 0x018C); +PROVIDE(TBCCTL6 = 0x018E); +PROVIDE(TBR = 0x0190); +PROVIDE(TBCCR0 = 0x0192); +PROVIDE(TBCCR1 = 0x0194); +PROVIDE(TBCCR2 = 0x0196); +PROVIDE(TBCCR3 = 0x0198); +PROVIDE(TBCCR4 = 0x019A); +PROVIDE(TBCCR5 = 0x019C); +PROVIDE(TBCCR6 = 0x019E); +/************************************************************ +* Basic Clock Module +************************************************************/ +PROVIDE(DCOCTL = 0x0056); +PROVIDE(BCSCTL1 = 0x0057); +PROVIDE(BCSCTL2 = 0x0058); +/************************************************************ +* Brown-Out, Supply Voltage Supervision (SVS) +************************************************************/ +PROVIDE(SVSCTL = 0x0055); +/************************************************************* +* Flash Memory +*************************************************************/ +PROVIDE(FCTL1 = 0x0128); +PROVIDE(FCTL2 = 0x012A); +PROVIDE(FCTL3 = 0x012C); +/************************************************************ +* Comparator A +************************************************************/ +PROVIDE(CACTL1 = 0x0059); +PROVIDE(CACTL2 = 0x005A); +PROVIDE(CAPD = 0x005B); +/************************************************************ +* ADC12 +************************************************************/ +PROVIDE(ADC12CTL0 = 0x01A0); +PROVIDE(ADC12CTL1 = 0x01A2); +PROVIDE(ADC12IFG = 0x01A4); +PROVIDE(ADC12IE = 0x01A6); +PROVIDE(ADC12IV = 0x01A8); +PROVIDE(ADC12MEM0 = 0x0140); +PROVIDE(ADC12MEM1 = 0x0142); +PROVIDE(ADC12MEM2 = 0x0144); +PROVIDE(ADC12MEM3 = 0x0146); +PROVIDE(ADC12MEM4 = 0x0148); +PROVIDE(ADC12MEM5 = 0x014A); +PROVIDE(ADC12MEM6 = 0x014C); +PROVIDE(ADC12MEM7 = 0x014E); +PROVIDE(ADC12MEM8 = 0x0150); +PROVIDE(ADC12MEM9 = 0x0152); +PROVIDE(ADC12MEM10 = 0x0154); +PROVIDE(ADC12MEM11 = 0x0156); +PROVIDE(ADC12MEM12 = 0x0158); +PROVIDE(ADC12MEM13 = 0x015A); +PROVIDE(ADC12MEM14 = 0x015C); +PROVIDE(ADC12MEM15 = 0x015E); +PROVIDE(ADC12MCTL0 = 0x0080); +PROVIDE(ADC12MCTL1 = 0x0081); +PROVIDE(ADC12MCTL2 = 0x0082); +PROVIDE(ADC12MCTL3 = 0x0083); +PROVIDE(ADC12MCTL4 = 0x0084); +PROVIDE(ADC12MCTL5 = 0x0085); +PROVIDE(ADC12MCTL6 = 0x0086); +PROVIDE(ADC12MCTL7 = 0x0087); +PROVIDE(ADC12MCTL8 = 0x0088); +PROVIDE(ADC12MCTL9 = 0x0089); +PROVIDE(ADC12MCTL10 = 0x008A); +PROVIDE(ADC12MCTL11 = 0x008B); +PROVIDE(ADC12MCTL12 = 0x008C); +PROVIDE(ADC12MCTL13 = 0x008D); +PROVIDE(ADC12MCTL14 = 0x008E); +PROVIDE(ADC12MCTL15 = 0x008F); +/************************************************************ +* DAC12 +************************************************************/ +PROVIDE(DAC12_0CTL = 0x01C0); +PROVIDE(DAC12_1CTL = 0x01C2); +PROVIDE(DAC12_0DAT = 0x01C8); +PROVIDE(DAC12_1DAT = 0x01CA); +/************************************************************ +* DMA +************************************************************/ +PROVIDE(DMACTL0 = 0x0122); +PROVIDE(DMACTL1 = 0x0124); +PROVIDE(DMA0CTL = 0x01E0); +PROVIDE(DMA1CTL = 0x01E8); +PROVIDE(DMA2CTL = 0x01F0); +PROVIDE(DMA0SA = 0x01E2); +PROVIDE(DMA0DA = 0x01E4); +PROVIDE(DMA0SZ = 0x01E6); +PROVIDE(DMA1SA = 0x01EA); +PROVIDE(DMA1DA = 0x01EC); +PROVIDE(DMA1SZ = 0x01EE); +PROVIDE(DMA2SA = 0x01F2); +PROVIDE(DMA2DA = 0x01F4); +PROVIDE(DMA2SZ = 0x01F6); +/************************************************************ +* Interrupt Vectors (offset from 0xFFE0) +************************************************************/ +/************************************************************ +* End of Modules +************************************************************/ diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1612.h b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1612.h new file mode 100644 index 0000000000..dc50dff4b2 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1612.h @@ -0,0 +1,1361 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430x16x devices. +* +* Texas Instruments, Version 2.7 +* +* Rev. 2.0, Fixed definitions for DMA +* Rev. 2.1, Alignment of defintions in Users Guide and of version numbers +* Rev. 2.2, Fixed definitions for I2C +* Rev. 2.21,Fixed definitions for I2C for assembler +* Rev. 2.3, Fixed type in ADC12 bit definitions (replaced ADC10 with ADC12) +* Added SVS +* Added DMA request definitions +* Rev. 2.4, Removed unused def of TASSEL2 / TBSSEL2 +* Rev. 2.5, Added VLD bits in SVS module +* Rev. 2.6, Fixed incorrect bits in I2C STT (wrong:SST) and I2C prefix was missing at some bits +* Rev. 2.7, added definitions for Interrupt Vectors xxIV +* +********************************************************************/ + +#ifndef __msp430x16x +#define __msp430x16x + +#define __MSP430_HEADER_VERSION__ 1208 + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------*/ +/* PERIPHERAL FILE MAP */ +/*----------------------------------------------------------------------------*/ + +#define __MSP430_TI_HEADERS__ + +#include + + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __STDC__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" + +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif /* End #defines for C */ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + +/************************************************************ +* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS +************************************************************/ + +sfr_b(IE1); /* Interrupt Enable 1 */ +#define U0IE IE1 /* UART0 Interrupt Enable Register */ +#define WDTIE (0x01) +#define OFIE (0x02) +#define NMIIE (0x10) +#define ACCVIE (0x20) +#define URXIE0 (0x40) +#define UTXIE0 (0x80) + +sfr_b(IFG1); /* Interrupt Flag 1 */ +#define U0IFG IFG1 /* UART0 Interrupt Flag Register */ +#define WDTIFG (0x01) +#define OFIFG (0x02) +#define NMIIFG (0x10) +#define URXIFG0 (0x40) +#define UTXIFG0 (0x80) + +sfr_b(ME1); /* Module Enable 1 */ +#define U0ME ME1 /* UART0 Module Enable Register */ +#define URXE0 (0x40) +#define UTXE0 (0x80) +#define USPIE0 (0x40) + +sfr_b(IE2); /* Interrupt Enable 2 */ +#define U1IE IE2 /* UART1 Interrupt Enable Register */ +#define URXIE1 (0x10) +#define UTXIE1 (0x20) + +sfr_b(IFG2); /* Interrupt Flag 2 */ +#define U1IFG IFG2 /* UART1 Interrupt Flag Register */ +#define URXIFG1 (0x10) +#define UTXIFG1 (0x20) + +sfr_b(ME2); /* Module Enable 2 */ +#define U1ME ME2 /* UART1 Module Enable Register */ +#define URXE1 (0x10) +#define UTXE1 (0x20) +#define USPIE1 (0x10) + +/************************************************************ +* WATCHDOG TIMER +************************************************************/ +#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */ + +sfr_w(WDTCTL); /* Watchdog Timer Control */ +/* The bit names have been prefixed with "WDT" */ +#define WDTIS0 (0x0001) +#define WDTIS1 (0x0002) +#define WDTSSEL (0x0004) +#define WDTCNTCL (0x0008) +#define WDTTMSEL (0x0010) +#define WDTNMI (0x0020) +#define WDTNMIES (0x0040) +#define WDTHOLD (0x0080) + +#define WDTPW (0x5A00) + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ + +/* INTERRUPT CONTROL */ +/* These two bits are defined in the Special Function Registers */ +/* #define WDTIE 0x01 */ +/* #define WDTIFG 0x01 */ + +/************************************************************ +* HARDWARE MULTIPLIER +************************************************************/ +#define __MSP430_HAS_MPY__ /* Definition to show that Module is available */ + +sfr_w(MPY); /* Multiply Unsigned/Operand 1 */ +sfr_w(MPYS); /* Multiply Signed/Operand 1 */ +sfr_w(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */ +sfr_w(MACS); /* Multiply Signed and Accumulate/Operand 1 */ +sfr_w(OP2); /* Operand 2 */ +sfr_w(RESLO); /* Result Low Word */ +sfr_w(RESHI); /* Result High Word */ +sfr_w(SUMEXT); /* Sum Extend */ + +/************************************************************ +* DIGITAL I/O Port1/2 +************************************************************/ +#define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P1SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P2SEL__ /* Define for DriverLib */ + +sfr_b(P1IN); /* Port 1 Input */ +sfr_b(P1OUT); /* Port 1 Output */ +sfr_b(P1DIR); /* Port 1 Direction */ +sfr_b(P1IFG); /* Port 1 Interrupt Flag */ +sfr_b(P1IES); /* Port 1 Interrupt Edge Select */ +sfr_b(P1IE); /* Port 1 Interrupt Enable */ +sfr_b(P1SEL); /* Port 1 Selection */ + +sfr_b(P2IN); /* Port 2 Input */ +sfr_b(P2OUT); /* Port 2 Output */ +sfr_b(P2DIR); /* Port 2 Direction */ +sfr_b(P2IFG); /* Port 2 Interrupt Flag */ +sfr_b(P2IES); /* Port 2 Interrupt Edge Select */ +sfr_b(P2IE); /* Port 2 Interrupt Enable */ +sfr_b(P2SEL); /* Port 2 Selection */ + +/************************************************************ +* DIGITAL I/O Port3/4 +************************************************************/ +#define __MSP430_HAS_PORT3__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT4__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P3SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P4SEL__ /* Define for DriverLib */ + +sfr_b(P3IN); /* Port 3 Input */ +sfr_b(P3OUT); /* Port 3 Output */ +sfr_b(P3DIR); /* Port 3 Direction */ +sfr_b(P3SEL); /* Port 3 Selection */ + +sfr_b(P4IN); /* Port 4 Input */ +sfr_b(P4OUT); /* Port 4 Output */ +sfr_b(P4DIR); /* Port 4 Direction */ +sfr_b(P4SEL); /* Port 4 Selection */ + +/************************************************************ +* DIGITAL I/O Port5/6 +************************************************************/ +#define __MSP430_HAS_PORT5__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT6__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P5SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P6SEL__ /* Define for DriverLib */ + +sfr_b(P5IN); /* Port 5 Input */ +sfr_b(P5OUT); /* Port 5 Output */ +sfr_b(P5DIR); /* Port 5 Direction */ +sfr_b(P5SEL); /* Port 5 Selection */ + +sfr_b(P6IN); /* Port 6 Input */ +sfr_b(P6OUT); /* Port 6 Output */ +sfr_b(P6DIR); /* Port 6 Direction */ +sfr_b(P6SEL); /* Port 6 Selection */ + +/************************************************************ +* USART +************************************************************/ + +/* UxCTL */ +#define PENA (0x80) /* Parity enable */ +#define PEV (0x40) /* Parity 0:odd / 1:even */ +#define SPB (0x20) /* Stop Bits 0:one / 1: two */ +#define CHAR (0x10) /* Data 0:7-bits / 1:8-bits */ +#define LISTEN (0x08) /* Listen mode */ +#define SYNC (0x04) /* UART / SPI mode */ +#define MM (0x02) /* Master Mode off/on */ +#define SWRST (0x01) /* USART Software Reset */ + +/* UxTCTL */ +#define CKPH (0x80) /* SPI: Clock Phase */ +#define CKPL (0x40) /* Clock Polarity */ +#define SSEL1 (0x20) /* Clock Source Select 1 */ +#define SSEL0 (0x10) /* Clock Source Select 0 */ +#define URXSE (0x08) /* Receive Start edge select */ +#define TXWAKE (0x04) /* TX Wake up mode */ +#define STC (0x02) /* SPI: STC enable 0:on / 1:off */ +#define TXEPT (0x01) /* TX Buffer empty */ + +/* UxRCTL */ +#define FE (0x80) /* Frame Error */ +#define PE (0x40) /* Parity Error */ +#define OE (0x20) /* Overrun Error */ +#define BRK (0x10) /* Break detected */ +#define URXEIE (0x08) /* RX Error interrupt enable */ +#define URXWIE (0x04) /* RX Wake up interrupt enable */ +#define RXWAKE (0x02) /* RX Wake up detect */ +#define RXERR (0x01) /* RX Error Error */ + +/************************************************************ +* USART 0 +************************************************************/ +#define __MSP430_HAS_UART0__ /* Definition to show that Module is available */ + +sfr_b(U0CTL); /* USART 0 Control */ +sfr_b(U0TCTL); /* USART 0 Transmit Control */ +sfr_b(U0RCTL); /* USART 0 Receive Control */ +sfr_b(U0MCTL); /* USART 0 Modulation Control */ +sfr_b(U0BR0); /* USART 0 Baud Rate 0 */ +sfr_b(U0BR1); /* USART 0 Baud Rate 1 */ +sfr_b(U0RXBUF); /* USART 0 Receive Buffer */ +sfr_b(U0TXBUF); /* USART 0 Transmit Buffer */ + +/* Alternate register names */ + +#define UCTL0 U0CTL /* USART 0 Control */ +#define UTCTL0 U0TCTL /* USART 0 Transmit Control */ +#define URCTL0 U0RCTL /* USART 0 Receive Control */ +#define UMCTL0 U0MCTL /* USART 0 Modulation Control */ +#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */ +#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */ +#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */ +#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */ +#define UCTL0_ U0CTL_ /* USART 0 Control */ +#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */ +#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */ +#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */ +#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */ +#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */ +#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */ +#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */ +#define UCTL_0 U0CTL /* USART 0 Control */ +#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */ +#define URCTL_0 U0RCTL /* USART 0 Receive Control */ +#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */ +#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */ +#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */ +#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */ +#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */ +#define UCTL_0_ U0CTL_ /* USART 0 Control */ +#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */ +#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */ +#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */ +#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */ +#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */ +#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */ +#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */ + +/************************************************************ +* USART 1 +************************************************************/ +#define __MSP430_HAS_UART1__ /* Definition to show that Module is available */ + +sfr_b(U1CTL); /* USART 1 Control */ +sfr_b(U1TCTL); /* USART 1 Transmit Control */ +sfr_b(U1RCTL); /* USART 1 Receive Control */ +sfr_b(U1MCTL); /* USART 1 Modulation Control */ +sfr_b(U1BR0); /* USART 1 Baud Rate 0 */ +sfr_b(U1BR1); /* USART 1 Baud Rate 1 */ +sfr_b(U1RXBUF); /* USART 1 Receive Buffer */ +sfr_b(U1TXBUF); /* USART 1 Transmit Buffer */ + +/* Alternate register names */ + +#define UCTL1 U1CTL /* USART 1 Control */ +#define UTCTL1 U1TCTL /* USART 1 Transmit Control */ +#define URCTL1 U1RCTL /* USART 1 Receive Control */ +#define UMCTL1 U1MCTL /* USART 1 Modulation Control */ +#define UBR01 U1BR0 /* USART 1 Baud Rate 0 */ +#define UBR11 U1BR1 /* USART 1 Baud Rate 1 */ +#define RXBUF1 U1RXBUF /* USART 1 Receive Buffer */ +#define TXBUF1 U1TXBUF /* USART 1 Transmit Buffer */ +#define UCTL1_ U1CTL_ /* USART 1 Control */ +#define UTCTL1_ U1TCTL_ /* USART 1 Transmit Control */ +#define URCTL1_ U1RCTL_ /* USART 1 Receive Control */ +#define UMCTL1_ U1MCTL_ /* USART 1 Modulation Control */ +#define UBR01_ U1BR0_ /* USART 1 Baud Rate 0 */ +#define UBR11_ U1BR1_ /* USART 1 Baud Rate 1 */ +#define RXBUF1_ U1RXBUF_ /* USART 1 Receive Buffer */ +#define TXBUF1_ U1TXBUF_ /* USART 1 Transmit Buffer */ +#define UCTL_1 U1CTL /* USART 1 Control */ +#define UTCTL_1 U1TCTL /* USART 1 Transmit Control */ +#define URCTL_1 U1RCTL /* USART 1 Receive Control */ +#define UMCTL_1 U1MCTL /* USART 1 Modulation Control */ +#define UBR0_1 U1BR0 /* USART 1 Baud Rate 0 */ +#define UBR1_1 U1BR1 /* USART 1 Baud Rate 1 */ +#define RXBUF_1 U1RXBUF /* USART 1 Receive Buffer */ +#define TXBUF_1 U1TXBUF /* USART 1 Transmit Buffer */ +#define UCTL_1_ U1CTL_ /* USART 1 Control */ +#define UTCTL_1_ U1TCTL_ /* USART 1 Transmit Control */ +#define URCTL_1_ U1RCTL_ /* USART 1 Receive Control */ +#define UMCTL_1_ U1MCTL_ /* USART 1 Modulation Control */ +#define UBR0_1_ U1BR0_ /* USART 1 Baud Rate 0 */ +#define UBR1_1_ U1BR1_ /* USART 1 Baud Rate 1 */ +#define RXBUF_1_ U1RXBUF_ /* USART 1 Receive Buffer */ +#define TXBUF_1_ U1TXBUF_ /* USART 1 Transmit Buffer */ + +/************************************************************ +* USART0 I2C +************************************************************/ +#define __MSP430_HAS_I2C__ /* Definition to show that Module is available */ + +sfr_b(I2CIE); /* I2C Interrupt Enable */ +#define ALIE (0x01) /* Arbitration lost */ +#define NACKIE (0x02) /* No acknowledge */ +#define OAIE (0x04) /* Own address */ +#define ARDYIE (0x08) /* Access ready (opeation complete) */ +#define RXRDYIE (0x10) /* Receive ready (data received) */ +#define TXRDYIE (0x20) /* Transmit ready (transmit register empty) */ +#define GCIE (0x40) /* General call */ +#define STTIE (0x80) /* Start condition */ + +sfr_b(I2CIFG); /* I2C Interrupt Flag */ +#define ALIFG (0x01) /* Arbitration lost */ +#define NACKIFG (0x02) /* No acknowledge */ +#define OAIFG (0x04) /* Own address */ +#define ARDYIFG (0x08) /* Access ready (opeation complete) */ +#define RXRDYIFG (0x10) /* Receive ready (data received) */ +#define TXRDYIFG (0x20) /* Transmit ready (transmit register empty) */ +#define GCIFG (0x40) /* General call */ +#define STTIFG (0x80) /* Start condition */ + +sfr_b(I2CNDAT); /* I2C Data Count */ + +/* USART 0 Control */ +#define I2CEN (0x01) /* I2C enable */ +#define MST (0x02) /* I2C master */ +#define XA (0x10) /* I2C extended addressing */ +#define I2C (0x20) /* USART I2C */ +#define TXDMAEN (0x40) /* Transmit DMA enable */ +#define RXDMAEN (0x80) /* Receive DMA enable */ + +sfr_b(I2CTCTL); /* I2C Transfer Control */ +#define I2CSTT (0x01) /* Start bit */ +#define I2CSTP (0x02) /* Stop bit */ +#define I2CSTB (0x04) /* Start byte mode */ +#define I2CTRX (0x08) /* Transmit */ +#define I2CSSEL0 (0x10) /* Clock select bit 0 */ +#define I2CSSEL1 (0x20) /* Clock select bit 1 */ +#define I2CRM (0x40) /* Repeat mode */ +#define I2CWORD (0x80) /* Word data mode */ + +#define I2CSSEL_0 (0x0000) /* I2C clock select 0: UCLK */ +#define I2CSSEL_1 (0x0010) /* I2C clock select 1: ACLK */ +#define I2CSSEL_2 (0x0020) /* I2C clock select 2: SMCLK */ +#define I2CSSEL_3 (0x0030) /* I2C clock select 3: SMCLK */ + +#define I2CMM_0 (0x00) /* Master mode 0 */ +#define I2CMM_1 (I2CSTT) /* Master mode 1 */ +#define I2CMM_2 (I2CSTP+I2CSTT) /* Master mode 2 */ +#define I2CMM_3 (I2CRM+I2CSTT) /* Master mode 3 */ +#define I2CMM_4 (I2CSTP) /* Master mode 4 */ + +sfr_b(I2CDCTL); /* I2C Data Control */ +#define I2CBB (0x01) /* Bus busy */ +#define I2CRXOVR (0x02) /* Receiver overrun */ +#define I2CTXUDF (0x04) /* Transmit underflow */ +#define I2CSBD (0x08) /* Received byte */ +#define I2CSCLLOW (0x10) /* SCL being held low */ +#define I2CBUSY (0x20) /* I2C Busy Flag */ + +sfr_b(I2CPSC); /* I2C Pre-scaler */ +sfr_b(I2CSCLH); /* I2C SCL High */ +sfr_b(I2CSCLL); /* I2C SCL Low */ +sfr_b(I2CDRB); /* I2C Data for Byte access */ +sfr_w(I2CDRW); /* I2C Data for Word access */ + +sfr_w(I2COA); /* I2C Own Address */ +sfr_w(I2CSA); /* I2C Slave Address */ + +sfr_w(I2CIV); /* I2C Interrupt Vector */ +#define I2CIV_NONE (0x0000) /* I2C interrupt vector: No interrupt pending */ +#define I2CIV_AL (0x0002) /* I2C interrupt vector: Arbitration lost (ALIFG) */ +#define I2CIV_NACK (0x0004) /* I2C interrupt vector: No acknowledge (NACKIFG) */ +#define I2CIV_OA (0x0006) /* I2C interrupt vector: Own address (OAIFG) */ +#define I2CIV_ARDY (0x0008) /* I2C interrupt vector: Access ready (ARDYIFG) */ +#define I2CIV_RXRDY (0x000A) /* I2C interrupt vector: Receive ready (RXRDYIFG) */ +#define I2CIV_TXRDY (0x000C) /* I2C interrupt vector: Transmit ready (TXRDYIFG) */ +#define I2CIV_GC (0x000E) /* I2C interrupt vector: General call (GCIFG) */ +#define I2CIV_STT (0x0010) /* I2C interrupt vector: Start condition (STTIFG) */ + +/************************************************************ +* Timer A3 +************************************************************/ +#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */ + +sfr_w(TAIV); /* Timer A Interrupt Vector Word */ +sfr_w(TACTL); /* Timer A Control */ +sfr_w(TACCTL0); /* Timer A Capture/Compare Control 0 */ +sfr_w(TACCTL1); /* Timer A Capture/Compare Control 1 */ +sfr_w(TACCTL2); /* Timer A Capture/Compare Control 2 */ +sfr_w(TAR); /* Timer A Counter Register */ +sfr_w(TACCR0); /* Timer A Capture/Compare 0 */ +sfr_w(TACCR1); /* Timer A Capture/Compare 1 */ +sfr_w(TACCR2); /* Timer A Capture/Compare 2 */ + +/* Alternate register names */ +#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ +#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ +#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ +#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */ +#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */ +#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */ +#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ +#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ +#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ +#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ +#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ +#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ +/* Alternate register names - 5xx style */ +#define TA0IV TAIV /* Timer A Interrupt Vector Word */ +#define TA0CTL TACTL /* Timer A Control */ +#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ +#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ +#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ +#define TA0R TAR /* Timer A Counter Register */ +#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */ +#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */ +#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */ +#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */ +#define TA0CTL_ TACTL_ /* Timer A Control */ +#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ +#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ +#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ +#define TA0R_ TAR_ /* Timer A Counter Register */ +#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ +#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ +#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ +#define TIMER0_A1_VECTOR TIMERA1_VECTOR /* Int. Vector: Timer A CC1-2, TA */ +#define TIMER0_A0_VECTOR TIMERA0_VECTOR /* Int. Vector: Timer A CC0 */ + +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (0x0020) /* Timer A mode control: 2 - Continous up */ +#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ + +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ +#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ +#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ +#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ +#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ +#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ + +/* TA3IV Definitions */ +#define TAIV_NONE (0x0000) /* No Interrupt pending */ +#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */ +#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */ +#define TAIV_6 (0x0006) /* Reserved */ +#define TAIV_8 (0x0008) /* Reserved */ +#define TAIV_TAIFG (0x000A) /* TAIFG */ + +/* Alternate register names - 5xx style */ +#define TA0IV_NONE (0x0000) /* No Interrupt pending */ +#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_6 (0x0006) /* Reserved */ +#define TA0IV_8 (0x0008) /* Reserved */ +#define TA0IV_TAIFG (0x000A) /* TA0IFG */ + +/************************************************************ +* Timer B7 +************************************************************/ +#define __MSP430_HAS_TB7__ /* Definition to show that Module is available */ + +sfr_w(TBIV); /* Timer B Interrupt Vector Word */ +sfr_w(TBCTL); /* Timer B Control */ +sfr_w(TBCCTL0); /* Timer B Capture/Compare Control 0 */ +sfr_w(TBCCTL1); /* Timer B Capture/Compare Control 1 */ +sfr_w(TBCCTL2); /* Timer B Capture/Compare Control 2 */ +sfr_w(TBCCTL3); /* Timer B Capture/Compare Control 3 */ +sfr_w(TBCCTL4); /* Timer B Capture/Compare Control 4 */ +sfr_w(TBCCTL5); /* Timer B Capture/Compare Control 5 */ +sfr_w(TBCCTL6); /* Timer B Capture/Compare Control 6 */ +sfr_w(TBR); /* Timer B Counter Register */ +sfr_w(TBCCR0); /* Timer B Capture/Compare 0 */ +sfr_w(TBCCR1); /* Timer B Capture/Compare 1 */ +sfr_w(TBCCR2); /* Timer B Capture/Compare 2 */ +sfr_w(TBCCR3); /* Timer B Capture/Compare 3 */ +sfr_w(TBCCR4); /* Timer B Capture/Compare 4 */ +sfr_w(TBCCR5); /* Timer B Capture/Compare 5 */ +sfr_w(TBCCR6); /* Timer B Capture/Compare 6 */ + +/* Alternate register names - 5xx style */ +#define TB0IV TBIV /* Timer B Interrupt Vector Word */ +#define TB0CTL TBCTL /* Timer B Control */ +#define TB0CCTL0 TBCCTL0 /* Timer B Capture/Compare Control 0 */ +#define TB0CCTL1 TBCCTL1 /* Timer B Capture/Compare Control 1 */ +#define TB0CCTL2 TBCCTL2 /* Timer B Capture/Compare Control 2 */ +#define TB0CCTL3 TBCCTL3 /* Timer B Capture/Compare Control 3 */ +#define TB0CCTL4 TBCCTL4 /* Timer B Capture/Compare Control 4 */ +#define TB0CCTL5 TBCCTL5 /* Timer B Capture/Compare Control 5 */ +#define TB0CCTL6 TBCCTL6 /* Timer B Capture/Compare Control 6 */ +#define TB0R TBR /* Timer B Counter Register */ +#define TB0CCR0 TBCCR0 /* Timer B Capture/Compare 0 */ +#define TB0CCR1 TBCCR1 /* Timer B Capture/Compare 1 */ +#define TB0CCR2 TBCCR2 /* Timer B Capture/Compare 2 */ +#define TB0CCR3 TBCCR3 /* Timer B Capture/Compare 3 */ +#define TB0CCR4 TBCCR4 /* Timer B Capture/Compare 4 */ +#define TB0CCR5 TBCCR5 /* Timer B Capture/Compare 5 */ +#define TB0CCR6 TBCCR6 /* Timer B Capture/Compare 6 */ +#define TB0IV_ TBIV_ /* Timer B Interrupt Vector Word */ +#define TB0CTL_ TBCTL_ /* Timer B Control */ +#define TB0CCTL0_ TBCCTL0_ /* Timer B Capture/Compare Control 0 */ +#define TB0CCTL1_ TBCCTL1_ /* Timer B Capture/Compare Control 1 */ +#define TB0CCTL2_ TBCCTL2_ /* Timer B Capture/Compare Control 2 */ +#define TB0CCTL3_ TBCCTL3_ /* Timer B Capture/Compare Control 3 */ +#define TB0CCTL4_ TBCCTL4_ /* Timer B Capture/Compare Control 4 */ +#define TB0CCTL5_ TBCCTL5_ /* Timer B Capture/Compare Control 5 */ +#define TB0CCTL6_ TBCCTL6_ /* Timer B Capture/Compare Control 6 */ +#define TB0R_ TBR_ /* Timer B Counter Register */ +#define TB0CCR0_ TBCCR0_ /* Timer B Capture/Compare 0 */ +#define TB0CCR1_ TBCCR1_ /* Timer B Capture/Compare 1 */ +#define TB0CCR2_ TBCCR2_ /* Timer B Capture/Compare 2 */ +#define TB0CCR3_ TBCCR3_ /* Timer B Capture/Compare 3 */ +#define TB0CCR4_ TBCCR4_ /* Timer B Capture/Compare 4 */ +#define TB0CCR5_ TBCCR5_ /* Timer B Capture/Compare 5 */ +#define TB0CCR6_ TBCCR6_ /* Timer B Capture/Compare 6 */ +#define TIMER0_B1_VECTOR TIMERB1_VECTOR /* Int. Vector: Timer B CC1-6, TB */ +#define TIMER0_B0_VECTOR TIMERB0_VECTOR /* Int. Vector: Timer B CC0 */ + +#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */ +#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */ +#define CNTL1 (0x1000) /* Counter lenght 1 */ +#define CNTL0 (0x0800) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200) /* Clock source 1 */ +#define TBSSEL0 (0x0100) /* Clock source 0 */ +#define TBCLR (0x0004) /* Timer B counter clear */ +#define TBIE (0x0002) /* Timer B interrupt enable */ +#define TBIFG (0x0001) /* Timer B interrupt flag */ + +#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */ +#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */ + +#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */ +#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */ +#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */ +#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */ +#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */ +#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */ +#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */ +#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */ +#define SHR_0 (0x0000) /* Timer B Group: 0 - individually */ +#define SHR_1 (0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (0x4000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (0x6000) /* Timer B Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0x0000) /* Timer B Group: 0 - individually */ +#define TBCLGRP_1 (0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (0x4000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (0x6000) /* Timer B Group: 3 - 1 group (all) */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +#define CLLD1 (0x0400) /* Compare latch load source 1 */ +#define CLLD0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TB7IV Definitions */ +#define TBIV_NONE (0x0000) /* No Interrupt pending */ +#define TBIV_TBCCR1 (0x0002) /* TBCCR1_CCIFG */ +#define TBIV_TBCCR2 (0x0004) /* TBCCR2_CCIFG */ +#define TBIV_TBCCR3 (0x0006) /* TBCCR3_CCIFG */ +#define TBIV_TBCCR4 (0x0008) /* TBCCR4_CCIFG */ +#define TBIV_TBCCR5 (0x000A) /* TBCCR3_CCIFG */ +#define TBIV_TBCCR6 (0x000C) /* TBCCR4_CCIFG */ +#define TBIV_TBIFG (0x000E) /* TBIFG */ + +/* Alternate register names - 5xx style */ +#define TB0IV_NONE (0x0000) /* No Interrupt pending */ +#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */ +#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */ +#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */ +#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */ +#define TB0IV_TBCCR5 (0x000A) /* TB0CCR3_CCIFG */ +#define TB0IV_TBCCR6 (0x000C) /* TB0CCR4_CCIFG */ +#define TB0IV_TBIFG (0x000E) /* TB0IFG */ + +/************************************************************ +* Basic Clock Module +************************************************************/ +#define __MSP430_HAS_BASIC_CLOCK__ /* Definition to show that Module is available */ + +sfr_b(DCOCTL); /* DCO Clock Frequency Control */ +sfr_b(BCSCTL1); /* Basic Clock System Control 1 */ +sfr_b(BCSCTL2); /* Basic Clock System Control 2 */ + +#define MOD0 (0x01) /* Modulation Bit 0 */ +#define MOD1 (0x02) /* Modulation Bit 1 */ +#define MOD2 (0x04) /* Modulation Bit 2 */ +#define MOD3 (0x08) /* Modulation Bit 3 */ +#define MOD4 (0x10) /* Modulation Bit 4 */ +#define DCO0 (0x20) /* DCO Select Bit 0 */ +#define DCO1 (0x40) /* DCO Select Bit 1 */ +#define DCO2 (0x80) /* DCO Select Bit 2 */ + +#define RSEL0 (0x01) /* Range Select Bit 0 */ +#define RSEL1 (0x02) /* Range Select Bit 1 */ +#define RSEL2 (0x04) /* Range Select Bit 2 */ +#define XT5V (0x08) /* XT5V should always be reset */ +#define DIVA0 (0x10) /* ACLK Divider 0 */ +#define DIVA1 (0x20) /* ACLK Divider 1 */ +#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ +#define XT2OFF (0x80) /* Enable XT2CLK */ + +#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */ +#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */ +#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */ +#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */ + +#define DCOR (0x01) /* Enable External Resistor : 1 */ +#define DIVS0 (0x02) /* SMCLK Divider 0 */ +#define DIVS1 (0x04) /* SMCLK Divider 1 */ +#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ +#define DIVM0 (0x10) /* MCLK Divider 0 */ +#define DIVM1 (0x20) /* MCLK Divider 1 */ +#define SELM0 (0x40) /* MCLK Source Select 0 */ +#define SELM1 (0x80) /* MCLK Source Select 1 */ + +#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */ +#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */ +#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */ +#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */ + +#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */ +#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */ +#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */ +#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */ + +#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */ +#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */ +#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */ +#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */ + +/************************************************************ +* Brown-Out, Supply Voltage Supervision (SVS) +************************************************************/ +#define __MSP430_HAS_SVS__ /* Definition to show that Module is available */ + +sfr_b(SVSCTL); /* SVS Control */ +#define SVSFG (0x01) /* SVS Flag */ +#define SVSOP (0x02) /* SVS output (read only) */ +#define SVSON (0x04) /* Switches the SVS on/off */ +#define PORON (0x08) /* Enable POR Generation if Low Voltage */ +#define VLD0 (0x10) +#define VLD1 (0x20) +#define VLD2 (0x40) +#define VLD3 (0x80) + +#define VLDON (0x10) +#define VLDOFF (0x00) +#define VLD_1_8V (0x10) + +/************************************************************* +* Flash Memory +*************************************************************/ +#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */ + +sfr_w(FCTL1); /* FLASH Control 1 */ +sfr_w(FCTL2); /* FLASH Control 2 */ +sfr_w(FCTL3); /* FLASH Control 3 */ + +#define FRKEY (0x9600) /* Flash key returned by read */ +#define FWKEY (0xA500) /* Flash key for write */ +#define FXKEY (0x3300) /* for use with XOR instruction */ + +#define ERASE (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004) /* Enable bit for Flash mass erase */ +#define WRT (0x0040) /* Enable bit for Flash write */ +#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ +#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */ + +#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */ +#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */ +#ifndef FN2 +#define FN2 (0x0004) +#endif +#ifndef FN3 +#define FN3 (0x0008) +#endif +#ifndef FN4 +#define FN4 (0x0010) +#endif +#define FN5 (0x0020) +#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */ +#define FSSEL1 (0x0080) /* Flash clock select 1 */ + +#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */ +#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */ +#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */ +#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */ + +#define BUSY (0x0001) /* Flash busy: 1 */ +#define KEYV (0x0002) /* Flash Key violation flag */ +#define ACCVIFG (0x0004) /* Flash Access violation flag */ +#define WAIT (0x0008) /* Wait flag for segment write */ +#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020) /* Flash Emergency Exit */ + +/************************************************************ +* Comparator A +************************************************************/ +#define __MSP430_HAS_COMPA__ /* Definition to show that Module is available */ + +sfr_b(CACTL1); /* Comparator A Control 1 */ +sfr_b(CACTL2); /* Comparator A Control 2 */ +sfr_b(CAPD); /* Comparator A Port Disable */ + +#define CAIFG (0x01) /* Comp. A Interrupt Flag */ +#define CAIE (0x02) /* Comp. A Interrupt Enable */ +#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */ +#define CAON (0x08) /* Comp. A enable */ +#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */ +#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */ +#define CARSEL (0x40) /* Comp. A Internal Reference Enable */ +#define CAEX (0x80) /* Comp. A Exchange Inputs */ + +#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */ +#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */ +#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */ +#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/ + +#define CAOUT (0x01) /* Comp. A Output */ +#define CAF (0x02) /* Comp. A Enable Output Filter */ +#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */ +#define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */ +#define CACTL24 (0x10) +#define CACTL25 (0x20) +#define CACTL26 (0x40) +#define CACTL27 (0x80) + +#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */ +#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */ +#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */ +#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */ +#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */ +#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */ +#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */ +#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */ + +/************************************************************ +* ADC12 +************************************************************/ +#define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */ + +sfr_w(ADC12CTL0); /* ADC12 Control 0 */ +sfr_w(ADC12CTL1); /* ADC12 Control 1 */ +sfr_w(ADC12IFG); /* ADC12 Interrupt Flag */ +sfr_w(ADC12IE); /* ADC12 Interrupt Enable */ +sfr_w(ADC12IV); /* ADC12 Interrupt Vector Word */ + +#define ADC12MEM_ (0x0140) /* ADC12 Conversion Memory */ +#ifndef __STDC__ +#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */ +#else +#define ADC12MEM ((volatile int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ +#endif +sfr_w(ADC12MEM0); /* ADC12 Conversion Memory 0 */ +sfr_w(ADC12MEM1); /* ADC12 Conversion Memory 1 */ +sfr_w(ADC12MEM2); /* ADC12 Conversion Memory 2 */ +sfr_w(ADC12MEM3); /* ADC12 Conversion Memory 3 */ +sfr_w(ADC12MEM4); /* ADC12 Conversion Memory 4 */ +sfr_w(ADC12MEM5); /* ADC12 Conversion Memory 5 */ +sfr_w(ADC12MEM6); /* ADC12 Conversion Memory 6 */ +sfr_w(ADC12MEM7); /* ADC12 Conversion Memory 7 */ +sfr_w(ADC12MEM8); /* ADC12 Conversion Memory 8 */ +sfr_w(ADC12MEM9); /* ADC12 Conversion Memory 9 */ +sfr_w(ADC12MEM10); /* ADC12 Conversion Memory 10 */ +sfr_w(ADC12MEM11); /* ADC12 Conversion Memory 11 */ +sfr_w(ADC12MEM12); /* ADC12 Conversion Memory 12 */ +sfr_w(ADC12MEM13); /* ADC12 Conversion Memory 13 */ +sfr_w(ADC12MEM14); /* ADC12 Conversion Memory 14 */ +sfr_w(ADC12MEM15); /* ADC12 Conversion Memory 15 */ + +#define ADC12MCTL_ (0x0080) /* ADC12 Memory Control */ +#ifndef __STDC__ +#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */ +#else +#define ADC12MCTL ((volatile char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ +#endif +sfr_b(ADC12MCTL0); /* ADC12 Memory Control 0 */ +sfr_b(ADC12MCTL1); /* ADC12 Memory Control 1 */ +sfr_b(ADC12MCTL2); /* ADC12 Memory Control 2 */ +sfr_b(ADC12MCTL3); /* ADC12 Memory Control 3 */ +sfr_b(ADC12MCTL4); /* ADC12 Memory Control 4 */ +sfr_b(ADC12MCTL5); /* ADC12 Memory Control 5 */ +sfr_b(ADC12MCTL6); /* ADC12 Memory Control 6 */ +sfr_b(ADC12MCTL7); /* ADC12 Memory Control 7 */ +sfr_b(ADC12MCTL8); /* ADC12 Memory Control 8 */ +sfr_b(ADC12MCTL9); /* ADC12 Memory Control 9 */ +sfr_b(ADC12MCTL10); /* ADC12 Memory Control 10 */ +sfr_b(ADC12MCTL11); /* ADC12 Memory Control 11 */ +sfr_b(ADC12MCTL12); /* ADC12 Memory Control 12 */ +sfr_b(ADC12MCTL13); /* ADC12 Memory Control 13 */ +sfr_b(ADC12MCTL14); /* ADC12 Memory Control 14 */ +sfr_b(ADC12MCTL15); /* ADC12 Memory Control 15 */ + +/* ADC12CTL0 */ +#define ADC12SC (0x001) /* ADC12 Start Conversion */ +#define ENC (0x002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON (0x010) /* ADC12 On/enable */ +#define REFON (0x020) /* ADC12 Reference on */ +#define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define MSC (0x080) /* ADC12 Multiple SampleConversion */ +#define SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */ +#define SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */ +#define SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */ +#define SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */ +#define SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */ +#define SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */ +#define SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */ +#define SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */ +#define MSH (0x080) + +#define SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 */ +#define ADC12BUSY (0x0001) /* ADC12 Busy */ +#define CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */ +#define CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */ +#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */ +#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */ +#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */ +#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */ +#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */ +#define ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ +#define SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ +#define SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */ +#define SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */ +#define CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */ +#define CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */ +#define CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */ +#define CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */ + +#define CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */ +#define CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */ +#define CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */ +#define CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */ +#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */ +#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */ +#define SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */ +#define SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */ +#define SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */ +#define SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */ +#define CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */ +#define CSTARTADD_1 (0x1000) /* ADC12 Conversion Start Address: 1 */ +#define CSTARTADD_2 (0x2000) /* ADC12 Conversion Start Address: 2 */ +#define CSTARTADD_3 (0x3000) /* ADC12 Conversion Start Address: 3 */ +#define CSTARTADD_4 (0x4000) /* ADC12 Conversion Start Address: 4 */ +#define CSTARTADD_5 (0x5000) /* ADC12 Conversion Start Address: 5 */ +#define CSTARTADD_6 (0x6000) /* ADC12 Conversion Start Address: 6 */ +#define CSTARTADD_7 (0x7000) /* ADC12 Conversion Start Address: 7 */ +#define CSTARTADD_8 (0x8000) /* ADC12 Conversion Start Address: 8 */ +#define CSTARTADD_9 (0x9000) /* ADC12 Conversion Start Address: 9 */ +#define CSTARTADD_10 (0xA000) /* ADC12 Conversion Start Address: 10 */ +#define CSTARTADD_11 (0xB000) /* ADC12 Conversion Start Address: 11 */ +#define CSTARTADD_12 (0xC000) /* ADC12 Conversion Start Address: 12 */ +#define CSTARTADD_13 (0xD000) /* ADC12 Conversion Start Address: 13 */ +#define CSTARTADD_14 (0xE000) /* ADC12 Conversion Start Address: 14 */ +#define CSTARTADD_15 (0xF000) /* ADC12 Conversion Start Address: 15 */ + +/* ADC12MCTLx */ +#define INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ +#define SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ +#define SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ +#define EOS (0x0080) /* ADC12 End of Sequence */ + +#define INCH_0 (0) /* ADC12 Input Channel 0 */ +#define INCH_1 (1) /* ADC12 Input Channel 1 */ +#define INCH_2 (2) /* ADC12 Input Channel 2 */ +#define INCH_3 (3) /* ADC12 Input Channel 3 */ +#define INCH_4 (4) /* ADC12 Input Channel 4 */ +#define INCH_5 (5) /* ADC12 Input Channel 5 */ +#define INCH_6 (6) /* ADC12 Input Channel 6 */ +#define INCH_7 (7) /* ADC12 Input Channel 7 */ +#define INCH_8 (8) /* ADC12 Input Channel 8 */ +#define INCH_9 (9) /* ADC12 Input Channel 9 */ +#define INCH_10 (10) /* ADC12 Input Channel 10 */ +#define INCH_11 (11) /* ADC12 Input Channel 11 */ +#define INCH_12 (12) /* ADC12 Input Channel 12 */ +#define INCH_13 (13) /* ADC12 Input Channel 13 */ +#define INCH_14 (14) /* ADC12 Input Channel 14 */ +#define INCH_15 (15) /* ADC12 Input Channel 15 */ + +#define SREF_0 (0x0000) /* ADC12 Select Reference 0 */ +#define SREF_1 (0x0010) /* ADC12 Select Reference 1 */ +#define SREF_2 (0x0020) /* ADC12 Select Reference 2 */ +#define SREF_3 (0x0030) /* ADC12 Select Reference 3 */ +#define SREF_4 (0x0040) /* ADC12 Select Reference 4 */ +#define SREF_5 (0x0050) /* ADC12 Select Reference 5 */ +#define SREF_6 (0x0060) /* ADC12 Select Reference 6 */ +#define SREF_7 (0x0070) /* ADC12 Select Reference 7 */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ +#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */ + +/************************************************************ +* DAC12 +************************************************************/ +#define __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */ + +sfr_w(DAC12_0CTL); /* DAC12_0 Control */ +sfr_w(DAC12_1CTL); /* DAC12_1 Control */ + +#define DAC12GRP (0x0001) /* DAC12 group */ +#define DAC12ENC (0x0002) /* DAC12 enable conversion */ +#define DAC12IFG (0x0004) /* DAC12 interrupt flag */ +#define DAC12IE (0x0008) /* DAC12 interrupt enable */ +#define DAC12DF (0x0010) /* DAC12 data format */ +#define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */ +#define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */ +#define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */ +#define DAC12IR (0x0100) /* DAC12 input reference and output range */ +#define DAC12CALON (0x0200) /* DAC12 calibration */ +#define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */ +#define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */ +#define DAC12RES (0x1000) /* DAC12 resolution */ +#define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */ +#define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */ + +#define DAC12AMP_0 (0x0000) /* DAC12 amplifier 0: off, 3-state */ +#define DAC12AMP_1 (0x0020) /* DAC12 amplifier 1: off, off */ +#define DAC12AMP_2 (0x0040) /* DAC12 amplifier 2: low, low */ +#define DAC12AMP_3 (0x0060) /* DAC12 amplifier 3: low, medium */ +#define DAC12AMP_4 (0x0080) /* DAC12 amplifier 4: low, high */ +#define DAC12AMP_5 (0x00A0) /* DAC12 amplifier 5: medium, medium */ +#define DAC12AMP_6 (0x00C0) /* DAC12 amplifier 6: medium, high */ +#define DAC12AMP_7 (0x00E0) /* DAC12 amplifier 7: high, high */ + +#define DAC12LSEL_0 (0x0000) /* DAC12 load select 0: direct */ +#define DAC12LSEL_1 (0x0400) /* DAC12 load select 1: latched with DAT */ +#define DAC12LSEL_2 (0x0800) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */ +#define DAC12LSEL_3 (0x0C00) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */ + +#define DAC12SREF_0 (0x0000) /* DAC12 reference 0: Vref+ */ +#define DAC12SREF_1 (0x2000) /* DAC12 reference 1: Vref+ */ +#define DAC12SREF_2 (0x4000) /* DAC12 reference 2: Veref+ */ +#define DAC12SREF_3 (0x6000) /* DAC12 reference 3: Veref+ */ + +sfr_w(DAC12_0DAT); /* DAC12_0 Data */ +sfr_w(DAC12_1DAT); /* DAC12_1 Data */ +/************************************************************ +* DMA +************************************************************/ +#define __MSP430_HAS_DMA_3__ /* Definition to show that Module is available */ + +sfr_w(DMACTL0); /* DMA Module Control 0 */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA1TSEL0 (0x0010) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0020) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0040) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0080) /* DMA channel 1 transfer select bit 3 */ +#define DMA2TSEL0 (0x0100) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0200) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0400) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0800) /* DMA channel 2 transfer select bit 3 */ + +#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw)*/ +#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: Timer_A (TACCR2.IFG) */ +#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: Timer_B (TBCCR2.IFG) */ +#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: UART0/I2C receive */ +#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: UART0/I2C transmit */ +#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: DAC12_0CTL.DAC12IFG */ +#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: UART1 receive */ +#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: UART1 transmit */ +#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: Multiplier ready */ +#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */ +#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */ + +#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ */ +#define DMA1TSEL_1 (0x0010) /* DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */ +#define DMA1TSEL_2 (0x0020) /* DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */ +#define DMA1TSEL_3 (0x0030) /* DMA channel 1 transfer select 3: UART0/I2C receive */ +#define DMA1TSEL_4 (0x0040) /* DMA channel 1 transfer select 4: UART0/I2C transmit */ +#define DMA1TSEL_5 (0x0050) /* DMA channel 1 transfer select 5: DAC12.0IFG */ +#define DMA1TSEL_6 (0x0060) /* DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA1TSEL_7 (0x0070) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA1TSEL_8 (0x0080) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA1TSEL_9 (0x0090) /* DMA channel 1 transfer select 9: UART1 receive */ +#define DMA1TSEL_10 (0x00A0) /* DMA channel 1 transfer select 10: UART1 transmit */ +#define DMA1TSEL_11 (0x00B0) /* DMA channel 1 transfer select 11: Multiplier ready */ +#define DMA1TSEL_14 (0x00E0) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */ +#define DMA1TSEL_15 (0x00F0) /* DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */ + +#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ */ +#define DMA2TSEL_1 (0x0100) /* DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */ +#define DMA2TSEL_2 (0x0200) /* DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */ +#define DMA2TSEL_3 (0x0300) /* DMA channel 2 transfer select 3: UART0/I2C receive */ +#define DMA2TSEL_4 (0x0400) /* DMA channel 2 transfer select 4: UART0/I2C transmit */ +#define DMA2TSEL_5 (0x0500) /* DMA channel 2 transfer select 5: DAC12.0IFG */ +#define DMA2TSEL_6 (0x0600) /* DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA2TSEL_7 (0x0700) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA2TSEL_8 (0x0800) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA2TSEL_9 (0x0900) /* DMA channel 2 transfer select 9: UART1 receive */ +#define DMA2TSEL_10 (0x0A00) /* DMA channel 2 transfer select 10: UART1 transmit */ +#define DMA2TSEL_11 (0x0B00) /* DMA channel 2 transfer select 11: Multiplier ready */ +#define DMA2TSEL_14 (0x0E00) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */ +#define DMA2TSEL_15 (0x0F00) /* DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */ + +sfr_w(DMACTL1); /* DMA Module Control 1 */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMAONFETCH (0x0004) /* DMA transfer on instruction fetch */ + +sfr_w(DMA0CTL); /* DMA Channel 0 Control */ +sfr_w(DMA1CTL); /* DMA Channel 1 Control */ +sfr_w(DMA2CTL); /* DMA Channel 2 Control */ + +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */ +#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */ +#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */ +#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0x0000) /* DMA transfer mode 0: single */ +#define DMADT_1 (0x1000) /* DMA transfer mode 1: block */ +#define DMADT_2 (0x2000) /* DMA transfer mode 2: interleaved */ +#define DMADT_3 (0x3000) /* DMA transfer mode 3: interleaved */ +#define DMADT_4 (0x4000) /* DMA transfer mode 4: single, repeat */ +#define DMADT_5 (0x5000) /* DMA transfer mode 5: block, repeat */ +#define DMADT_6 (0x6000) /* DMA transfer mode 6: interleaved, repeat */ +#define DMADT_7 (0x7000) /* DMA transfer mode 7: interleaved, repeat */ + +sfr_w(DMA0SA); /* DMA Channel 0 Source Address */ +sfr_w(DMA0DA); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0SZ); /* DMA Channel 0 Transfer Size */ +sfr_w(DMA1SA); /* DMA Channel 1 Source Address */ +sfr_w(DMA1DA); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1SZ); /* DMA Channel 1 Transfer Size */ +sfr_w(DMA2SA); /* DMA Channel 2 Source Address */ +sfr_w(DMA2DA); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2SZ); /* DMA Channel 2 Transfer Size */ + +/************************************************************ +* Interrupt Vectors (offset from 0xFFE0) +************************************************************/ + +#define DACDMA_VECTOR ( 1) /* 0xFFE0 DAC/DMA */ +#define PORT2_VECTOR ( 2) /* 0xFFE2 Port 2 */ +#define USART1TX_VECTOR ( 3) /* 0xFFE4 USART 1 Transmit */ +#define USART1RX_VECTOR ( 4) /* 0xFFE6 USART 1 Receive */ +#define PORT1_VECTOR ( 5) /* 0xFFE8 Port 1 */ +#define TIMERA1_VECTOR ( 6) /* 0xFFEA Timer A CC1-2, TA */ +#define TIMERA0_VECTOR ( 7) /* 0xFFEC Timer A CC0 */ +#define ADC12_VECTOR ( 8) /* 0xFFEE ADC */ +#define USART0TX_VECTOR ( 9) /* 0xFFF0 USART 0 Transmit */ +#define USART0RX_VECTOR (10) /* 0xFFF2 USART 0 Receive */ +#define WDT_VECTOR (11) /* 0xFFF4 Watchdog Timer */ +#define COMPARATORA_VECTOR (12) /* 0xFFF6 Comparator A */ +#define TIMERB1_VECTOR (13) /* 0xFFF8 Timer B CC1-6, TB */ +#define TIMERB0_VECTOR (14) /* 0xFFFA Timer B CC0 */ +#define NMI_VECTOR (15) /* 0xFFFC Non-maskable */ +#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ + + +/************************************************************ +* End of Modules +************************************************************/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* #ifndef __msp430x16x */ + diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1612.ld b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1612.ld new file mode 100644 index 0000000000..48f7f22156 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1612.ld @@ -0,0 +1,303 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430F1612 devices. */ +/* Version: 1.208 */ +/* Default linker script, for normal executables */ + +OUTPUT_ARCH(msp430) +ENTRY(_start) + +MEMORY { + SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ + RAM : ORIGIN = 0x1100, LENGTH = 0x1400 /* END=0x24FF, size 5120 */ + RAM_MIRROR : ORIGIN = 0x0200, LENGTH = 0x0800 + INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 2 128-byte segments */ + INFOA : ORIGIN = 0x1080, LENGTH = 0x0080 /* END=0x10FF, size 128 */ + INFOB : ORIGIN = 0x1000, LENGTH = 0x0080 /* END=0x107F, size 128 */ + ROM (rx) : ORIGIN = 0x2500, LENGTH = 0xDAE0 /* END=0xFFDF, size 56032 */ + VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002 + VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002 + VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002 + VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002 + VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002 + VECT6 : ORIGIN = 0xFFEA, LENGTH = 0x0002 + VECT7 : ORIGIN = 0xFFEC, LENGTH = 0x0002 + VECT8 : ORIGIN = 0xFFEE, LENGTH = 0x0002 + VECT9 : ORIGIN = 0xFFF0, LENGTH = 0x0002 + VECT10 : ORIGIN = 0xFFF2, LENGTH = 0x0002 + VECT11 : ORIGIN = 0xFFF4, LENGTH = 0x0002 + VECT12 : ORIGIN = 0xFFF6, LENGTH = 0x0002 + VECT13 : ORIGIN = 0xFFF8, LENGTH = 0x0002 + VECT14 : ORIGIN = 0xFFFA, LENGTH = 0x0002 + VECT15 : ORIGIN = 0xFFFC, LENGTH = 0x0002 + RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 +} + +SECTIONS +{ + __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) KEEP (*(__interrupt_vector_dacdma)) } > VECT1 + __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) KEEP (*(__interrupt_vector_port2)) } > VECT2 + __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_usart1tx)) } > VECT3 + __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_usart1rx)) } > VECT4 + __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) KEEP (*(__interrupt_vector_port1)) } > VECT5 + __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_timera1)) } > VECT6 + __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) KEEP (*(__interrupt_vector_timera0)) } > VECT7 + __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) KEEP (*(__interrupt_vector_adc12)) } > VECT8 + __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_usart0tx)) } > VECT9 + __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_usart0rx)) } > VECT10 + __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_wdt)) } > VECT11 + __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) KEEP (*(__interrupt_vector_comparatora)) } > VECT12 + __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) KEEP (*(__interrupt_vector_timerb1)) } > VECT13 + __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) KEEP (*(__interrupt_vector_timerb0)) } > VECT14 + __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_nmi)) } > VECT15 + __reset_vector : + { + KEEP (*(__interrupt_vector_16)) + KEEP (*(__interrupt_vector_reset)) + KEEP (*(.resetvec)) + } > RESETVEC + + .rodata : + { + . = ALIGN(2); + *(.plt) + *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) + *(.rodata1) + KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) + } > ROM + + /* Note: This is a separate .rodata section for sections which are + read only but which older linkers treat as read-write. + This prevents older linkers from marking the entire .rodata + section as read-write. */ + .rodata2 : + { + . = ALIGN(2); + PROVIDE (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE (__init_array_end = .); + . = ALIGN(2); + PROVIDE (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE (__fini_array_end = .); + . = ALIGN(2); + *(.eh_frame_hdr) + KEEP (*(.eh_frame)) + + /* gcc uses crtbegin.o to find the start of the constructors, so + we make sure it is first. Because this is a wildcard, it + doesn't matter if the user does not actually link against + crtbegin.o; the linker won't look for a file to match a + wildcard. The wildcard also means that it doesn't matter which + directory crtbegin.o is in. */ + KEEP (*crtbegin*.o(.ctors)) + + /* We don't want to include the .ctor section from from the + crtend.o file until after the sorted ctors. The .ctor section + from the crtend file contains the end of ctors marker and it + must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > ROM + + .text : + { + . = ALIGN(2); + PROVIDE (_start = .); + KEEP (*(SORT(.crt_*))) + *(.lowtext .text .stub .text.* .gnu.linkonce.t.* .text:*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.interp .hash .dynsym .dynstr .gnu.version*) + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + . = ALIGN(2); + KEEP (*(.init)) + KEEP (*(.fini)) + KEEP (*(.tm_clone_table)) + } > ROM + + .data : + { + . = ALIGN(2); + PROVIDE (__datastart = .); + + KEEP (*(.jcr)) + *(.data.rel.ro.local) *(.data.rel.ro*) + *(.dynamic) + + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + *(.data1) + *(.got.plt) *(.got) + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + . = ALIGN(2); + *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) + + . = ALIGN(2); + _edata = .; + PROVIDE (edata = .); + PROVIDE (__dataend = .); + } > RAM AT>ROM + + /* Note that crt0 assumes this is a multiple of two; all the + start/stop symbols are also assumed word-aligned. */ + PROVIDE(__romdatastart = LOADADDR(.data)); + PROVIDE (__romdatacopysize = SIZEOF(.data)); + + .bss : + { + . = ALIGN(2); + PROVIDE (__bssstart = .); + *(.dynbss) + *(.sbss .sbss.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(2); + *(COMMON) + PROVIDE (__bssend = .); + } > RAM + PROVIDE (__bsssize = SIZEOF(.bss)); + + /* This section contains data that is not initialised during load + or application reset. */ + .noinit (NOLOAD) : + { + . = ALIGN(2); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(2); + PROVIDE (__noinit_end = .); + end = .; + } > RAM + + /* We create this section so that "end" will always be in the + RAM region (matching .stack below), even if the .bss + section is empty. */ + .heap (NOLOAD) : + { + . = ALIGN(2); + __heap_start__ = .; + _end = __heap_start__; + PROVIDE (end = .); + KEEP (*(.heap)) + _end = .; + PROVIDE (end = .); + /* This word is here so that the section is not empty, and thus + not discarded by the linker. The actual value does not matter + and is ignored. */ + LONG(0); + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > RAM + /* WARNING: Do not place anything in RAM here. + The heap section must be the last section in RAM and the stack + section must be placed at the very end of the RAM region. */ + + .stack (ORIGIN (RAM) + LENGTH(RAM)) : + { + PROVIDE (__stack = .); + *(.stack) + } + + .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */ + .infoB : {} > INFOB + + .MSP430.attributes 0 : + { + KEEP (*(.MSP430.attributes)) + KEEP (*(.gnu.attributes)) + KEEP (*(__TI_build_attributes)) + } + + /* The rest are all not normally part of the runtime image. */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /DISCARD/ : { *(.note.GNU-stack) } +} + + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +INCLUDE msp430f1612_symbols.ld + diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1612_symbols.ld b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1612_symbols.ld new file mode 100644 index 0000000000..a9e9b55020 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1612_symbols.ld @@ -0,0 +1,272 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430F1612 devices. */ +/* Version: 1.208 */ + +/************************************************************ +* STANDARD BITS +************************************************************/ +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ +/************************************************************ +* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS +************************************************************/ +PROVIDE(IE1 = 0x0000); +PROVIDE(IFG1 = 0x0002); +PROVIDE(ME1 = 0x0004); +PROVIDE(IE2 = 0x0001); +PROVIDE(IFG2 = 0x0003); +PROVIDE(ME2 = 0x0005); +/************************************************************ +* WATCHDOG TIMER +************************************************************/ +PROVIDE(WDTCTL = 0x0120); +/************************************************************ +* HARDWARE MULTIPLIER +************************************************************/ +PROVIDE(MPY = 0x0130); +PROVIDE(MPYS = 0x0132); +PROVIDE(MAC = 0x0134); +PROVIDE(MACS = 0x0136); +PROVIDE(OP2 = 0x0138); +PROVIDE(RESLO = 0x013A); +PROVIDE(RESHI = 0x013C); +PROVIDE(SUMEXT = 0x013E); +/************************************************************ +* DIGITAL I/O Port1/2 +************************************************************/ +PROVIDE(P1IN = 0x0020); +PROVIDE(P1OUT = 0x0021); +PROVIDE(P1DIR = 0x0022); +PROVIDE(P1IFG = 0x0023); +PROVIDE(P1IES = 0x0024); +PROVIDE(P1IE = 0x0025); +PROVIDE(P1SEL = 0x0026); +PROVIDE(P2IN = 0x0028); +PROVIDE(P2OUT = 0x0029); +PROVIDE(P2DIR = 0x002A); +PROVIDE(P2IFG = 0x002B); +PROVIDE(P2IES = 0x002C); +PROVIDE(P2IE = 0x002D); +PROVIDE(P2SEL = 0x002E); +/************************************************************ +* DIGITAL I/O Port3/4 +************************************************************/ +PROVIDE(P3IN = 0x0018); +PROVIDE(P3OUT = 0x0019); +PROVIDE(P3DIR = 0x001A); +PROVIDE(P3SEL = 0x001B); +PROVIDE(P4IN = 0x001C); +PROVIDE(P4OUT = 0x001D); +PROVIDE(P4DIR = 0x001E); +PROVIDE(P4SEL = 0x001F); +/************************************************************ +* DIGITAL I/O Port5/6 +************************************************************/ +PROVIDE(P5IN = 0x0030); +PROVIDE(P5OUT = 0x0031); +PROVIDE(P5DIR = 0x0032); +PROVIDE(P5SEL = 0x0033); +PROVIDE(P6IN = 0x0034); +PROVIDE(P6OUT = 0x0035); +PROVIDE(P6DIR = 0x0036); +PROVIDE(P6SEL = 0x0037); +/************************************************************ +* USART +************************************************************/ +/************************************************************ +* USART 0 +************************************************************/ +PROVIDE(U0CTL = 0x0070); +PROVIDE(U0TCTL = 0x0071); +PROVIDE(U0RCTL = 0x0072); +PROVIDE(U0MCTL = 0x0073); +PROVIDE(U0BR0 = 0x0074); +PROVIDE(U0BR1 = 0x0075); +PROVIDE(U0RXBUF = 0x0076); +PROVIDE(U0TXBUF = 0x0077); +/************************************************************ +* USART 1 +************************************************************/ +PROVIDE(U1CTL = 0x0078); +PROVIDE(U1TCTL = 0x0079); +PROVIDE(U1RCTL = 0x007A); +PROVIDE(U1MCTL = 0x007B); +PROVIDE(U1BR0 = 0x007C); +PROVIDE(U1BR1 = 0x007D); +PROVIDE(U1RXBUF = 0x007E); +PROVIDE(U1TXBUF = 0x007F); +/************************************************************ +* USART0 I2C +************************************************************/ +PROVIDE(I2CIE = 0x0050); +PROVIDE(I2CIFG = 0x0051); +PROVIDE(I2CNDAT = 0x0052); +PROVIDE(I2CTCTL = 0x0071); +PROVIDE(I2CDCTL = 0x0072); +PROVIDE(I2CPSC = 0x0073); +PROVIDE(I2CSCLH = 0x0074); +PROVIDE(I2CSCLL = 0x0075); +PROVIDE(I2CDRB = 0x0076); +PROVIDE(I2CDRW = 0x0076); +PROVIDE(I2COA = 0x0118); +PROVIDE(I2CSA = 0x011A); +PROVIDE(I2CIV = 0x011C); +/************************************************************ +* Timer A3 +************************************************************/ +PROVIDE(TAIV = 0x012E); +PROVIDE(TACTL = 0x0160); +PROVIDE(TACCTL0 = 0x0162); +PROVIDE(TACCTL1 = 0x0164); +PROVIDE(TACCTL2 = 0x0166); +PROVIDE(TAR = 0x0170); +PROVIDE(TACCR0 = 0x0172); +PROVIDE(TACCR1 = 0x0174); +PROVIDE(TACCR2 = 0x0176); +/************************************************************ +* Timer B7 +************************************************************/ +PROVIDE(TBIV = 0x011E); +PROVIDE(TBCTL = 0x0180); +PROVIDE(TBCCTL0 = 0x0182); +PROVIDE(TBCCTL1 = 0x0184); +PROVIDE(TBCCTL2 = 0x0186); +PROVIDE(TBCCTL3 = 0x0188); +PROVIDE(TBCCTL4 = 0x018A); +PROVIDE(TBCCTL5 = 0x018C); +PROVIDE(TBCCTL6 = 0x018E); +PROVIDE(TBR = 0x0190); +PROVIDE(TBCCR0 = 0x0192); +PROVIDE(TBCCR1 = 0x0194); +PROVIDE(TBCCR2 = 0x0196); +PROVIDE(TBCCR3 = 0x0198); +PROVIDE(TBCCR4 = 0x019A); +PROVIDE(TBCCR5 = 0x019C); +PROVIDE(TBCCR6 = 0x019E); +/************************************************************ +* Basic Clock Module +************************************************************/ +PROVIDE(DCOCTL = 0x0056); +PROVIDE(BCSCTL1 = 0x0057); +PROVIDE(BCSCTL2 = 0x0058); +/************************************************************ +* Brown-Out, Supply Voltage Supervision (SVS) +************************************************************/ +PROVIDE(SVSCTL = 0x0055); +/************************************************************* +* Flash Memory +*************************************************************/ +PROVIDE(FCTL1 = 0x0128); +PROVIDE(FCTL2 = 0x012A); +PROVIDE(FCTL3 = 0x012C); +/************************************************************ +* Comparator A +************************************************************/ +PROVIDE(CACTL1 = 0x0059); +PROVIDE(CACTL2 = 0x005A); +PROVIDE(CAPD = 0x005B); +/************************************************************ +* ADC12 +************************************************************/ +PROVIDE(ADC12CTL0 = 0x01A0); +PROVIDE(ADC12CTL1 = 0x01A2); +PROVIDE(ADC12IFG = 0x01A4); +PROVIDE(ADC12IE = 0x01A6); +PROVIDE(ADC12IV = 0x01A8); +PROVIDE(ADC12MEM0 = 0x0140); +PROVIDE(ADC12MEM1 = 0x0142); +PROVIDE(ADC12MEM2 = 0x0144); +PROVIDE(ADC12MEM3 = 0x0146); +PROVIDE(ADC12MEM4 = 0x0148); +PROVIDE(ADC12MEM5 = 0x014A); +PROVIDE(ADC12MEM6 = 0x014C); +PROVIDE(ADC12MEM7 = 0x014E); +PROVIDE(ADC12MEM8 = 0x0150); +PROVIDE(ADC12MEM9 = 0x0152); +PROVIDE(ADC12MEM10 = 0x0154); +PROVIDE(ADC12MEM11 = 0x0156); +PROVIDE(ADC12MEM12 = 0x0158); +PROVIDE(ADC12MEM13 = 0x015A); +PROVIDE(ADC12MEM14 = 0x015C); +PROVIDE(ADC12MEM15 = 0x015E); +PROVIDE(ADC12MCTL0 = 0x0080); +PROVIDE(ADC12MCTL1 = 0x0081); +PROVIDE(ADC12MCTL2 = 0x0082); +PROVIDE(ADC12MCTL3 = 0x0083); +PROVIDE(ADC12MCTL4 = 0x0084); +PROVIDE(ADC12MCTL5 = 0x0085); +PROVIDE(ADC12MCTL6 = 0x0086); +PROVIDE(ADC12MCTL7 = 0x0087); +PROVIDE(ADC12MCTL8 = 0x0088); +PROVIDE(ADC12MCTL9 = 0x0089); +PROVIDE(ADC12MCTL10 = 0x008A); +PROVIDE(ADC12MCTL11 = 0x008B); +PROVIDE(ADC12MCTL12 = 0x008C); +PROVIDE(ADC12MCTL13 = 0x008D); +PROVIDE(ADC12MCTL14 = 0x008E); +PROVIDE(ADC12MCTL15 = 0x008F); +/************************************************************ +* DAC12 +************************************************************/ +PROVIDE(DAC12_0CTL = 0x01C0); +PROVIDE(DAC12_1CTL = 0x01C2); +PROVIDE(DAC12_0DAT = 0x01C8); +PROVIDE(DAC12_1DAT = 0x01CA); +/************************************************************ +* DMA +************************************************************/ +PROVIDE(DMACTL0 = 0x0122); +PROVIDE(DMACTL1 = 0x0124); +PROVIDE(DMA0CTL = 0x01E0); +PROVIDE(DMA1CTL = 0x01E8); +PROVIDE(DMA2CTL = 0x01F0); +PROVIDE(DMA0SA = 0x01E2); +PROVIDE(DMA0DA = 0x01E4); +PROVIDE(DMA0SZ = 0x01E6); +PROVIDE(DMA1SA = 0x01EA); +PROVIDE(DMA1DA = 0x01EC); +PROVIDE(DMA1SZ = 0x01EE); +PROVIDE(DMA2SA = 0x01F2); +PROVIDE(DMA2DA = 0x01F4); +PROVIDE(DMA2SZ = 0x01F6); +/************************************************************ +* Interrupt Vectors (offset from 0xFFE0) +************************************************************/ +/************************************************************ +* End of Modules +************************************************************/ diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617.h b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617.h new file mode 100644 index 0000000000..db79e40cba --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617.h @@ -0,0 +1,1520 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430x26x devices. +* +* Texas Instruments, Version 1.5 +* +* Rev. 1.0, Initial Version +* Rev. 1.1, changed PAREN from sfrb to sfrw +* Rev. 1.2 added TLV in INFO Memory +* Rev. 1.3, added definitions for Interrupt Vectors xxIV +* Rev. 1.4, changed 'void __data20 * volatile' definition +* Rev. 1.5, fixed define: TAG_ADC12_1 to 0x08 +* +********************************************************************/ + +#ifndef __msp430x26x +#define __msp430x26x + +#define __MSP430_HAS_MSP430X_CPU__ /* Definition to show that it has MSP430X CPU */ + +#define __MSP430_HEADER_VERSION__ 1208 + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------*/ +/* PERIPHERAL FILE MAP */ +/*----------------------------------------------------------------------------*/ + +#define __MSP430_TI_HEADERS__ + +#include + + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __STDC__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" + +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif /* End #defines for C */ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + +/************************************************************ +* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS +************************************************************/ + +sfr_b(IE1); /* Interrupt Enable 1 */ +#define WDTIE (0x01) /* Watchdog Interrupt Enable */ +#define OFIE (0x02) /* Osc. Fault Interrupt Enable */ +#define NMIIE (0x10) /* NMI Interrupt Enable */ +#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */ + +sfr_b(IFG1); /* Interrupt Flag 1 */ +#define WDTIFG (0x01) /* Watchdog Interrupt Flag */ +#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */ +#define PORIFG (0x04) /* Power On Interrupt Flag */ +#define RSTIFG (0x08) /* Reset Interrupt Flag */ +#define NMIIFG (0x10) /* NMI Interrupt Flag */ + +sfr_b(IE2); /* Interrupt Enable 2 */ +#define UC0IE IE2 +#define UCA0RXIE (0x01) +#define UCA0TXIE (0x02) +#define UCB0RXIE (0x04) +#define UCB0TXIE (0x08) + +sfr_b(IFG2); /* Interrupt Flag 2 */ +#define UC0IFG IFG2 +#define UCA0RXIFG (0x01) +#define UCA0TXIFG (0x02) +#define UCB0RXIFG (0x04) +#define UCB0TXIFG (0x08) + +sfr_b(UC1IE); /* USCI 1 Interrupt Enable */ +#define UCA1RXIE (0x01) +#define UCA1TXIE (0x02) +#define UCB1RXIE (0x04) +#define UCB1TXIE (0x08) + +sfr_b(UC1IFG); /* ISCI 1 Interrupt Flags */ +#define UCA1RXIFG (0x01) +#define UCA1TXIFG (0x02) +#define UCB1RXIFG (0x04) +#define UCB1TXIFG (0x08) + +/************************************************************ +* ADC12 +************************************************************/ +#define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */ + +sfr_w(ADC12CTL0); /* ADC12 Control 0 */ +sfr_w(ADC12CTL1); /* ADC12 Control 1 */ +sfr_w(ADC12IFG); /* ADC12 Interrupt Flag */ +sfr_w(ADC12IE); /* ADC12 Interrupt Enable */ +sfr_w(ADC12IV); /* ADC12 Interrupt Vector Word */ + +#define ADC12MEM_ (0x0140) /* ADC12 Conversion Memory */ +#ifndef __STDC__ +#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */ +#else +#define ADC12MEM ((volatile int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ +#endif +sfr_w(ADC12MEM0); /* ADC12 Conversion Memory 0 */ +sfr_w(ADC12MEM1); /* ADC12 Conversion Memory 1 */ +sfr_w(ADC12MEM2); /* ADC12 Conversion Memory 2 */ +sfr_w(ADC12MEM3); /* ADC12 Conversion Memory 3 */ +sfr_w(ADC12MEM4); /* ADC12 Conversion Memory 4 */ +sfr_w(ADC12MEM5); /* ADC12 Conversion Memory 5 */ +sfr_w(ADC12MEM6); /* ADC12 Conversion Memory 6 */ +sfr_w(ADC12MEM7); /* ADC12 Conversion Memory 7 */ +sfr_w(ADC12MEM8); /* ADC12 Conversion Memory 8 */ +sfr_w(ADC12MEM9); /* ADC12 Conversion Memory 9 */ +sfr_w(ADC12MEM10); /* ADC12 Conversion Memory 10 */ +sfr_w(ADC12MEM11); /* ADC12 Conversion Memory 11 */ +sfr_w(ADC12MEM12); /* ADC12 Conversion Memory 12 */ +sfr_w(ADC12MEM13); /* ADC12 Conversion Memory 13 */ +sfr_w(ADC12MEM14); /* ADC12 Conversion Memory 14 */ +sfr_w(ADC12MEM15); /* ADC12 Conversion Memory 15 */ + +#define ADC12MCTL_ (0x0080) /* ADC12 Memory Control */ +#ifndef __STDC__ +#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */ +#else +#define ADC12MCTL ((volatile char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ +#endif +sfr_b(ADC12MCTL0); /* ADC12 Memory Control 0 */ +sfr_b(ADC12MCTL1); /* ADC12 Memory Control 1 */ +sfr_b(ADC12MCTL2); /* ADC12 Memory Control 2 */ +sfr_b(ADC12MCTL3); /* ADC12 Memory Control 3 */ +sfr_b(ADC12MCTL4); /* ADC12 Memory Control 4 */ +sfr_b(ADC12MCTL5); /* ADC12 Memory Control 5 */ +sfr_b(ADC12MCTL6); /* ADC12 Memory Control 6 */ +sfr_b(ADC12MCTL7); /* ADC12 Memory Control 7 */ +sfr_b(ADC12MCTL8); /* ADC12 Memory Control 8 */ +sfr_b(ADC12MCTL9); /* ADC12 Memory Control 9 */ +sfr_b(ADC12MCTL10); /* ADC12 Memory Control 10 */ +sfr_b(ADC12MCTL11); /* ADC12 Memory Control 11 */ +sfr_b(ADC12MCTL12); /* ADC12 Memory Control 12 */ +sfr_b(ADC12MCTL13); /* ADC12 Memory Control 13 */ +sfr_b(ADC12MCTL14); /* ADC12 Memory Control 14 */ +sfr_b(ADC12MCTL15); /* ADC12 Memory Control 15 */ + +/* ADC12CTL0 */ +#define ADC12SC (0x001) /* ADC12 Start Conversion */ +#define ENC (0x002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON (0x010) /* ADC12 On/enable */ +#define REFON (0x020) /* ADC12 Reference on */ +#define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define MSC (0x080) /* ADC12 Multiple SampleConversion */ +#define SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */ +#define SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */ +#define SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */ +#define SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */ +#define SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */ +#define SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */ +#define SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */ +#define SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */ +#define MSH (0x080) + +#define SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 */ +#define ADC12BUSY (0x0001) /* ADC12 Busy */ +#define CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */ +#define CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */ +#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */ +#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */ +#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */ +#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */ +#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */ +#define ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ +#define SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ +#define SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */ +#define SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */ +#define CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */ +#define CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */ +#define CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */ +#define CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */ + +#define CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */ +#define CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */ +#define CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */ +#define CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */ +#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */ +#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */ +#define SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */ +#define SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */ +#define SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */ +#define SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */ +#define CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */ +#define CSTARTADD_1 (0x1000) /* ADC12 Conversion Start Address: 1 */ +#define CSTARTADD_2 (0x2000) /* ADC12 Conversion Start Address: 2 */ +#define CSTARTADD_3 (0x3000) /* ADC12 Conversion Start Address: 3 */ +#define CSTARTADD_4 (0x4000) /* ADC12 Conversion Start Address: 4 */ +#define CSTARTADD_5 (0x5000) /* ADC12 Conversion Start Address: 5 */ +#define CSTARTADD_6 (0x6000) /* ADC12 Conversion Start Address: 6 */ +#define CSTARTADD_7 (0x7000) /* ADC12 Conversion Start Address: 7 */ +#define CSTARTADD_8 (0x8000) /* ADC12 Conversion Start Address: 8 */ +#define CSTARTADD_9 (0x9000) /* ADC12 Conversion Start Address: 9 */ +#define CSTARTADD_10 (0xA000) /* ADC12 Conversion Start Address: 10 */ +#define CSTARTADD_11 (0xB000) /* ADC12 Conversion Start Address: 11 */ +#define CSTARTADD_12 (0xC000) /* ADC12 Conversion Start Address: 12 */ +#define CSTARTADD_13 (0xD000) /* ADC12 Conversion Start Address: 13 */ +#define CSTARTADD_14 (0xE000) /* ADC12 Conversion Start Address: 14 */ +#define CSTARTADD_15 (0xF000) /* ADC12 Conversion Start Address: 15 */ + +/* ADC12MCTLx */ +#define INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ +#define SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ +#define SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ +#define EOS (0x0080) /* ADC12 End of Sequence */ + +#define INCH_0 (0) /* ADC12 Input Channel 0 */ +#define INCH_1 (1) /* ADC12 Input Channel 1 */ +#define INCH_2 (2) /* ADC12 Input Channel 2 */ +#define INCH_3 (3) /* ADC12 Input Channel 3 */ +#define INCH_4 (4) /* ADC12 Input Channel 4 */ +#define INCH_5 (5) /* ADC12 Input Channel 5 */ +#define INCH_6 (6) /* ADC12 Input Channel 6 */ +#define INCH_7 (7) /* ADC12 Input Channel 7 */ +#define INCH_8 (8) /* ADC12 Input Channel 8 */ +#define INCH_9 (9) /* ADC12 Input Channel 9 */ +#define INCH_10 (10) /* ADC12 Input Channel 10 */ +#define INCH_11 (11) /* ADC12 Input Channel 11 */ +#define INCH_12 (12) /* ADC12 Input Channel 12 */ +#define INCH_13 (13) /* ADC12 Input Channel 13 */ +#define INCH_14 (14) /* ADC12 Input Channel 14 */ +#define INCH_15 (15) /* ADC12 Input Channel 15 */ + +#define SREF_0 (0x0000) /* ADC12 Select Reference 0 */ +#define SREF_1 (0x0010) /* ADC12 Select Reference 1 */ +#define SREF_2 (0x0020) /* ADC12 Select Reference 2 */ +#define SREF_3 (0x0030) /* ADC12 Select Reference 3 */ +#define SREF_4 (0x0040) /* ADC12 Select Reference 4 */ +#define SREF_5 (0x0050) /* ADC12 Select Reference 5 */ +#define SREF_6 (0x0060) /* ADC12 Select Reference 6 */ +#define SREF_7 (0x0070) /* ADC12 Select Reference 7 */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ +#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */ + +/************************************************************ +* Basic Clock Module +************************************************************/ +#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */ + +sfr_b(DCOCTL); /* DCO Clock Frequency Control */ +sfr_b(BCSCTL1); /* Basic Clock System Control 1 */ +sfr_b(BCSCTL2); /* Basic Clock System Control 2 */ +sfr_b(BCSCTL3); /* Basic Clock System Control 3 */ + +#define MOD0 (0x01) /* Modulation Bit 0 */ +#define MOD1 (0x02) /* Modulation Bit 1 */ +#define MOD2 (0x04) /* Modulation Bit 2 */ +#define MOD3 (0x08) /* Modulation Bit 3 */ +#define MOD4 (0x10) /* Modulation Bit 4 */ +#define DCO0 (0x20) /* DCO Select Bit 0 */ +#define DCO1 (0x40) /* DCO Select Bit 1 */ +#define DCO2 (0x80) /* DCO Select Bit 2 */ + +#define RSEL0 (0x01) /* Range Select Bit 0 */ +#define RSEL1 (0x02) /* Range Select Bit 1 */ +#define RSEL2 (0x04) /* Range Select Bit 2 */ +#define RSEL3 (0x08) /* Range Select Bit 3 */ +#define DIVA0 (0x10) /* ACLK Divider 0 */ +#define DIVA1 (0x20) /* ACLK Divider 1 */ +#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ +#define XT2OFF (0x80) /* Enable XT2CLK */ + +#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */ +#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */ +#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */ +#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */ + +#define DCOR (0x01) /* Enable External Resistor : 1 */ +#define DIVS0 (0x02) /* SMCLK Divider 0 */ +#define DIVS1 (0x04) /* SMCLK Divider 1 */ +#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ +#define DIVM0 (0x10) /* MCLK Divider 0 */ +#define DIVM1 (0x20) /* MCLK Divider 1 */ +#define SELM0 (0x40) /* MCLK Source Select 0 */ +#define SELM1 (0x80) /* MCLK Source Select 1 */ + +#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */ +#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */ +#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */ +#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */ + +#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */ +#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */ +#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */ +#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */ + +#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */ +#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */ +#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */ +#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */ + +#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */ +#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */ +#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */ +#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */ +#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */ +#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */ +#define XT2S0 (0x40) /* Mode 0 for XT2 */ +#define XT2S1 (0x80) /* Mode 1 for XT2 */ + +#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */ +#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */ +#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */ +#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */ + +#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */ +#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */ +#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */ +#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */ + +#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */ +#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */ +#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */ +#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */ + +/************************************************************ +* Comparator A +************************************************************/ +#define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */ + +sfr_b(CACTL1); /* Comparator A Control 1 */ +sfr_b(CACTL2); /* Comparator A Control 2 */ +sfr_b(CAPD); /* Comparator A Port Disable */ + +#define CAIFG (0x01) /* Comp. A Interrupt Flag */ +#define CAIE (0x02) /* Comp. A Interrupt Enable */ +#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */ +#define CAON (0x08) /* Comp. A enable */ +#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */ +#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */ +#define CARSEL (0x40) /* Comp. A Internal Reference Enable */ +#define CAEX (0x80) /* Comp. A Exchange Inputs */ + +#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */ +#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */ +#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */ +#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/ + +#define CAOUT (0x01) /* Comp. A Output */ +#define CAF (0x02) /* Comp. A Enable Output Filter */ +#define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */ +#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */ +#define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */ +#define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */ +#define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */ +#define CASHORT (0x80) /* Comp. A Short + and - Terminals */ + +#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */ +#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */ +#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */ +#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */ +#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */ +#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */ +#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */ +#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */ + +/************************************************************ +* DAC12 +************************************************************/ +#define __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */ + +sfr_w(DAC12_0CTL); /* DAC12_0 Control */ +sfr_w(DAC12_1CTL); /* DAC12_1 Control */ + +#define DAC12GRP (0x0001) /* DAC12 group */ +#define DAC12ENC (0x0002) /* DAC12 enable conversion */ +#define DAC12IFG (0x0004) /* DAC12 interrupt flag */ +#define DAC12IE (0x0008) /* DAC12 interrupt enable */ +#define DAC12DF (0x0010) /* DAC12 data format */ +#define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */ +#define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */ +#define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */ +#define DAC12IR (0x0100) /* DAC12 input reference and output range */ +#define DAC12CALON (0x0200) /* DAC12 calibration */ +#define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */ +#define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */ +#define DAC12RES (0x1000) /* DAC12 resolution */ +#define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */ +#define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */ +#define DAC12OPS (0x8000) /* DAC12 Operation Amp. */ + +#define DAC12AMP_0 (0x0000) /* DAC12 amplifier 0: off, 3-state */ +#define DAC12AMP_1 (0x0020) /* DAC12 amplifier 1: off, off */ +#define DAC12AMP_2 (0x0040) /* DAC12 amplifier 2: low, low */ +#define DAC12AMP_3 (0x0060) /* DAC12 amplifier 3: low, medium */ +#define DAC12AMP_4 (0x0080) /* DAC12 amplifier 4: low, high */ +#define DAC12AMP_5 (0x00A0) /* DAC12 amplifier 5: medium, medium */ +#define DAC12AMP_6 (0x00C0) /* DAC12 amplifier 6: medium, high */ +#define DAC12AMP_7 (0x00E0) /* DAC12 amplifier 7: high, high */ + +#define DAC12LSEL_0 (0x0000) /* DAC12 load select 0: direct */ +#define DAC12LSEL_1 (0x0400) /* DAC12 load select 1: latched with DAT */ +#define DAC12LSEL_2 (0x0800) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */ +#define DAC12LSEL_3 (0x0C00) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */ + +#define DAC12SREF_0 (0x0000) /* DAC12 reference 0: Vref+ */ +#define DAC12SREF_1 (0x2000) /* DAC12 reference 1: Vref+ */ +#define DAC12SREF_2 (0x4000) /* DAC12 reference 2: Veref+ */ +#define DAC12SREF_3 (0x6000) /* DAC12 reference 3: Veref+ */ + +sfr_w(DAC12_0DAT); /* DAC12_0 Data */ +sfr_w(DAC12_1DAT); /* DAC12_1 Data */ +/************************************************************ +* DMA_X +************************************************************/ +#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ + +sfr_w(DMACTL0); /* DMA Module Control 0 */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA1TSEL0 (0x0010) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0020) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0040) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0080) /* DMA channel 1 transfer select bit 3 */ +#define DMA2TSEL0 (0x0100) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0200) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0400) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0800) /* DMA channel 2 transfer select bit 3 */ + +#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw)*/ +#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: Timer_A (TACCR2.IFG) */ +#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: Timer_B (TBCCR2.IFG) */ +#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: USCIA0 receive */ +#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: USCIA0 transmit */ +#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: DAC12_0CTL.DAC12IFG */ +#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: USCIA1 receive */ +#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: USCIA1 transmit */ +#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: Multiplier ready */ +#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: USCIB0 receive */ +#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: USCIB0 transmit */ +#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */ +#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */ + +#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ */ +#define DMA1TSEL_1 (0x0010) /* DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */ +#define DMA1TSEL_2 (0x0020) /* DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */ +#define DMA1TSEL_3 (0x0030) /* DMA channel 1 transfer select 3: USCIA0 receive */ +#define DMA1TSEL_4 (0x0040) /* DMA channel 1 transfer select 4: USCIA0 transmit */ +#define DMA1TSEL_5 (0x0050) /* DMA channel 1 transfer select 5: DAC12.0IFG */ +#define DMA1TSEL_6 (0x0060) /* DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA1TSEL_7 (0x0070) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA1TSEL_8 (0x0080) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA1TSEL_9 (0x0090) /* DMA channel 1 transfer select 9: USCIA1 receive */ +#define DMA1TSEL_10 (0x00A0) /* DMA channel 1 transfer select 10: USCIA1 transmit */ +#define DMA1TSEL_11 (0x00B0) /* DMA channel 1 transfer select 11: Multiplier ready */ +#define DMA1TSEL_12 (0x00C0) /* DMA channel 1 transfer select 12: USCIB0 receive */ +#define DMA1TSEL_13 (0x00D0) /* DMA channel 1 transfer select 13: USCIB0 transmit */ +#define DMA1TSEL_14 (0x00E0) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */ +#define DMA1TSEL_15 (0x00F0) /* DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */ + +#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ */ +#define DMA2TSEL_1 (0x0100) /* DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */ +#define DMA2TSEL_2 (0x0200) /* DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */ +#define DMA2TSEL_3 (0x0300) /* DMA channel 2 transfer select 3: USCIA0 receive */ +#define DMA2TSEL_4 (0x0400) /* DMA channel 2 transfer select 4: USCIA0 transmit */ +#define DMA2TSEL_5 (0x0500) /* DMA channel 2 transfer select 5: DAC12.0IFG */ +#define DMA2TSEL_6 (0x0600) /* DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA2TSEL_7 (0x0700) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA2TSEL_8 (0x0800) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA2TSEL_9 (0x0900) /* DMA channel 2 transfer select 9: USCIA1 receive */ +#define DMA2TSEL_10 (0x0A00) /* DMA channel 2 transfer select 10: USCIA1 transmit */ +#define DMA2TSEL_11 (0x0B00) /* DMA channel 2 transfer select 11: Multiplier ready */ +#define DMA2TSEL_12 (0x0C00) /* DMA channel 2 transfer select 12: USCIB0 receive */ +#define DMA2TSEL_13 (0x0D00) /* DMA channel 2 transfer select 13: USCIB0 transmit */ +#define DMA2TSEL_14 (0x0E00) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */ +#define DMA2TSEL_15 (0x0F00) /* DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */ + +sfr_w(DMACTL1); /* DMA Module Control 1 */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMAONFETCH (0x0004) /* DMA transfer on instruction fetch */ + +sfr_w(DMAIV); /* DMA Interrupt Vector Word */ +sfr_w(DMA0CTL); /* DMA Channel 0 Control */ +sfr_w(DMA1CTL); /* DMA Channel 1 Control */ +sfr_w(DMA2CTL); /* DMA Channel 2 Control */ + +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */ +#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */ +#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */ +#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0x0000) /* DMA transfer mode 0: single */ +#define DMADT_1 (0x1000) /* DMA transfer mode 1: block */ +#define DMADT_2 (0x2000) /* DMA transfer mode 2: interleaved */ +#define DMADT_3 (0x3000) /* DMA transfer mode 3: interleaved */ +#define DMADT_4 (0x4000) /* DMA transfer mode 4: single, repeat */ +#define DMADT_5 (0x5000) /* DMA transfer mode 5: block, repeat */ +#define DMADT_6 (0x6000) /* DMA transfer mode 6: interleaved, repeat */ +#define DMADT_7 (0x7000) /* DMA transfer mode 7: interleaved, repeat */ + +sfr_l(DMA0SA); /* DMA Channel 0 Source Address */ +sfr_w(DMA0SAL); /* DMA Channel 0 Source Address */ +sfr_l(DMA0DA); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0DAL); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0SZ); /* DMA Channel 0 Transfer Size */ +sfr_l(DMA1SA); /* DMA Channel 1 Source Address */ +sfr_w(DMA1SAL); /* DMA Channel 1 Source Address */ +sfr_l(DMA1DA); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1DAL); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1SZ); /* DMA Channel 1 Transfer Size */ +sfr_l(DMA2SA); /* DMA Channel 2 Source Address */ +sfr_w(DMA2SAL); /* DMA Channel 2 Source Address */ +sfr_l(DMA2DA); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2DAL); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2SZ); /* DMA Channel 2 Transfer Size */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG */ +#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG */ +#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG */ + +/************************************************************* +* Flash Memory +*************************************************************/ +#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */ + +sfr_w(FCTL1); /* FLASH Control 1 */ +sfr_w(FCTL2); /* FLASH Control 2 */ +sfr_w(FCTL3); /* FLASH Control 3 */ +sfr_w(FCTL4); /* FLASH Control 4 */ + +#define FRKEY (0x9600) /* Flash key returned by read */ +#define FWKEY (0xA500) /* Flash key for write */ +#define FXKEY (0x3300) /* for use with XOR instruction */ + +#define ERASE (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004) /* Enable bit for Flash mass erase */ +#define EEI (0x0008) /* Enable Erase Interrupts */ +#define EEIEX (0x0010) /* Enable Emergency Interrupt Exit */ +#define WRT (0x0040) /* Enable bit for Flash write */ +#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ +#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */ + +#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */ +#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */ +#ifndef FN2 +#define FN2 (0x0004) +#endif +#ifndef FN3 +#define FN3 (0x0008) +#endif +#ifndef FN4 +#define FN4 (0x0010) +#endif +#define FN5 (0x0020) +#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */ +#define FSSEL1 (0x0080) /* Flash clock select 1 */ + +#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */ +#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */ +#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */ +#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */ + +#define BUSY (0x0001) /* Flash busy: 1 */ +#define KEYV (0x0002) /* Flash Key violation flag */ +#define ACCVIFG (0x0004) /* Flash Access violation flag */ +#define WAIT (0x0008) /* Wait flag for segment write */ +#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020) /* Flash Emergency Exit */ +#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +#define FAIL (0x0080) /* Last Program or Erase failed */ + +#define MGR0 (0x0010) /* Marginal read 0 mode. */ +#define MGR1 (0x0020) /* Marginal read 1 mode. */ + +/************************************************************ +* HARDWARE MULTIPLIER +************************************************************/ +#define __MSP430_HAS_MPY__ /* Definition to show that Module is available */ + +sfr_w(MPY); /* Multiply Unsigned/Operand 1 */ +sfr_w(MPYS); /* Multiply Signed/Operand 1 */ +sfr_w(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */ +sfr_w(MACS); /* Multiply Signed and Accumulate/Operand 1 */ +sfr_w(OP2); /* Operand 2 */ +sfr_w(RESLO); /* Result Low Word */ +sfr_w(RESHI); /* Result High Word */ +sfr_w(SUMEXT); /* Sum Extend */ + +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P1SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P2SEL__ /* Define for DriverLib */ + +sfr_b(P1IN); /* Port 1 Input */ +sfr_b(P1OUT); /* Port 1 Output */ +sfr_b(P1DIR); /* Port 1 Direction */ +sfr_b(P1IFG); /* Port 1 Interrupt Flag */ +sfr_b(P1IES); /* Port 1 Interrupt Edge Select */ +sfr_b(P1IE); /* Port 1 Interrupt Enable */ +sfr_b(P1SEL); /* Port 1 Selection */ +sfr_b(P1REN); /* Port 1 Resistor Enable */ + +sfr_b(P2IN); /* Port 2 Input */ +sfr_b(P2OUT); /* Port 2 Output */ +sfr_b(P2DIR); /* Port 2 Direction */ +sfr_b(P2IFG); /* Port 2 Interrupt Flag */ +sfr_b(P2IES); /* Port 2 Interrupt Edge Select */ +sfr_b(P2IE); /* Port 2 Interrupt Enable */ +sfr_b(P2SEL); /* Port 2 Selection */ +sfr_b(P2REN); /* Port 2 Resistor Enable */ + +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P3SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P4SEL__ /* Define for DriverLib */ + +sfr_b(P3IN); /* Port 3 Input */ +sfr_b(P3OUT); /* Port 3 Output */ +sfr_b(P3DIR); /* Port 3 Direction */ +sfr_b(P3SEL); /* Port 3 Selection */ +sfr_b(P3REN); /* Port 3 Resistor Enable */ + +sfr_b(P4IN); /* Port 4 Input */ +sfr_b(P4OUT); /* Port 4 Output */ +sfr_b(P4DIR); /* Port 4 Direction */ +sfr_b(P4SEL); /* Port 4 Selection */ +sfr_b(P4REN); /* Port 4 Resistor Enable */ + +/************************************************************ +* DIGITAL I/O Port5/6 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P5SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P6SEL__ /* Define for DriverLib */ + +sfr_b(P5IN); /* Port 5 Input */ +sfr_b(P5OUT); /* Port 5 Output */ +sfr_b(P5DIR); /* Port 5 Direction */ +sfr_b(P5SEL); /* Port 5 Selection */ +sfr_b(P5REN); /* Port 5 Resistor Enable */ + +sfr_b(P6IN); /* Port 6 Input */ +sfr_b(P6OUT); /* Port 6 Output */ +sfr_b(P6DIR); /* Port 6 Direction */ +sfr_b(P6SEL); /* Port 6 Selection */ +sfr_b(P6REN); /* Port 6 Resistor Enable */ + +/************************************************************ +* DIGITAL I/O Port7/8 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P7SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P8SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_PASEL__ /* Define for DriverLib */ + +sfr_b(P7IN); /* Port 7 Input */ +sfr_b(P7OUT); /* Port 7 Output */ +sfr_b(P7DIR); /* Port 7 Direction */ +sfr_b(P7SEL); /* Port 7 Selection */ +sfr_b(P7REN); /* Port 7 Resistor Enable */ + +sfr_b(P8IN); /* Port 8 Input */ +sfr_b(P8OUT); /* Port 8 Output */ +sfr_b(P8DIR); /* Port 8 Direction */ +sfr_b(P8SEL); /* Port 8 Selection */ +sfr_b(P8REN); /* Port 8 Resistor Enable */ + +sfr_w(PAIN); /* Port A Input */ +sfr_w(PAOUT); /* Port A Output */ +sfr_w(PADIR); /* Port A Direction */ +sfr_w(PASEL); /* Port A Selection */ +sfr_w(PAREN); /* Port A Resistor Enable */ + +/************************************************************ +* Brown-Out, Supply Voltage Supervision (SVS) +************************************************************/ +#define __MSP430_HAS_SVS__ /* Definition to show that Module is available */ + +sfr_b(SVSCTL); /* SVS Control */ +#define SVSFG (0x01) /* SVS Flag */ +#define SVSOP (0x02) /* SVS output (read only) */ +#define SVSON (0x04) /* Switches the SVS on/off */ +#define PORON (0x08) /* Enable POR Generation if Low Voltage */ +#define VLD0 (0x10) +#define VLD1 (0x20) +#define VLD2 (0x40) +#define VLD3 (0x80) + +#define VLDON (0x10) +#define VLDOFF (0x00) +#define VLD_1_8V (0x10) + +/************************************************************ +* Timer A3 +************************************************************/ +#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */ + +sfr_w(TAIV); /* Timer A Interrupt Vector Word */ +sfr_w(TACTL); /* Timer A Control */ +sfr_w(TACCTL0); /* Timer A Capture/Compare Control 0 */ +sfr_w(TACCTL1); /* Timer A Capture/Compare Control 1 */ +sfr_w(TACCTL2); /* Timer A Capture/Compare Control 2 */ +sfr_w(TAR); /* Timer A Counter Register */ +sfr_w(TACCR0); /* Timer A Capture/Compare 0 */ +sfr_w(TACCR1); /* Timer A Capture/Compare 1 */ +sfr_w(TACCR2); /* Timer A Capture/Compare 2 */ + +/* Alternate register names */ +#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ +#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ +#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ +#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */ +#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */ +#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */ +#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ +#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ +#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ +#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ +#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ +#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ +/* Alternate register names - 5xx style */ +#define TA0IV TAIV /* Timer A Interrupt Vector Word */ +#define TA0CTL TACTL /* Timer A Control */ +#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ +#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ +#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ +#define TA0R TAR /* Timer A Counter Register */ +#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */ +#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */ +#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */ +#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */ +#define TA0CTL_ TACTL_ /* Timer A Control */ +#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ +#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ +#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ +#define TA0R_ TAR_ /* Timer A Counter Register */ +#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ +#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ +#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ +#define TIMER0_A1_VECTOR TIMERA1_VECTOR /* Int. Vector: Timer A CC1-2, TA */ +#define TIMER0_A0_VECTOR TIMERA0_VECTOR /* Int. Vector: Timer A CC0 */ + +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (0x0020) /* Timer A mode control: 2 - Continous up */ +#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ + +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ +#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ +#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ +#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ +#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ +#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ + +/* TA3IV Definitions */ +#define TAIV_NONE (0x0000) /* No Interrupt pending */ +#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */ +#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */ +#define TAIV_6 (0x0006) /* Reserved */ +#define TAIV_8 (0x0008) /* Reserved */ +#define TAIV_TAIFG (0x000A) /* TAIFG */ + +/* Alternate register names - 5xx style */ +#define TA0IV_NONE (0x0000) /* No Interrupt pending */ +#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_6 (0x0006) /* Reserved */ +#define TA0IV_8 (0x0008) /* Reserved */ +#define TA0IV_TAIFG (0x000A) /* TA0IFG */ + +/************************************************************ +* Timer B7 +************************************************************/ +#define __MSP430_HAS_TB7__ /* Definition to show that Module is available */ + +sfr_w(TBIV); /* Timer B Interrupt Vector Word */ +sfr_w(TBCTL); /* Timer B Control */ +sfr_w(TBCCTL0); /* Timer B Capture/Compare Control 0 */ +sfr_w(TBCCTL1); /* Timer B Capture/Compare Control 1 */ +sfr_w(TBCCTL2); /* Timer B Capture/Compare Control 2 */ +sfr_w(TBCCTL3); /* Timer B Capture/Compare Control 3 */ +sfr_w(TBCCTL4); /* Timer B Capture/Compare Control 4 */ +sfr_w(TBCCTL5); /* Timer B Capture/Compare Control 5 */ +sfr_w(TBCCTL6); /* Timer B Capture/Compare Control 6 */ +sfr_w(TBR); /* Timer B Counter Register */ +sfr_w(TBCCR0); /* Timer B Capture/Compare 0 */ +sfr_w(TBCCR1); /* Timer B Capture/Compare 1 */ +sfr_w(TBCCR2); /* Timer B Capture/Compare 2 */ +sfr_w(TBCCR3); /* Timer B Capture/Compare 3 */ +sfr_w(TBCCR4); /* Timer B Capture/Compare 4 */ +sfr_w(TBCCR5); /* Timer B Capture/Compare 5 */ +sfr_w(TBCCR6); /* Timer B Capture/Compare 6 */ + +/* Alternate register names - 5xx style */ +#define TB0IV TBIV /* Timer B Interrupt Vector Word */ +#define TB0CTL TBCTL /* Timer B Control */ +#define TB0CCTL0 TBCCTL0 /* Timer B Capture/Compare Control 0 */ +#define TB0CCTL1 TBCCTL1 /* Timer B Capture/Compare Control 1 */ +#define TB0CCTL2 TBCCTL2 /* Timer B Capture/Compare Control 2 */ +#define TB0CCTL3 TBCCTL3 /* Timer B Capture/Compare Control 3 */ +#define TB0CCTL4 TBCCTL4 /* Timer B Capture/Compare Control 4 */ +#define TB0CCTL5 TBCCTL5 /* Timer B Capture/Compare Control 5 */ +#define TB0CCTL6 TBCCTL6 /* Timer B Capture/Compare Control 6 */ +#define TB0R TBR /* Timer B Counter Register */ +#define TB0CCR0 TBCCR0 /* Timer B Capture/Compare 0 */ +#define TB0CCR1 TBCCR1 /* Timer B Capture/Compare 1 */ +#define TB0CCR2 TBCCR2 /* Timer B Capture/Compare 2 */ +#define TB0CCR3 TBCCR3 /* Timer B Capture/Compare 3 */ +#define TB0CCR4 TBCCR4 /* Timer B Capture/Compare 4 */ +#define TB0CCR5 TBCCR5 /* Timer B Capture/Compare 5 */ +#define TB0CCR6 TBCCR6 /* Timer B Capture/Compare 6 */ +#define TB0IV_ TBIV_ /* Timer B Interrupt Vector Word */ +#define TB0CTL_ TBCTL_ /* Timer B Control */ +#define TB0CCTL0_ TBCCTL0_ /* Timer B Capture/Compare Control 0 */ +#define TB0CCTL1_ TBCCTL1_ /* Timer B Capture/Compare Control 1 */ +#define TB0CCTL2_ TBCCTL2_ /* Timer B Capture/Compare Control 2 */ +#define TB0CCTL3_ TBCCTL3_ /* Timer B Capture/Compare Control 3 */ +#define TB0CCTL4_ TBCCTL4_ /* Timer B Capture/Compare Control 4 */ +#define TB0CCTL5_ TBCCTL5_ /* Timer B Capture/Compare Control 5 */ +#define TB0CCTL6_ TBCCTL6_ /* Timer B Capture/Compare Control 6 */ +#define TB0R_ TBR_ /* Timer B Counter Register */ +#define TB0CCR0_ TBCCR0_ /* Timer B Capture/Compare 0 */ +#define TB0CCR1_ TBCCR1_ /* Timer B Capture/Compare 1 */ +#define TB0CCR2_ TBCCR2_ /* Timer B Capture/Compare 2 */ +#define TB0CCR3_ TBCCR3_ /* Timer B Capture/Compare 3 */ +#define TB0CCR4_ TBCCR4_ /* Timer B Capture/Compare 4 */ +#define TB0CCR5_ TBCCR5_ /* Timer B Capture/Compare 5 */ +#define TB0CCR6_ TBCCR6_ /* Timer B Capture/Compare 6 */ +#define TIMER0_B1_VECTOR TIMERB1_VECTOR /* Int. Vector: Timer B CC1-6, TB */ +#define TIMER0_B0_VECTOR TIMERB0_VECTOR /* Int. Vector: Timer B CC0 */ + +#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */ +#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */ +#define CNTL1 (0x1000) /* Counter lenght 1 */ +#define CNTL0 (0x0800) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200) /* Clock source 1 */ +#define TBSSEL0 (0x0100) /* Clock source 0 */ +#define TBCLR (0x0004) /* Timer B counter clear */ +#define TBIE (0x0002) /* Timer B interrupt enable */ +#define TBIFG (0x0001) /* Timer B interrupt flag */ + +#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */ +#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */ + +#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */ +#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */ +#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */ +#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */ +#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */ +#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */ +#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */ +#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */ +#define SHR_0 (0x0000) /* Timer B Group: 0 - individually */ +#define SHR_1 (0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (0x4000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (0x6000) /* Timer B Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0x0000) /* Timer B Group: 0 - individually */ +#define TBCLGRP_1 (0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (0x4000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (0x6000) /* Timer B Group: 3 - 1 group (all) */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +#define CLLD1 (0x0400) /* Compare latch load source 1 */ +#define CLLD0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TB7IV Definitions */ +#define TBIV_NONE (0x0000) /* No Interrupt pending */ +#define TBIV_TBCCR1 (0x0002) /* TBCCR1_CCIFG */ +#define TBIV_TBCCR2 (0x0004) /* TBCCR2_CCIFG */ +#define TBIV_TBCCR3 (0x0006) /* TBCCR3_CCIFG */ +#define TBIV_TBCCR4 (0x0008) /* TBCCR4_CCIFG */ +#define TBIV_TBCCR5 (0x000A) /* TBCCR3_CCIFG */ +#define TBIV_TBCCR6 (0x000C) /* TBCCR4_CCIFG */ +#define TBIV_TBIFG (0x000E) /* TBIFG */ + +/* Alternate register names - 5xx style */ +#define TB0IV_NONE (0x0000) /* No Interrupt pending */ +#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */ +#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */ +#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */ +#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */ +#define TB0IV_TBCCR5 (0x000A) /* TB0CCR3_CCIFG */ +#define TB0IV_TBCCR6 (0x000C) /* TB0CCR4_CCIFG */ +#define TB0IV_TBIFG (0x000E) /* TB0IFG */ + +/************************************************************ +* USCI +************************************************************/ +#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */ +#define __MSP430_HAS_USCI_AB0__ /* Definition to show that Module is available */ +#define __MSP430_HAS_USCI_AB1__ /* Definition to show that Module is available */ + +sfr_b(UCA0CTL0); /* USCI A0 Control Register 0 */ +sfr_b(UCA0CTL1); /* USCI A0 Control Register 1 */ +sfr_b(UCA0BR0); /* USCI A0 Baud Rate 0 */ +sfr_b(UCA0BR1); /* USCI A0 Baud Rate 1 */ +sfr_b(UCA0MCTL); /* USCI A0 Modulation Control */ +sfr_b(UCA0STAT); /* USCI A0 Status Register */ +sfr_b(UCA0RXBUF); /* USCI A0 Receive Buffer */ +sfr_b(UCA0TXBUF); /* USCI A0 Transmit Buffer */ +sfr_b(UCA0ABCTL); /* USCI A0 LIN Control */ +sfr_b(UCA0IRTCTL); /* USCI A0 IrDA Transmit Control */ +sfr_b(UCA0IRRCTL); /* USCI A0 IrDA Receive Control */ + + + +sfr_b(UCB0CTL0); /* USCI B0 Control Register 0 */ +sfr_b(UCB0CTL1); /* USCI B0 Control Register 1 */ +sfr_b(UCB0BR0); /* USCI B0 Baud Rate 0 */ +sfr_b(UCB0BR1); /* USCI B0 Baud Rate 1 */ +sfr_b(UCB0I2CIE); /* USCI B0 I2C Interrupt Enable Register */ +sfr_b(UCB0STAT); /* USCI B0 Status Register */ +sfr_b(UCB0RXBUF); /* USCI B0 Receive Buffer */ +sfr_b(UCB0TXBUF); /* USCI B0 Transmit Buffer */ +sfr_w(UCB0I2COA); /* USCI B0 I2C Own Address */ +sfr_w(UCB0I2CSA); /* USCI B0 I2C Slave Address */ + +sfr_b(UCA1CTL0); /* USCI A1 Control Register 0 */ +sfr_b(UCA1CTL1); /* USCI A1 Control Register 1 */ +sfr_b(UCA1BR0); /* USCI A1 Baud Rate 0 */ +sfr_b(UCA1BR1); /* USCI A1 Baud Rate 1 */ +sfr_b(UCA1MCTL); /* USCI A1 Modulation Control */ +sfr_b(UCA1STAT); /* USCI A1 Status Register */ +sfr_b(UCA1RXBUF); /* USCI A1 Receive Buffer */ +sfr_b(UCA1TXBUF); /* USCI A1 Transmit Buffer */ +sfr_b(UCA1ABCTL); /* USCI A1 LIN Control */ +sfr_b(UCA1IRTCTL); /* USCI A1 IrDA Transmit Control */ +sfr_b(UCA1IRRCTL); /* USCI A1 IrDA Receive Control */ + + + +sfr_b(UCB1CTL0); /* USCI B1 Control Register 0 */ +sfr_b(UCB1CTL1); /* USCI B1 Control Register 1 */ +sfr_b(UCB1BR0); /* USCI B1 Baud Rate 0 */ +sfr_b(UCB1BR1); /* USCI B1 Baud Rate 1 */ +sfr_b(UCB1I2CIE); /* USCI B1 I2C Interrupt Enable Register */ +sfr_b(UCB1STAT); /* USCI B1 Status Register */ +sfr_b(UCB1RXBUF); /* USCI B1 Receive Buffer */ +sfr_b(UCB1TXBUF); /* USCI B1 Transmit Buffer */ +sfr_w(UCB1I2COA); /* USCI B1 I2C Own Address */ +sfr_w(UCB1I2CSA); /* USCI B1 I2C Slave Address */ + +// UART-Mode Bits +#define UCPEN (0x80) /* Async. Mode: Parity enable */ +#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// SPI-Mode Bits +#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x08) /* Sync. Mode: Master Select */ + +// I2C-Mode Bits +#define UCA10 (0x80) /* 10-bit Address Mode */ +#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ +#define UCMM (0x20) /* Multi-Master Environment */ +//#define res (0x10) /* reserved */ +#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ + +// UART-Mode Bits +#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x20) /* RX Error interrupt enable */ +#define UCBRKIE (0x10) /* Break interrupt enable */ +#define UCDORM (0x08) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x04) /* Send next Data as Address */ +#define UCTXBRK (0x02) /* Send next Data as Break */ +#define UCSWRST (0x01) /* USCI Software Reset */ + +// SPI-Mode Bits +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +//#define res (0x08) /* reserved */ +//#define res (0x04) /* reserved */ +//#define res (0x02) /* reserved */ + +// I2C-Mode Bits +//#define res (0x20) /* reserved */ +#define UCTR (0x10) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x08) /* Transmit NACK */ +#define UCTXSTP (0x04) /* Transmit STOP */ +#define UCTXSTT (0x02) /* Transmit START */ +#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ + +#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ +#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ +#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ +#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ +#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ +#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ +#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ +#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ +#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ +#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ + +#define UCLISTEN (0x80) /* USCI Listen mode */ +#define UCFE (0x40) /* USCI Frame Error Flag */ +#define UCOE (0x20) /* USCI Overrun Error Flag */ +#define UCPE (0x10) /* USCI Parity Error Flag */ +#define UCBRK (0x08) /* USCI Break received */ +#define UCRXERR (0x04) /* USCI RX Error Flag */ +#define UCADDR (0x02) /* USCI Address received Flag */ +#define UCBUSY (0x01) /* USCI Busy Flag */ +#define UCIDLE (0x02) /* USCI Idle line detected Flag */ + +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +#define UCNACKIE (0x08) /* NACK Condition interrupt enable */ +#define UCSTPIE (0x04) /* STOP Condition interrupt enable */ +#define UCSTTIE (0x02) /* START Condition interrupt enable */ +#define UCALIE (0x01) /* Arbitration Lost interrupt enable */ + +#define UCSCLLOW (0x40) /* SCL low */ +#define UCGC (0x20) /* General Call address received Flag */ +#define UCBBUSY (0x10) /* Bus Busy Flag */ +#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */ +#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */ +#define UCSTTIFG (0x02) /* START Condition interrupt Flag */ +#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */ + +#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ + +#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ + +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOA9 (0x0200) /* I2C Own Address 9 */ +#define UCOA8 (0x0100) /* I2C Own Address 8 */ +#define UCOA7 (0x0080) /* I2C Own Address 7 */ +#define UCOA6 (0x0040) /* I2C Own Address 6 */ +#define UCOA5 (0x0020) /* I2C Own Address 5 */ +#define UCOA4 (0x0010) /* I2C Own Address 4 */ +#define UCOA3 (0x0008) /* I2C Own Address 3 */ +#define UCOA2 (0x0004) /* I2C Own Address 2 */ +#define UCOA1 (0x0002) /* I2C Own Address 1 */ +#define UCOA0 (0x0001) /* I2C Own Address 0 */ + +#define UCSA9 (0x0200) /* I2C Slave Address 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address 0 */ + +/************************************************************ +* WATCHDOG TIMER +************************************************************/ +#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */ + +sfr_w(WDTCTL); /* Watchdog Timer Control */ +/* The bit names have been prefixed with "WDT" */ +#define WDTIS0 (0x0001) +#define WDTIS1 (0x0002) +#define WDTSSEL (0x0004) +#define WDTCNTCL (0x0008) +#define WDTTMSEL (0x0010) +#define WDTNMI (0x0020) +#define WDTNMIES (0x0040) +#define WDTHOLD (0x0080) + +#define WDTPW (0x5A00) + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ + +/* INTERRUPT CONTROL */ +/* These two bits are defined in the Special Function Registers */ +/* #define WDTIE 0x01 */ +/* #define WDTIFG 0x01 */ + +/************************************************************ +* Calibration Data in Info Mem +************************************************************/ + +/* TLV Calibration Data Structure */ +#define TAG_DCO_30 (0x01) /* Tag for DCO30 Calibration Data */ +#define TAG_ADC12_1 (0x08) /* Tag for ADC12_1 Calibration Data */ +#define TAG_EMPTY (0xFE) /* Tag for Empty Data Field in Calibration Data */ + +#ifndef __DisableCalData +sfr_w(TLV_CHECKSUM); /* TLV CHECK SUM */ +sfr_b(TLV_DCO_30_TAG); /* TLV TAG_DCO30 TAG */ +sfr_b(TLV_DCO_30_LEN); /* TLV TAG_DCO30 LEN */ +sfr_b(TLV_ADC12_1_TAG); /* TLV ADC12_1 TAG */ +sfr_b(TLV_ADC12_1_LEN); /* TLV ADC12_1 LEN */ +#endif + +#define CAL_ADC_25T85 (0x0010) /* Index for 2.5V/85Deg Cal. Value */ +#define CAL_ADC_25T30 (0x000E) /* Index for 2.5V/30Deg Cal. Value */ +#define CAL_ADC_25VREF_FACTOR (0x000C) /* Index for 2.5V Ref. Factor */ +#define CAL_ADC_15T85 (0x000A) /* Index for 1.5V/85Deg Cal. Value */ +#define CAL_ADC_15T30 (0x0008) /* Index for 1.5V/30Deg Cal. Value */ +#define CAL_ADC_15VREF_FACTOR (0x0006) /* Index for ADC 1.5V Ref. Factor */ +#define CAL_ADC_OFFSET (0x0004) /* Index for ADC Offset */ +#define CAL_ADC_GAIN_FACTOR (0x0002) /* Index for ADC Gain Factor */ + +#define CAL_DCO_16MHZ (0x0002) /* Index for DCOCTL Calibration Data for 16MHz */ +#define CAL_BC1_16MHZ (0x0003) /* Index for BCSCTL1 Calibration Data for 16MHz */ +#define CAL_DCO_12MHZ (0x0004) /* Index for DCOCTL Calibration Data for 12MHz */ +#define CAL_BC1_12MHZ (0x0005) /* Index for BCSCTL1 Calibration Data for 12MHz */ +#define CAL_DCO_8MHZ (0x0006) /* Index for DCOCTL Calibration Data for 8MHz */ +#define CAL_BC1_8MHZ (0x0007) /* Index for BCSCTL1 Calibration Data for 8MHz */ +#define CAL_DCO_1MHZ (0x0008) /* Index for DCOCTL Calibration Data for 1MHz */ +#define CAL_BC1_1MHZ (0x0009) /* Index for BCSCTL1 Calibration Data for 1MHz */ + + +/************************************************************ +* Calibration Data in Info Mem +************************************************************/ + +#ifndef __DisableCalData + +sfr_b(CALDCO_16MHZ); /* DCOCTL Calibration Data for 16MHz */ +sfr_b(CALBC1_16MHZ); /* BCSCTL1 Calibration Data for 16MHz */ +sfr_b(CALDCO_12MHZ); /* DCOCTL Calibration Data for 12MHz */ +sfr_b(CALBC1_12MHZ); /* BCSCTL1 Calibration Data for 12MHz */ +sfr_b(CALDCO_8MHZ); /* DCOCTL Calibration Data for 8MHz */ +sfr_b(CALBC1_8MHZ); /* BCSCTL1 Calibration Data for 8MHz */ +sfr_b(CALDCO_1MHZ); /* DCOCTL Calibration Data for 1MHz */ +sfr_b(CALBC1_1MHZ); /* BCSCTL1 Calibration Data for 1MHz */ + +#endif /* #ifndef __DisableCalData */ + +/************************************************************ +* Interrupt Vectors (offset from 0xFFC0) +************************************************************/ + +#define RESERVED0_VECTOR ( 1) /* 0xFFC0 Reserved Int. Vector 0 */ +#define RESERVED1_VECTOR ( 2) /* 0xFFC2 Reserved Int. Vector 1 */ +#define RESERVED2_VECTOR ( 3) /* 0xFFC4 Reserved Int. Vector 2 */ +#define RESERVED3_VECTOR ( 4) /* 0xFFC6 Reserved Int. Vector 3 */ +#define RESERVED4_VECTOR ( 5) /* 0xFFC8 Reserved Int. Vector 4 */ +#define RESERVED5_VECTOR ( 6) /* 0xFFCA Reserved Int. Vector 5 */ +#define RESERVED6_VECTOR ( 7) /* 0xFFCC Reserved Int. Vector 6 */ +#define RESERVED7_VECTOR ( 8) /* 0xFFCE Reserved Int. Vector 7 */ +#define RESERVED8_VECTOR ( 9) /* 0xFFD0 Reserved Int. Vector 8 */ +#define RESERVED9_VECTOR (10) /* 0xFFD2 Reserved Int. Vector 9 */ +#define RESERVED10_VECTOR (11) /* 0xFFD4 Reserved Int. Vector 10 */ +#define RESERVED11_VECTOR (12) /* 0xFFD6 Reserved Int. Vector 11 */ +#define RESERVED12_VECTOR (13) /* 0xFFD8 Reserved Int. Vector 12 */ +#define RESERVED13_VECTOR (14) /* 0xFFDA Reserved Int. Vector 13 */ +#define DAC12_VECTOR (15) /* 0xFFDC DAC12 */ +#define DMA_VECTOR (16) /* 0xFFDE DMA */ +#define USCIAB1TX_VECTOR (17) /* 0xFFE0 USCI A1/B1 Transmit */ +#define USCIAB1RX_VECTOR (18) /* 0xFFE2 USCI A1/B1 Receive */ +#define PORT1_VECTOR (19) /* 0xFFE4 Port 1 */ +#define PORT2_VECTOR (20) /* 0xFFE6 Port 2 */ +#define RESERVED20_VECTOR (21) /* 0xFFE8 Reserved Int. Vector 20 */ +#define ADC12_VECTOR (22) /* 0xFFEA ADC */ +#define USCIAB0TX_VECTOR (23) /* 0xFFEC USCI A0/B0 Transmit */ +#define USCIAB0RX_VECTOR (24) /* 0xFFEE USCI A0/B0 Receive */ +#define TIMERA1_VECTOR (25) /* 0xFFF0 Timer A CC1-2, TA */ +#define TIMERA0_VECTOR (26) /* 0xFFF2 Timer A CC0 */ +#define WDT_VECTOR (27) /* 0xFFF4 Watchdog Timer */ +#define COMPARATORA_VECTOR (28) /* 0xFFF6 Comparator A */ +#define TIMERB1_VECTOR (29) /* 0xFFF8 Timer B CC1-6, TB */ +#define TIMERB0_VECTOR (30) /* 0xFFFA Timer B CC0 */ +#define NMI_VECTOR (31) /* 0xFFFC Non-maskable */ +#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ + +/************************************************************ +* End of Modules +************************************************************/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* #ifndef __msp430x26x */ + diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617.ld b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617.ld new file mode 100644 index 0000000000..e3ae2d1074 --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617.ld @@ -0,0 +1,397 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430F2617 devices. */ +/* Version: 1.208 */ +/* Default linker script, for normal executables */ + +OUTPUT_ARCH(msp430) +ENTRY(_start) + +MEMORY { + SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ + RAM : ORIGIN = 0x1100, LENGTH = 0x2000 /* END=0x30FF, size 8192 */ + RAM_MIRROR : ORIGIN = 0x0200, LENGTH = 0x0800 + INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 4 64-byte segments */ + INFOA : ORIGIN = 0x10C0, LENGTH = 0x0040 /* END=0x10FF, size 64 */ + INFOB : ORIGIN = 0x1080, LENGTH = 0x0040 /* END=0x10BF, size 64 */ + INFOC : ORIGIN = 0x1040, LENGTH = 0x0040 /* END=0x107F, size 64 */ + INFOD : ORIGIN = 0x1000, LENGTH = 0x0040 /* END=0x103F, size 64 */ + ROM (rx) : ORIGIN = 0x3100, LENGTH = 0xCEBE /* END=0xFFBD, size 52926 */ + HIROM (rx) : ORIGIN = 0x00010000, LENGTH = 0x00009FFF + BSLSIGNATURE : ORIGIN = 0xFFBE, LENGTH = 0x0002 + VECT1 : ORIGIN = 0xFFC0, LENGTH = 0x0002 + VECT2 : ORIGIN = 0xFFC2, LENGTH = 0x0002 + VECT3 : ORIGIN = 0xFFC4, LENGTH = 0x0002 + VECT4 : ORIGIN = 0xFFC6, LENGTH = 0x0002 + VECT5 : ORIGIN = 0xFFC8, LENGTH = 0x0002 + VECT6 : ORIGIN = 0xFFCA, LENGTH = 0x0002 + VECT7 : ORIGIN = 0xFFCC, LENGTH = 0x0002 + VECT8 : ORIGIN = 0xFFCE, LENGTH = 0x0002 + VECT9 : ORIGIN = 0xFFD0, LENGTH = 0x0002 + VECT10 : ORIGIN = 0xFFD2, LENGTH = 0x0002 + VECT11 : ORIGIN = 0xFFD4, LENGTH = 0x0002 + VECT12 : ORIGIN = 0xFFD6, LENGTH = 0x0002 + VECT13 : ORIGIN = 0xFFD8, LENGTH = 0x0002 + VECT14 : ORIGIN = 0xFFDA, LENGTH = 0x0002 + VECT15 : ORIGIN = 0xFFDC, LENGTH = 0x0002 + VECT16 : ORIGIN = 0xFFDE, LENGTH = 0x0002 + VECT17 : ORIGIN = 0xFFE0, LENGTH = 0x0002 + VECT18 : ORIGIN = 0xFFE2, LENGTH = 0x0002 + VECT19 : ORIGIN = 0xFFE4, LENGTH = 0x0002 + VECT20 : ORIGIN = 0xFFE6, LENGTH = 0x0002 + VECT21 : ORIGIN = 0xFFE8, LENGTH = 0x0002 + VECT22 : ORIGIN = 0xFFEA, LENGTH = 0x0002 + VECT23 : ORIGIN = 0xFFEC, LENGTH = 0x0002 + VECT24 : ORIGIN = 0xFFEE, LENGTH = 0x0002 + VECT25 : ORIGIN = 0xFFF0, LENGTH = 0x0002 + VECT26 : ORIGIN = 0xFFF2, LENGTH = 0x0002 + VECT27 : ORIGIN = 0xFFF4, LENGTH = 0x0002 + VECT28 : ORIGIN = 0xFFF6, LENGTH = 0x0002 + VECT29 : ORIGIN = 0xFFF8, LENGTH = 0x0002 + VECT30 : ORIGIN = 0xFFFA, LENGTH = 0x0002 + VECT31 : ORIGIN = 0xFFFC, LENGTH = 0x0002 + RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 +} + +SECTIONS +{ + .bslsignature : {} > BSLSIGNATURE + __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) KEEP (*(__interrupt_vector_reserved0)) } > VECT1 + __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) KEEP (*(__interrupt_vector_reserved1)) } > VECT2 + __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_reserved2)) } > VECT3 + __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_reserved3)) } > VECT4 + __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) KEEP (*(__interrupt_vector_reserved4)) } > VECT5 + __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_reserved5)) } > VECT6 + __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) KEEP (*(__interrupt_vector_reserved6)) } > VECT7 + __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) KEEP (*(__interrupt_vector_reserved7)) } > VECT8 + __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_reserved8)) } > VECT9 + __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_reserved9)) } > VECT10 + __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_reserved10)) } > VECT11 + __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) KEEP (*(__interrupt_vector_reserved11)) } > VECT12 + __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) KEEP (*(__interrupt_vector_reserved12)) } > VECT13 + __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) KEEP (*(__interrupt_vector_reserved13)) } > VECT14 + __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_dac12)) } > VECT15 + __interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) KEEP (*(__interrupt_vector_dma)) } > VECT16 + __interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) KEEP (*(__interrupt_vector_usciab1tx)) } > VECT17 + __interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) KEEP (*(__interrupt_vector_usciab1rx)) } > VECT18 + __interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) KEEP (*(__interrupt_vector_port1)) } > VECT19 + __interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) KEEP (*(__interrupt_vector_port2)) } > VECT20 + __interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) KEEP (*(__interrupt_vector_reserved20)) } > VECT21 + __interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) KEEP (*(__interrupt_vector_adc12)) } > VECT22 + __interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) KEEP (*(__interrupt_vector_usciab0tx)) } > VECT23 + __interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) KEEP (*(__interrupt_vector_usciab0rx)) } > VECT24 + __interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) KEEP (*(__interrupt_vector_timera1)) } > VECT25 + __interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) KEEP (*(__interrupt_vector_timera0)) } > VECT26 + __interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) KEEP (*(__interrupt_vector_wdt)) } > VECT27 + __interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) KEEP (*(__interrupt_vector_comparatora)) } > VECT28 + __interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) KEEP (*(__interrupt_vector_timerb1)) } > VECT29 + __interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) KEEP (*(__interrupt_vector_timerb0)) } > VECT30 + __interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) KEEP (*(__interrupt_vector_nmi)) } > VECT31 + __reset_vector : + { + KEEP (*(__interrupt_vector_32)) + KEEP (*(__interrupt_vector_reset)) + KEEP (*(.resetvec)) + } > RESETVEC + + .lower.rodata : + { + . = ALIGN(2); + *(.lower.rodata.* .lower.rodata) + } > ROM + + .rodata : + { + . = ALIGN(2); + *(.plt) + . = ALIGN(2); + *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) + *(.rodata1) + KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) + } > ROM + + /* Note: This is a separate .rodata section for sections which are + read only but which older linkers treat as read-write. + This prevents older linkers from marking the entire .rodata + section as read-write. */ + .rodata2 : + { + . = ALIGN(2); + PROVIDE (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + . = ALIGN(2); + PROVIDE (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE (__init_array_end = .); + . = ALIGN(2); + PROVIDE (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE (__fini_array_end = .); + . = ALIGN(2); + *(.eh_frame_hdr) + KEEP (*(.eh_frame)) + + /* gcc uses crtbegin.o to find the start of the constructors, so + we make sure it is first. Because this is a wildcard, it + doesn't matter if the user does not actually link against + crtbegin.o; the linker won't look for a file to match a + wildcard. The wildcard also means that it doesn't matter which + directory crtbegin.o is in. */ + KEEP (*crtbegin*.o(.ctors)) + + /* We don't want to include the .ctor section from from the + crtend.o file until after the sorted ctors. The .ctor section + from the crtend file contains the end of ctors marker and it + must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > ROM + + .upper.rodata : + { + *(.upper.rodata.* .upper.rodata) + } > HIROM + + .data : + { + . = ALIGN(2); + PROVIDE (__datastart = .); + *(.lower.data.* .lower.data) + + . = ALIGN(2); + *(.either.data.* .either.data) + + . = ALIGN(2); + KEEP (*(.jcr)) + *(.data.rel.ro.local) *(.data.rel.ro*) + *(.dynamic) + + . = ALIGN(2); + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + *(.data1) + *(.got.plt) *(.got) + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + . = ALIGN(2); + *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) + + . = ALIGN(2); + _edata = .; + PROVIDE (edata = .); + PROVIDE (__dataend = .); + } > RAM AT> ROM + + /* Note that crt0 assumes this is a multiple of two; all the + start/stop symbols are also assumed word-aligned. */ + PROVIDE(__romdatastart = LOADADDR(.data)); + PROVIDE (__romdatacopysize = SIZEOF(.data)); + + .bss : + { + . = ALIGN(2); + PROVIDE (__bssstart = .); + *(.lower.bss.* .lower.bss) + . = ALIGN(2); + *(.either.bss.* .either.bss) + *(.dynbss) + *(.sbss .sbss.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(2); + *(COMMON) + PROVIDE (__bssend = .); + } > RAM + PROVIDE (__bsssize = SIZEOF(.bss)); + + /* This section contains data that is not initialised during load + or application reset. */ + .noinit (NOLOAD) : + { + . = ALIGN(2); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(2); + PROVIDE (__noinit_end = .); + } > RAM + + /* We create this section so that "end" will always be in the + RAM region (matching .stack below), even if the .bss + section is empty. */ + .heap (NOLOAD) : + { + . = ALIGN(2); + __heap_start__ = .; + _end = __heap_start__; + PROVIDE (end = .); + KEEP (*(.heap)) + _end = .; + PROVIDE (end = .); + /* This word is here so that the section is not empty, and thus + not discarded by the linker. The actual value does not matter + and is ignored. */ + LONG(0); + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > RAM + /* WARNING: Do not place anything in RAM here. + The heap section must be the last section in RAM and the stack + section must be placed at the very end of the RAM region. */ + + .stack (ORIGIN (RAM) + LENGTH(RAM)) : + { + PROVIDE (__stack = .); + *(.stack) + } + + /* This is just for crt0.S and interrupt handlers. */ + .lowtext : + { + PROVIDE (_start = .); + . = ALIGN(2); + KEEP (*(SORT(.crt_*))) + KEEP (*(.lowtext)) + } > ROM + + .lower.text : + { + . = ALIGN(2); + *(.lower.text.* .lower.text) + } > ROM + + .text : + { + . = ALIGN(2); + *(.text .stub .text.* .gnu.linkonce.t.* .text:*) + + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.interp .hash .dynsym .dynstr .gnu.version*) + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + . = ALIGN(2); + KEEP (*(.init)) + KEEP (*(.fini)) + KEEP (*(.tm_clone_table)) + } > ROM + + .upper.text : + { + . = ALIGN(2); + *(.upper.text.* .upper.text) + } > HIROM + + .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* Make sure that upper data sections are not used. */ + .upper : + { + *(.upper.bss.* .upper.bss) + *(.upper.data.* .upper.data) + ASSERT (SIZEOF(.upper) == 0, "This MCU does not support placing read/write data into high memory"); + } > HIROM + + /* The rest are all not normally part of the runtime image. */ + + .MSP430.attributes 0 : + { + KEEP (*(.MSP430.attributes)) + KEEP (*(.gnu.attributes)) + KEEP (*(__TI_build_attributes)) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF Extension. */ + .debug_macro 0 : { *(.debug_macro) } + + /DISCARD/ : { *(.note.GNU-stack) } +} + + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +INCLUDE msp430f2617_symbols.ld + diff --git a/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617_symbols.ld b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617_symbols.ld new file mode 100644 index 0000000000..084477faaf --- /dev/null +++ b/cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617_symbols.ld @@ -0,0 +1,328 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430F2617 devices. */ +/* Version: 1.208 */ + +/************************************************************ +* STANDARD BITS +************************************************************/ +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ +/************************************************************ +* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS +************************************************************/ +PROVIDE(IE1 = 0x0000); +PROVIDE(IFG1 = 0x0002); +PROVIDE(IE2 = 0x0001); +PROVIDE(IFG2 = 0x0003); +PROVIDE(UC1IE = 0x0006); +PROVIDE(UC1IFG = 0x0007); +/************************************************************ +* ADC12 +************************************************************/ +PROVIDE(ADC12CTL0 = 0x01A0); +PROVIDE(ADC12CTL1 = 0x01A2); +PROVIDE(ADC12IFG = 0x01A4); +PROVIDE(ADC12IE = 0x01A6); +PROVIDE(ADC12IV = 0x01A8); +PROVIDE(ADC12MEM0 = 0x0140); +PROVIDE(ADC12MEM1 = 0x0142); +PROVIDE(ADC12MEM2 = 0x0144); +PROVIDE(ADC12MEM3 = 0x0146); +PROVIDE(ADC12MEM4 = 0x0148); +PROVIDE(ADC12MEM5 = 0x014A); +PROVIDE(ADC12MEM6 = 0x014C); +PROVIDE(ADC12MEM7 = 0x014E); +PROVIDE(ADC12MEM8 = 0x0150); +PROVIDE(ADC12MEM9 = 0x0152); +PROVIDE(ADC12MEM10 = 0x0154); +PROVIDE(ADC12MEM11 = 0x0156); +PROVIDE(ADC12MEM12 = 0x0158); +PROVIDE(ADC12MEM13 = 0x015A); +PROVIDE(ADC12MEM14 = 0x015C); +PROVIDE(ADC12MEM15 = 0x015E); +PROVIDE(ADC12MCTL0 = 0x0080); +PROVIDE(ADC12MCTL1 = 0x0081); +PROVIDE(ADC12MCTL2 = 0x0082); +PROVIDE(ADC12MCTL3 = 0x0083); +PROVIDE(ADC12MCTL4 = 0x0084); +PROVIDE(ADC12MCTL5 = 0x0085); +PROVIDE(ADC12MCTL6 = 0x0086); +PROVIDE(ADC12MCTL7 = 0x0087); +PROVIDE(ADC12MCTL8 = 0x0088); +PROVIDE(ADC12MCTL9 = 0x0089); +PROVIDE(ADC12MCTL10 = 0x008A); +PROVIDE(ADC12MCTL11 = 0x008B); +PROVIDE(ADC12MCTL12 = 0x008C); +PROVIDE(ADC12MCTL13 = 0x008D); +PROVIDE(ADC12MCTL14 = 0x008E); +PROVIDE(ADC12MCTL15 = 0x008F); +/************************************************************ +* Basic Clock Module +************************************************************/ +PROVIDE(DCOCTL = 0x0056); +PROVIDE(BCSCTL1 = 0x0057); +PROVIDE(BCSCTL2 = 0x0058); +PROVIDE(BCSCTL3 = 0x0053); +/************************************************************ +* Comparator A +************************************************************/ +PROVIDE(CACTL1 = 0x0059); +PROVIDE(CACTL2 = 0x005A); +PROVIDE(CAPD = 0x005B); +/************************************************************ +* DAC12 +************************************************************/ +PROVIDE(DAC12_0CTL = 0x01C0); +PROVIDE(DAC12_1CTL = 0x01C2); +PROVIDE(DAC12_0DAT = 0x01C8); +PROVIDE(DAC12_1DAT = 0x01CA); +/************************************************************ +* DMA_X +************************************************************/ +PROVIDE(DMACTL0 = 0x0122); +PROVIDE(DMACTL1 = 0x0124); +PROVIDE(DMAIV = 0x0126); +PROVIDE(DMA0CTL = 0x01D0); +PROVIDE(DMA1CTL = 0x01DC); +PROVIDE(DMA2CTL = 0x01E8); +PROVIDE(DMA0SA = 0x01D2); +PROVIDE(DMA0SAL = 0x01D2); +PROVIDE(DMA0DA = 0x01D6); +PROVIDE(DMA0DAL = 0x01D6); +PROVIDE(DMA0SZ = 0x01DA); +PROVIDE(DMA1SA = 0x01DE); +PROVIDE(DMA1SAL = 0x01DE); +PROVIDE(DMA1DA = 0x01E2); +PROVIDE(DMA1DAL = 0x01E2); +PROVIDE(DMA1SZ = 0x01E6); +PROVIDE(DMA2SA = 0x01EA); +PROVIDE(DMA2SAL = 0x01EA); +PROVIDE(DMA2DA = 0x01EE); +PROVIDE(DMA2DAL = 0x01EE); +PROVIDE(DMA2SZ = 0x01F2); +/************************************************************* +* Flash Memory +*************************************************************/ +PROVIDE(FCTL1 = 0x0128); +PROVIDE(FCTL2 = 0x012A); +PROVIDE(FCTL3 = 0x012C); +PROVIDE(FCTL4 = 0x01BE); +/************************************************************ +* HARDWARE MULTIPLIER +************************************************************/ +PROVIDE(MPY = 0x0130); +PROVIDE(MPYS = 0x0132); +PROVIDE(MAC = 0x0134); +PROVIDE(MACS = 0x0136); +PROVIDE(OP2 = 0x0138); +PROVIDE(RESLO = 0x013A); +PROVIDE(RESHI = 0x013C); +PROVIDE(SUMEXT = 0x013E); +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(P1IN = 0x0020); +PROVIDE(P1OUT = 0x0021); +PROVIDE(P1DIR = 0x0022); +PROVIDE(P1IFG = 0x0023); +PROVIDE(P1IES = 0x0024); +PROVIDE(P1IE = 0x0025); +PROVIDE(P1SEL = 0x0026); +PROVIDE(P1REN = 0x0027); +PROVIDE(P2IN = 0x0028); +PROVIDE(P2OUT = 0x0029); +PROVIDE(P2DIR = 0x002A); +PROVIDE(P2IFG = 0x002B); +PROVIDE(P2IES = 0x002C); +PROVIDE(P2IE = 0x002D); +PROVIDE(P2SEL = 0x002E); +PROVIDE(P2REN = 0x002F); +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(P3IN = 0x0018); +PROVIDE(P3OUT = 0x0019); +PROVIDE(P3DIR = 0x001A); +PROVIDE(P3SEL = 0x001B); +PROVIDE(P3REN = 0x0010); +PROVIDE(P4IN = 0x001C); +PROVIDE(P4OUT = 0x001D); +PROVIDE(P4DIR = 0x001E); +PROVIDE(P4SEL = 0x001F); +PROVIDE(P4REN = 0x0011); +/************************************************************ +* DIGITAL I/O Port5/6 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(P5IN = 0x0030); +PROVIDE(P5OUT = 0x0031); +PROVIDE(P5DIR = 0x0032); +PROVIDE(P5SEL = 0x0033); +PROVIDE(P5REN = 0x0012); +PROVIDE(P6IN = 0x0034); +PROVIDE(P6OUT = 0x0035); +PROVIDE(P6DIR = 0x0036); +PROVIDE(P6SEL = 0x0037); +PROVIDE(P6REN = 0x0013); +/************************************************************ +* DIGITAL I/O Port7/8 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(P7IN = 0x0038); +PROVIDE(P7OUT = 0x003A); +PROVIDE(P7DIR = 0x003C); +PROVIDE(P7SEL = 0x003E); +PROVIDE(P7REN = 0x0014); +PROVIDE(P8IN = 0x0039); +PROVIDE(P8OUT = 0x003B); +PROVIDE(P8DIR = 0x003D); +PROVIDE(P8SEL = 0x003F); +PROVIDE(P8REN = 0x0015); +PROVIDE(PAIN = 0x0038); +PROVIDE(PAOUT = 0x003A); +PROVIDE(PADIR = 0x003C); +PROVIDE(PASEL = 0x003E); +PROVIDE(PAREN = 0x0014); +/************************************************************ +* Brown-Out, Supply Voltage Supervision (SVS) +************************************************************/ +PROVIDE(SVSCTL = 0x0055); +/************************************************************ +* Timer A3 +************************************************************/ +PROVIDE(TAIV = 0x012E); +PROVIDE(TACTL = 0x0160); +PROVIDE(TACCTL0 = 0x0162); +PROVIDE(TACCTL1 = 0x0164); +PROVIDE(TACCTL2 = 0x0166); +PROVIDE(TAR = 0x0170); +PROVIDE(TACCR0 = 0x0172); +PROVIDE(TACCR1 = 0x0174); +PROVIDE(TACCR2 = 0x0176); +/************************************************************ +* Timer B7 +************************************************************/ +PROVIDE(TBIV = 0x011E); +PROVIDE(TBCTL = 0x0180); +PROVIDE(TBCCTL0 = 0x0182); +PROVIDE(TBCCTL1 = 0x0184); +PROVIDE(TBCCTL2 = 0x0186); +PROVIDE(TBCCTL3 = 0x0188); +PROVIDE(TBCCTL4 = 0x018A); +PROVIDE(TBCCTL5 = 0x018C); +PROVIDE(TBCCTL6 = 0x018E); +PROVIDE(TBR = 0x0190); +PROVIDE(TBCCR0 = 0x0192); +PROVIDE(TBCCR1 = 0x0194); +PROVIDE(TBCCR2 = 0x0196); +PROVIDE(TBCCR3 = 0x0198); +PROVIDE(TBCCR4 = 0x019A); +PROVIDE(TBCCR5 = 0x019C); +PROVIDE(TBCCR6 = 0x019E); +/************************************************************ +* USCI +************************************************************/ +PROVIDE(UCA0CTL0 = 0x0060); +PROVIDE(UCA0CTL1 = 0x0061); +PROVIDE(UCA0BR0 = 0x0062); +PROVIDE(UCA0BR1 = 0x0063); +PROVIDE(UCA0MCTL = 0x0064); +PROVIDE(UCA0STAT = 0x0065); +PROVIDE(UCA0RXBUF = 0x0066); +PROVIDE(UCA0TXBUF = 0x0067); +PROVIDE(UCA0ABCTL = 0x005D); +PROVIDE(UCA0IRTCTL = 0x005E); +PROVIDE(UCA0IRRCTL = 0x005F); +PROVIDE(UCB0CTL0 = 0x0068); +PROVIDE(UCB0CTL1 = 0x0069); +PROVIDE(UCB0BR0 = 0x006A); +PROVIDE(UCB0BR1 = 0x006B); +PROVIDE(UCB0I2CIE = 0x006C); +PROVIDE(UCB0STAT = 0x006D); +PROVIDE(UCB0RXBUF = 0x006E); +PROVIDE(UCB0TXBUF = 0x006F); +PROVIDE(UCB0I2COA = 0x0118); +PROVIDE(UCB0I2CSA = 0x011A); +PROVIDE(UCA1CTL0 = 0x00D0); +PROVIDE(UCA1CTL1 = 0x00D1); +PROVIDE(UCA1BR0 = 0x00D2); +PROVIDE(UCA1BR1 = 0x00D3); +PROVIDE(UCA1MCTL = 0x00D4); +PROVIDE(UCA1STAT = 0x00D5); +PROVIDE(UCA1RXBUF = 0x00D6); +PROVIDE(UCA1TXBUF = 0x00D7); +PROVIDE(UCA1ABCTL = 0x00CD); +PROVIDE(UCA1IRTCTL = 0x00CE); +PROVIDE(UCA1IRRCTL = 0x00CF); +PROVIDE(UCB1CTL0 = 0x00D8); +PROVIDE(UCB1CTL1 = 0x00D9); +PROVIDE(UCB1BR0 = 0x00DA); +PROVIDE(UCB1BR1 = 0x00DB); +PROVIDE(UCB1I2CIE = 0x00DC); +PROVIDE(UCB1STAT = 0x00DD); +PROVIDE(UCB1RXBUF = 0x00DE); +PROVIDE(UCB1TXBUF = 0x00DF); +PROVIDE(UCB1I2COA = 0x017C); +PROVIDE(UCB1I2CSA = 0x017E); +/************************************************************ +* WATCHDOG TIMER +************************************************************/ +PROVIDE(WDTCTL = 0x0120); +/************************************************************ +* Calibration Data in Info Mem +************************************************************/ +PROVIDE(TLV_CHECKSUM = 0x10C0); +PROVIDE(TLV_DCO_30_TAG = 0x10F6); +PROVIDE(TLV_DCO_30_LEN = 0x10F7); +PROVIDE(TLV_ADC12_1_TAG = 0x10DA); +PROVIDE(TLV_ADC12_1_LEN = 0x10DB); +/************************************************************ +* Calibration Data in Info Mem +************************************************************/ +PROVIDE(CALDCO_16MHZ = 0x10F8); +PROVIDE(CALBC1_16MHZ = 0x10F9); +PROVIDE(CALDCO_12MHZ = 0x10FA); +PROVIDE(CALBC1_12MHZ = 0x10FB); +PROVIDE(CALDCO_8MHZ = 0x10FC); +PROVIDE(CALBC1_8MHZ = 0x10FD); +PROVIDE(CALDCO_1MHZ = 0x10FE); +PROVIDE(CALBC1_1MHZ = 0x10FF); +/************************************************************ +* Interrupt Vectors (offset from 0xFFC0) +************************************************************/ +/************************************************************ +* End of Modules +************************************************************/ diff --git a/cpu/msp430_common/vendor/update.sh b/cpu/msp430_common/vendor/update.sh new file mode 100644 index 0000000000..03a01a6864 --- /dev/null +++ b/cpu/msp430_common/vendor/update.sh @@ -0,0 +1,19 @@ +#!/bin/sh + +# This script downloads downloads and extracts the msp430 support files, +# then removes currently unused headers and linker scripts. + +set -e + +URL="https://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/exports/msp430-gcc-support-files-1.208.zip" +rm -Rf msp430-gcc-support-files + +_CPUS="$(git -C ../../.. grep -o '^CPU_MODEL.=.*430.*$' | cut -d' ' -f 3 | sort -u)" +wget $URL +unzip $(basename $URL) + +( + cd msp430-gcc-support-files/include + rm $(ls | grep -v -E '(msp430\.h|in430\.h|legacy\.h|iomacros\.h|devices.csv)' | \ + grep -v -F "${_CPUS}" ) +)