From 9214990aee0e23cd49ab160c77abbf82036880a0 Mon Sep 17 00:00:00 2001 From: Hauke Petersen Date: Wed, 19 Nov 2014 16:31:33 +0100 Subject: [PATCH 1/2] cpu/lpc1768: heavy clean-up of existing code - moved to new port structure - rewrote startup code - added implementation dummies for UART and timer - switched to atmel linkerscript - cleaned up Makefiles --- cpu/lpc1768/LPC1768.ld | 154 --- cpu/lpc1768/Makefile | 4 + cpu/lpc1768/Makefile.include | 25 +- cpu/lpc1768/atom.c | 174 --- cpu/lpc1768/cpu.c | 154 +-- cpu/lpc1768/crash.c | 68 -- cpu/lpc1768/hwtimer_arch.c | 70 ++ cpu/lpc1768/include/LPC17xx.h | 8 + cpu/lpc1768/include/cmsis.h | 25 - cpu/lpc1768/include/core_cm3.h | 1616 --------------------------- cpu/lpc1768/include/core_cmFunc.h | 616 ---------- cpu/lpc1768/include/core_cmInstr.h | 644 ----------- cpu/lpc1768/include/cpu-conf.h | 62 +- cpu/lpc1768/include/cpu.h | 44 - cpu/lpc1768/include/hwtimer_cpu.h | 44 +- cpu/lpc1768/io_arch.c | 32 + cpu/lpc1768/lpc1768-lpm.c | 36 - cpu/lpc1768/lpc1768_linkerscript.ld | 147 +++ cpu/lpc1768/lpm_arch.c | 54 + cpu/lpc1768/periph/Makefile | 3 + cpu/lpc1768/periph/timer.c | 81 ++ cpu/lpc1768/periph/uart.c | 65 ++ cpu/lpc1768/reboot_arch.c | 34 + cpu/lpc1768/startup.c | 481 ++++---- cpu/lpc1768/syscalls.c | 475 ++++---- 25 files changed, 1105 insertions(+), 4011 deletions(-) delete mode 100644 cpu/lpc1768/LPC1768.ld delete mode 100644 cpu/lpc1768/atom.c delete mode 100644 cpu/lpc1768/crash.c create mode 100644 cpu/lpc1768/hwtimer_arch.c delete mode 100644 cpu/lpc1768/include/cmsis.h delete mode 100644 cpu/lpc1768/include/core_cm3.h delete mode 100644 cpu/lpc1768/include/core_cmFunc.h delete mode 100644 cpu/lpc1768/include/core_cmInstr.h delete mode 100644 cpu/lpc1768/include/cpu.h create mode 100644 cpu/lpc1768/io_arch.c delete mode 100644 cpu/lpc1768/lpc1768-lpm.c create mode 100644 cpu/lpc1768/lpc1768_linkerscript.ld create mode 100644 cpu/lpc1768/lpm_arch.c create mode 100644 cpu/lpc1768/periph/Makefile create mode 100644 cpu/lpc1768/periph/timer.c create mode 100644 cpu/lpc1768/periph/uart.c create mode 100644 cpu/lpc1768/reboot_arch.c diff --git a/cpu/lpc1768/LPC1768.ld b/cpu/lpc1768/LPC1768.ld deleted file mode 100644 index 0e7d2518d8..0000000000 --- a/cpu/lpc1768/LPC1768.ld +++ /dev/null @@ -1,154 +0,0 @@ -/* Linker script for mbed LPC1768 */ - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K - RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 - - USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K - ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - __sidata = __etext; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - __heap_size = ORIGIN(RAM) + LENGTH(RAM) - . ;/*- __stack_size;*/ - .heap : - { - PROVIDE(__heap_start = .); - __end__ = .; - end = __end__; - *(.heap*) - . = . + __heap_size; - PROVIDE(__heap_max = .); - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/cpu/lpc1768/Makefile b/cpu/lpc1768/Makefile index 08e25a221a..55e50d2099 100644 --- a/cpu/lpc1768/Makefile +++ b/cpu/lpc1768/Makefile @@ -1,3 +1,7 @@ +# define the module that is build MODULE = cpu +# add a list of subdirectories, that should also be build +DIRS = periph $(CORTEX_COMMON) + include $(RIOTBASE)/Makefile.base diff --git a/cpu/lpc1768/Makefile.include b/cpu/lpc1768/Makefile.include index bfc25dabb9..2dacfc1fd9 100644 --- a/cpu/lpc1768/Makefile.include +++ b/cpu/lpc1768/Makefile.include @@ -1,3 +1,26 @@ -INCLUDES += -I$(RIOTBASE)/cpu/lpc1768/include +# this CPU implementation is using the new core/CPU interface +export CFLAGS += -DCOREIF_NG=1 +# tell the build system that the CPU depends on the Cortex-M common files +export USEMODULE += cortex-m3_common + +# define path to cortex-m common module, which is needed for this CPU +export CORTEX_COMMON = $(RIOTCPU)/cortex-m3_common/ + +# define the linker script to use for this CPU. The CPU_MODEL variable is defined in the +# board's Makefile.include. This enables multiple STMF0 controllers with different memory to +# use the same code-base. +export LINKERSCRIPT = $(RIOTCPU)/$(CPU)/lpc1768_linkerscript.ld + +# include CPU specific includes +export INCLUDES += -I$(RIOTCPU)/$(CPU)/include + +# add the CPU specific system calls implementations for the linker export UNDEF += $(BINDIR)cpu/syscalls.o +export UNDEF += $(BINDIR)cpu/startup.o + +# export the peripheral drivers to be linked into the final binary +export USEMODULE += periph + +# CPU depends on the cortex-m common module, so include it +include $(CORTEX_COMMON)Makefile.include diff --git a/cpu/lpc1768/atom.c b/cpu/lpc1768/atom.c deleted file mode 100644 index 575162dab4..0000000000 --- a/cpu/lpc1768/atom.c +++ /dev/null @@ -1,174 +0,0 @@ -/** - * CPU speficic RIOT kernel function for NXP LPC1768 - * - * Copyright (C) 2013 Oliver Hahm - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - * - * @ingroup lpc1768 - * @{ - * @file atom.c - * @author Stefan Pfeiffer - * @author Oliver Hahm - * @} - */ - -#include "sched.h" -#include "cpu.h" -#include "irq.h" -#include "kernel_internal.h" - -NORETURN void sched_task_return(void); - -unsigned int atomic_set_return(unsigned int* p, unsigned int uiVal) { - //unsigned int cspr = disableIRQ(); //crashes - dINT(); - unsigned int uiOldVal = *p; - *p = uiVal; - //restoreIRQ(cspr); //crashes - eINT(); - return uiOldVal; -} - -NORETURN void cpu_switch_context_exit(void){ - sched_run(); - sched_task_return(); -} - - -void thread_yield_higher(void) { - asm("svc 0x01\n"); -} - - -__attribute__((naked)) -void SVC_Handler(void) -{ - save_context(); - asm("bl sched_run"); - /* call scheduler update sched_active_thread variable with pdc of next thread - * the thread that has higest priority and is in PENDING state */ - restore_context(); -} - - /* kernel functions */ -void ctx_switch(void) -{ - /* Save return address on stack */ - /* stmfd sp!, {lr} */ - - /* disable interrupts */ - /* mov lr, #NOINT|SVCMODE */ - /* msr CPSR_c, lr */ - /* cpsid i */ - - /* save other register */ - asm("nop"); - - asm("mov r12, sp"); - asm("stmfd r12!, {r4-r11}"); - - /* save user mode stack pointer in *sched_active_thread */ - asm("ldr r1, =sched_active_thread"); /* r1 = &sched_active_thread */ - asm("ldr r1, [r1]"); /* r1 = *r1 = sched_active_thread */ - asm("str r12, [r1]"); /* store stack pointer in tasks pdc*/ - - sched_task_return(); -} -/* call scheduler so sched_active_thread points to the next task */ -NORETURN void sched_task_return(void) -{ - /* load pdc->stackpointer in r0 */ - asm("ldr r0, =sched_active_thread"); /* r0 = &sched_active_thread */ - asm("ldr r0, [r0]"); /* r0 = *r0 = sched_active_thread */ - asm("ldr sp, [r0]"); /* sp = r0 restore stack pointer*/ - asm("pop {r4}"); /* skip exception return */ - asm(" pop {r4-r11}"); - asm(" pop {r0-r3,r12,lr}"); /* simulate register restor from stack */ -// asm("pop {r4}"); /*foo*/ - asm("pop {pc}"); - - UNREACHABLE(); -} -/* - * cortex m4 knows stacks and handles register backups - * - * so use different stack frame layout - * - * - * with float storage - * ------------------------------------------------------------------------------------------------------------------------------------ - * | R0 | R1 | R2 | R3 | LR | PC | xPSR | S0 | S1 | S2 | S3 | S4 | S5 | S6 | S7 | S8 | S9 | S10 | S11 | S12 | S13 | S14 | S15 | FPSCR | - * ------------------------------------------------------------------------------------------------------------------------------------ - * - * without - * - * -------------------------------------- - * | R0 | R1 | R2 | R3 | LR | PC | xPSR | - * -------------------------------------- - * - * - */ -char * thread_stack_init(void *(*task_func)(void *), void *arg, void *stack_start, int stack_size) -{ - unsigned int * stk; - stk = (unsigned int *) ((uintptr_t) stack_start + stack_size); - - /* marker */ - stk--; - *stk = 0x77777777; - - //FIXME FPSCR - stk--; - *stk = (unsigned int) 0; - - //S0 - S15 - for (int i = 15; i >= 0; i--) { - stk--; - *stk = i; - } - - //FIXME xPSR - stk--; - *stk = (unsigned int) 0x01000200; - - //program counter - stk--; - *stk = (unsigned int) task_func; - - /* link register */ - stk--; - *stk = (unsigned int) 0x0; - - /* r12 */ - stk--; - *stk = (unsigned int) 0; - - /* r1 - r3 */ - for (int i = 3; i >= 1; i--) { - stk--; - *stk = i; - } - - /* r0 -> thread function parameter */ - stk--; - *stk = (unsigned int) arg; - - /* r11 - r4 */ - for (int i = 11; i >= 4; i--) { - stk--; - *stk = i; - } - - /* foo */ - /*stk--; - *stk = (unsigned int) 0xDEADBEEF;*/ - - /* lr means exception return code */ - stk--; - *stk = (unsigned int) 0xfffffff9; // return to taskmode main stack pointer - - return (char*) stk; -} diff --git a/cpu/lpc1768/cpu.c b/cpu/lpc1768/cpu.c index 6f706ff898..b983cec4e8 100644 --- a/cpu/lpc1768/cpu.c +++ b/cpu/lpc1768/cpu.c @@ -1,145 +1,29 @@ -/** - * CPU specific functions for the RIOT scheduler on NXP LPC1768 - * - * Copyright (C) 2013 Oliver Hahm +/* + * Copyright (C) 2014 Freie Universität Berlin * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. - * - * @file cpu.c - * @author Kaspar Schleiser - * @author Oliver Hahm */ -#include +/** + * @ingroup cpu_lpc1768 + * @{ + * + * @file + * @brief Implementation of the CPU initialization + * + * @author Hauke Petersen + * @} + */ + #include "cpu.h" -#include "kernel.h" -#define ENABLE_DEBUG (0) -#include "debug.h" - -int inISR(void) +/** + * @brief Initialize the CPU, set IRQ priorities + */ +void cpu_init(void) { - return (__get_IPSR() & 0xFF); -} - -unsigned int disableIRQ(void) -{ - // FIXME PRIMASK is the old CPSR (FAULTMASK ??? BASEPRI ???) - //PRIMASK lesen - unsigned int uiPriMask = __get_PRIMASK(); - __disable_irq(); - return uiPriMask; -} - -unsigned enableIRQ(void) -{ - unsigned int uiPriMask = __get_PRIMASK(); - __enable_irq(); - return uiPriMask; -} - -void restoreIRQ(unsigned oldPRIMASK) -{ - //PRIMASK lesen setzen - __set_PRIMASK(oldPRIMASK); -} - - -__attribute__((naked)) -void HardFault_Handler(void) { - DEBUG("HARD FAULT\n"); - while(1); -} - -__attribute__((naked)) -void BusFault_Handler(void) { - DEBUG("BusFault_Handler\n"); - while(1); -} - -__attribute__((naked)) -void Usage_Handler(void) { - DEBUG("Usage FAULT\n"); - while(1); -} - -__attribute__((naked)) -void WWDG_Handler(void) { - DEBUG("WWDG FAULT\n"); - while(1); -} - -void dINT(void) -{ - __disable_irq(); -} - -void eINT(void) -{ - __enable_irq(); -} - -void save_context(void) -{ - /* {r0-r3,r12,LR,PC,xPSR} are saved automatically on exception entry */ - asm("push {r4-r11}"); - /* save unsaved registers */ - asm("push {LR}"); - /* save exception return value */ - - asm("ldr r1, =sched_active_thread"); - /* load address of currend pdc */ - asm("ldr r1, [r1]"); - /* deref pdc */ - asm("str sp, [r1]"); - /* write sp to pdc->sp means current threads stack pointer */ -} - -void restore_context(void) -{ - asm("ldr r0, =sched_active_thread"); - /* load address of currend pdc */ - asm("ldr r0, [r0]"); - /* deref pdc */ - asm("ldr sp, [r0]"); - /* load pdc->sp to sp register */ - - asm("pop {r0}"); - /* restore exception retrun value from stack */ - asm("pop {r4-r11}"); - /* load unloaded register */ -// asm("pop {r4}"); /*foo*/ - asm("bx r0"); /* load exception return value to pc causes end of exception*/ - /* {r0-r3,r12,LR,PC,xPSR} are restored automatically on exception return */ -} - -#define USR_RESET (0x102) -#define SWI (0xAB) - -__attribute__((naked,noreturn)) void arm_reset(void) -{ - int value; - - asm volatile ( - "mov r0, %1" "\n\t" - "mov r1, %2" "\n\t" - "bkpt" " %a3" "\n\t" - "mov %0, r0" - : "=r" (value) /* output operands */ - : "r" USR_RESET, "r" NULL, "i" SWI /* input operands */ - : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* list of clobbered registers */ - ); -} - -int reboot_arch(int mode) -{ - (void) mode; - - while (1) { - arm_reset(); - } - - return -1; + /* set pendSV interrupt to lowest possible priority */ + NVIC_SetPriority(PendSV_IRQn, 0xff); } diff --git a/cpu/lpc1768/crash.c b/cpu/lpc1768/crash.c deleted file mode 100644 index f8a3d20e61..0000000000 --- a/cpu/lpc1768/crash.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2014 INRIA - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup core_util - * @{ - * - * @file crash.c - * @brief Crash handling functions implementation for LPC1768 MCU - * (actually, a copy from 'arm_common'...) - * - * @author Kévin Roussel - */ - -#include "cpu.h" -#include "lpm.h" -#include "crash.h" - -#include -#include - -/* "public" variables holding the crash data */ -char panic_str[80]; -int panic_code; - -/* flag preventing "recursive crash printing loop" */ -static int crashed = 0; - -/* WARNING: this function NEVER returns! */ -NORETURN void core_panic(int crash_code, const char *message) -{ - /* copy panic datas to "public" global variables */ - panic_code = crash_code; - strncpy(panic_str, message, 80); - /* print panic message to console (if possible) */ - if (crashed == 0) { - crashed = 1; - puts("******** SYSTEM FAILURE ********\n"); - puts(message); -#if DEVELHELP - puts("******** RIOT HALTS HERE ********\n"); -#else - puts("******** RIOT WILL REBOOT ********\n"); -#endif - puts("\n\n"); - } - /* disable watchdog and all possible sources of interrupts */ - //TODO - dINT(); -#if DEVELHELP - /* enter infinite loop, into deepest possible sleep mode */ - while (1) { - lpm_set(LPM_OFF); - } -#else - /* DEVELHELP not set => reboot system */ - (void) reboot(RB_AUTOBOOT); -#endif - - /* tell the compiler that we won't return from this function - (even if we actually won't even get here...) */ - UNREACHABLE(); -} diff --git a/cpu/lpc1768/hwtimer_arch.c b/cpu/lpc1768/hwtimer_arch.c new file mode 100644 index 0000000000..1587efef1d --- /dev/null +++ b/cpu/lpc1768/hwtimer_arch.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_lpc1768 + * @{ + * + * @file + * @brief Implementation of the kernel's hwtimer interface + * + * The hardware timer implementation uses the Cortex build-in system timer as back-end. + * + * @author Hauke Petersen + * + * @} + */ + +#include "arch/hwtimer_arch.h" +#include "periph/timer.h" +#include "board.h" +#include "thread.h" + +void irq_handler(int channel); +void (*timeout_handler)(int); + +void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) +{ + timeout_handler = handler; + timer_init(HW_TIMER, 1, &irq_handler); +} + +void hwtimer_arch_enable_interrupt(void) +{ + timer_irq_enable(HW_TIMER); +} + +void hwtimer_arch_disable_interrupt(void) +{ + timer_irq_disable(HW_TIMER); +} + +void hwtimer_arch_set(unsigned long offset, short timer) +{ + timer_set(HW_TIMER, timer, offset); +} + +void hwtimer_arch_set_absolute(unsigned long value, short timer) +{ + timer_set_absolute(HW_TIMER, timer, value); +} + +void hwtimer_arch_unset(short timer) +{ + timer_clear(HW_TIMER, timer); +} + +unsigned long hwtimer_arch_now(void) +{ + return timer_read(HW_TIMER); +} + +void irq_handler(int channel) +{ + timeout_handler((short)(channel)); +} diff --git a/cpu/lpc1768/include/LPC17xx.h b/cpu/lpc1768/include/LPC17xx.h index c19aac542a..497e7a8e4b 100644 --- a/cpu/lpc1768/include/LPC17xx.h +++ b/cpu/lpc1768/include/LPC17xx.h @@ -26,6 +26,10 @@ #ifndef __LPC17xx_H__ #define __LPC17xx_H__ +#ifdef __cplusplus +extern "C" { +#endif + /* * ========================================================================== * ---------- Interrupt Number Definition ----------------------------------- @@ -1030,4 +1034,8 @@ typedef struct #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) +#ifdef __cplusplus +} +#endif + #endif // __LPC17xx_H__ diff --git a/cpu/lpc1768/include/cmsis.h b/cpu/lpc1768/include/cmsis.h deleted file mode 100644 index c705982a15..0000000000 --- a/cpu/lpc1768/include/cmsis.h +++ /dev/null @@ -1,25 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC1768 specifics - */ - -/** - * @defgroup CMSIS - * @brief Cortex Microcontroller Software Interface Standard - * @ingroup cpu - * @{ - * - * @file cmsis.h - * @brief CMSIS interface pulling in LPC1768 specifics - */ - - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC17xx.h" -#include "cmsis_nvic.h" - -#endif -/** @} */ diff --git a/cpu/lpc1768/include/core_cm3.h b/cpu/lpc1768/include/core_cm3.h deleted file mode 100644 index fba51811c1..0000000000 --- a/cpu/lpc1768/include/core_cm3.h +++ /dev/null @@ -1,1616 +0,0 @@ -/** - * @ingroup CMSIS - * - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.02 - * @date 16. July 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - \ingroup CMSIS - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - * \ingroup CMSIS - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference - * \ingroup CMSIS -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/cpu/lpc1768/include/core_cmFunc.h b/cpu/lpc1768/include/core_cmFunc.h deleted file mode 100644 index 2720241c31..0000000000 --- a/cpu/lpc1768/include/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.02 - * @date 24. May 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - -#include - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl asm("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl asm("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR asm("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR asm("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR asm("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer asm("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer asm("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer asm("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer asm("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask asm("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask asm("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri asm("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri asm("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask asm("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask asm("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr asm("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr asm("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - asm volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - asm volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - asm volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - asm volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - asm volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - asm volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - asm volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - asm volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - asm volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - asm volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - asm volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - asm volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - asm volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - asm volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - asm volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - asm volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - asm volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - asm volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - asm volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - asm volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - asm volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/cpu/lpc1768/include/core_cmInstr.h b/cpu/lpc1768/include/core_cmInstr.h deleted file mode 100644 index d02bf6357b..0000000000 --- a/cpu/lpc1768/include/core_cmInstr.h +++ /dev/null @@ -1,644 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.03 - * @date 29. August 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - - \ingroup CMSIS - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/cpu/lpc1768/include/cpu-conf.h b/cpu/lpc1768/include/cpu-conf.h index 115727ed74..23d65c1eae 100644 --- a/cpu/lpc1768/include/cpu-conf.h +++ b/cpu/lpc1768/include/cpu-conf.h @@ -1,18 +1,64 @@ -#ifndef CPU_CONF_H -#define CPU_CONF_H +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup cpu_lpc1768 NXP LPC1768 + * @ingroup cpu + * @brief CPU specific implementations for the NXP LPC1768 cpu + * @{ + * + * @file + * @brief CPU specific hwtimer configuration options + *12 + * @author Hauke Petersen + */ + +#ifndef __CPU_CONF_H +#define __CPU_CONF_H + +#include "LPC17xx.h" + +#ifdef __cplusplus +extern "C" { +#endif /** * @name Kernel configuration + * + * The absolute minimum stack size is 140 byte (68 byte for the tcb + 72 byte + * for a complete context save). + * + * TODO: measure and adjust for the Cortex-M3 * @{ */ -#define KERNEL_CONF_STACKSIZE_PRINTF (4096) +#define KERNEL_CONF_STACKSIZE_PRINTF (1024) + #ifndef KERNEL_CONF_STACKSIZE_DEFAULT -#define KERNEL_CONF_STACKSIZE_DEFAULT 1500 +#define KERNEL_CONF_STACKSIZE_DEFAULT (1024) #endif -#define KERNEL_CONF_STACKSIZE_IDLE 1000 - -#define UART0_BUFSIZE (128) +#define KERNEL_CONF_STACKSIZE_IDLE (256) /** @} */ -#endif /* CPU_CONF_H */ +/** + * @name UART0 buffer size definition for compatibility reasons + * + * TODO: remove once the remodeling of the uart0 driver is done + * @{ + */ +#ifndef UART0_BUFSIZE +#define UART0_BUFSIZE (128) +#endif +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CPU_CONF_H */ +/** @} */ diff --git a/cpu/lpc1768/include/cpu.h b/cpu/lpc1768/include/cpu.h deleted file mode 100644 index 96fcca4a38..0000000000 --- a/cpu/lpc1768/include/cpu.h +++ /dev/null @@ -1,44 +0,0 @@ -/** - * Copyright (C) 2014 Oliver Hahm - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -#ifndef CPU_H -#define CPU_H - -/** - * @defgroup lpc1768 NXP LPC1768 - * @brief NXP LPC1768 specific code - * @ingroup cpu - * @{ - * @author Oliver Hahm - */ - -#include "LPC17xx.h" -#include "core_cm3.h" -#include "core_cmFunc.h" - -extern void dINT(void); -extern void eINT(void); - -/** - * @brief Save the thread's context - */ -void save_context(void); - -/** - * @brief Restores the before saved context of a thread - */ -void restore_context(void); - -/** - * @brief Let the scheduler yield - */ -void thread_yield_higher(void); - -/** @} */ - -#endif /* CPU_H */ diff --git a/cpu/lpc1768/include/hwtimer_cpu.h b/cpu/lpc1768/include/hwtimer_cpu.h index d91982eb49..e001d14273 100644 --- a/cpu/lpc1768/include/hwtimer_cpu.h +++ b/cpu/lpc1768/include/hwtimer_cpu.h @@ -1,8 +1,40 @@ -#ifndef HWTIMER_CPU_H_ -#define HWTIMER_CPU_H_ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ -#define HWTIMER_MAXTIMERS 3 -#define HWTIMER_SPEED 1000000 -#define HWTIMER_MAXTICKS (0xFFFFFFFF) +/** + * @ingroup cpu_lpc1768 + * @{ + * + * @file + * @brief CPU specific hwtimer configuration options + * + * @author Hauke Petersen + */ -#endif /* HWTIMER_CPU_H_ */ +#ifndef __HWTIMER_CPU_H +#define __HWTIMER_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Hardware timer configuration + * @{ + */ +#define HWTIMER_MAXTIMERS 4 /**< the CPU implementation supports 4 HW timers */ +#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */ +#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< 32-bit timer */ +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HWTIMER_CPU_H */ +/** @} */ diff --git a/cpu/lpc1768/io_arch.c b/cpu/lpc1768/io_arch.c new file mode 100644 index 0000000000..0e4827b7cd --- /dev/null +++ b/cpu/lpc1768/io_arch.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_lpc1768 + * @{ + * + * @file + * @brief Implementation of the kernel's architecture dependent IO interface + * + * @author Hauke Petersen + * + * @} + */ + +#include "board.h" +#include "arch/io_arch.h" +#include "periph/uart.h" + +int io_arch_puts(char *data, int size) +{ + int i = 0; + for (; i < size; i++) { + uart_write_blocking(STDIO, data[i]); + } + return i; +} diff --git a/cpu/lpc1768/lpc1768-lpm.c b/cpu/lpc1768/lpc1768-lpm.c deleted file mode 100644 index 5856ab1ace..0000000000 --- a/cpu/lpc1768/lpc1768-lpm.c +++ /dev/null @@ -1,36 +0,0 @@ -/** - * LPM dummys for NXP LPC1768 - * - * Copyright (C) 2013 Oliver Hahm - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - * - * @ingroup lpc1768 - * @{ - * @file lpc1768-lpm.c - * @author Oliver Hahm - * @} - */ - -#include -#include -#include "lpm.h" - -/* lpm is accessed before memory init and initialized separately through code */ -__attribute__((section(".noinit"))) -static enum lpm_mode lpm; - -// TODO -enum lpm_mode lpm_set(enum lpm_mode target) { - enum lpm_mode last_lpm = lpm; - - lpm = target; - - return last_lpm; -} - -void lpm_awake(void) { - lpm = LPM_ON; -} diff --git a/cpu/lpc1768/lpc1768_linkerscript.ld b/cpu/lpc1768/lpc1768_linkerscript.ld new file mode 100644 index 0000000000..4f1ef3fb2e --- /dev/null +++ b/cpu/lpc1768/lpc1768_linkerscript.ld @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K + ram (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8) + usb_ram (rwx) : ORIGIN = 0x2007C000, LENGTH = 16K + eth_ram (rwx) : ORIGIN = 0x20080000, LENGTH = 16K +} + +/* The stack size used by the application. NOTE: you need to adjust */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0xa00 ; + + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + . = ALIGN(4); + _sheap = . ; + _eheap = ORIGIN(ram) + LENGTH(ram); +} diff --git a/cpu/lpc1768/lpm_arch.c b/cpu/lpc1768/lpm_arch.c new file mode 100644 index 0000000000..24fc58b0f9 --- /dev/null +++ b/cpu/lpc1768/lpm_arch.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_lpc1768 + * @{ + * + * @file + * @brief Implementation of the kernels power management interface + * + * @author Hauke Petersen + * + * @} + */ + +#include "cpu.h" +#include "arch/lpm_arch.h" + +void lpm_arch_init(void) +{ + /* TODO */ +} + +enum lpm_mode lpm_arch_set(enum lpm_mode target) +{ + /* TODO */ + return 0; +} + +enum lpm_mode lpm_arch_get(void) +{ + /* TODO */ + return 0; +} + +void lpm_arch_awake(void) +{ + /* TODO*/ +} + +void lpm_arch_begin_awake(void) +{ + /* TODO */ +} + +void lpm_arch_end_awake(void) +{ + /* TODO */ +} diff --git a/cpu/lpc1768/periph/Makefile b/cpu/lpc1768/periph/Makefile new file mode 100644 index 0000000000..6d1887b640 --- /dev/null +++ b/cpu/lpc1768/periph/Makefile @@ -0,0 +1,3 @@ +MODULE = periph + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/lpc1768/periph/timer.c b/cpu/lpc1768/periph/timer.c new file mode 100644 index 0000000000..6ff6b42583 --- /dev/null +++ b/cpu/lpc1768/periph/timer.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_lpc1768 + * @{ + * + * @file + * @brief Implementation of the low-level timer driver for the LPC1768 + * + * @author Hauke Petersen + * @} + */ + +#include "periph_conf.h" +#include "periph/timer.h" + +/* guard file in case no timers are defined */ +#if TIMER_0_EN + +int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int)) +{ + /* not yet implemented */ + return -1; +} + +int timer_set(tim_t dev, int channel, unsigned int timeout) +{ + /* not yet implemented */ + return -1; +} + +int timer_set_absolute(tim_t dev, int channel, unsigned int value) +{ + /* not yet implemented */ + return -1; +} + +int timer_clear(tim_t dev, int channel) +{ + /* not yet implemented */ + return -1; +} + +unsigned int timer_read(tim_t dev) +{ + /* not yet implemented */ + return 0; +} + +void timer_start(tim_t dev) +{ + /* not yet implemented */ +} + +void timer_stop(tim_t dev) +{ + /* not yet implemented */ +} + +void timer_irq_enable(tim_t dev) +{ + /* not yet implemented */ +} + +void timer_irq_disable(tim_t dev) +{ + /* not yet implemented */ +} + +void timer_reset(tim_t dev) +{ + /* not yet implemented */ +} + +#endif /* TIMER_0_EN */ diff --git a/cpu/lpc1768/periph/uart.c b/cpu/lpc1768/periph/uart.c new file mode 100644 index 0000000000..2356e641c2 --- /dev/null +++ b/cpu/lpc1768/periph/uart.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_lpc1768 + * @{ + * + * @file + * @brief Implementation of the low-level UART driver for the LPC1768 + * + * @author Hauke Petersen + * @} + */ + +#include +#include + +#include "cpu.h" +#include "periph/uart.h" +#include "periph_conf.h" + +/* guard the file in case no UART is defined */ +#if UART_0_EN + +int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg) +{ + /* not yet implemented */ + return -1; +} + +int uart_init_blocking(uart_t uart, uint32_t baudrate) +{ + /* not yet implemented */ + return -1; +} + +void uart_tx_begin(uart_t uart) +{ + /* not yet implemented */ +} + +int uart_write(uart_t uart, char data) +{ + /* not yet implemented */ + return -1; +} + +int uart_read_blocking(uart_t uart, char *data) +{ + /* not yet implemented */ + return -1; +} + +int uart_write_blocking(uart_t uart, char data) +{ + /* not yet implemented */ + return -1; +} + +#endif /* UART_0_EN */ diff --git a/cpu/lpc1768/reboot_arch.c b/cpu/lpc1768/reboot_arch.c new file mode 100644 index 0000000000..ca12bb1b51 --- /dev/null +++ b/cpu/lpc1768/reboot_arch.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_lpc1768 + * @{ + * + * @file + * @brief Implementation of the kernels reboot interface + * + * @author Oliver Hahm + * @author Hauke Petersen + * + * @} + */ + +#include + +#include "arch/reboot_arch.h" +#include "cpu.h" + +int reboot_arch(int mode) +{ + printf("Going into reboot, mode %i\n", mode); + + NVIC_SystemReset(); + + return 0; +} diff --git a/cpu/lpc1768/startup.c b/cpu/lpc1768/startup.c index dad6cb7463..24c9a5d4b6 100644 --- a/cpu/lpc1768/startup.c +++ b/cpu/lpc1768/startup.c @@ -1,310 +1,215 @@ -/****************************************************************************** - * @file: startup.c - * @purpose: CMSIS Cortex-M3 Core Device Startup File - * @version: V1.02 - * @date: 9. November 2013 +/* + * Copyright (C) 2014 Freie Universität Berlin * - * @note: Integrated and adopted for RIOT by Oliver Hahm. - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * Copyright (C) 2013 Oliver Hahm - * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ /** - * @ingroup lpc1768 + * @ingroup cpu_lpc1768 * @{ + * + * @file + * @brief Startup code and interrupt vector definition + * + * @author Hauke Petersen + * + * @} */ +#include +#include + /** - * @file - * @brief lpc1768 startup code - * - * @author Oliver Hahm - * + * memory markers as defined in the linker script */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; -#include "LPC17xx.h" -#include "kernel_internal.h" -#define WEAK __attribute__ ((weak)) +/** + * @brief functions for initializing the board, std-lib and kernel + */ +extern void board_init(void); +extern void kernel_init(void); +extern void __libc_init_array(void); -/***************************************************************************** +/** + * @brief This function is the entry point after a system reset * - * Forward declaration of the default fault handlers. - * - *****************************************************************************/ -/* System exception vector handler */ -void WEAK Reset_Handler(void); /* Reset Handler */ -void WEAK NMI_Handler(void); /* NMI Handler */ -void WEAK HardFault_Handler(void); /* Hard Fault Handler */ -void WEAK MemManage_Handler(void); /* MPU Fault Handler */ -void WEAK BusFault_Handler(void); /* Bus Fault Handler */ -void WEAK UsageFault_Handler(void); /* Usage Fault Handler */ -void WEAK SVC_Handler(void); /* SVCall Handler */ -void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */ -void WEAK PendSV_Handler(void); /* PendSV Handler */ -void WEAK SysTick_Handler(void); /* SysTick Handler */ - -/* External interrupt vector handler */ -void WEAK WDT_IRQHandler(void); /* Watchdog Timer */ -void WEAK TIMER0_IRQHandler(void); /* Timer0 */ -void WEAK TIMER1_IRQHandler(void); /* Timer1 */ -void WEAK TIMER2_IRQHandler(void); /* Timer2 */ -void WEAK TIMER3_IRQHandler(void); /* Timer3 */ -void WEAK UART0_IRQHandler(void); /* UART0 */ -void WEAK UART1_IRQHandler(void); /* UART1 */ -void WEAK UART2_IRQHandler(void); /* UART2 */ -void WEAK UART3_IRQHandler(void); /* UART3 */ -void WEAK PWM1_IRQHandler(void); /* PWM1 */ -void WEAK I2C0_IRQHandler(void); /* I2C0 */ -void WEAK I2C1_IRQHandler(void); /* I2C1 */ -void WEAK I2C2_IRQHandler(void); /* I2C2 */ -void WEAK SPI_IRQHandler(void); /* SPI */ -void WEAK SSP0_IRQHandler(void); /* SSP0 */ -void WEAK SSP1_IRQHandler(void); /* SSP1 */ -void WEAK PLL0_IRQHandler(void); /* PLL0 (Main PLL) */ -void WEAK RTC_IRQHandler(void); /* Real Time Clock */ -void WEAK EINT0_IRQHandler(void); /* External Interrupt 0 */ -void WEAK EINT1_IRQHandler(void); /* External Interrupt 1 */ -void WEAK EINT2_IRQHandler(void); /* External Interrupt 2 */ -void WEAK EINT3_IRQHandler(void); /* External Interrupt 3 */ -void WEAK ADC_IRQHandler(void); /* A/D Converter */ -void WEAK BOD_IRQHandler(void); /* Brown Out Detect */ -void WEAK USB_IRQHandler(void); /* USB */ -void WEAK CAN_IRQHandler(void); /* CAN */ -void WEAK DMA_IRQHandler(void); /* GP DMA */ -void WEAK I2S_IRQHandler(void); /* I2S */ -void WEAK ENET_IRQHandler(void); /* Ethernet */ -void WEAK RIT_IRQHandler(void); /* Repetitive Interrupt Timer */ -void WEAK MCPWM_IRQHandler(void); /* Motor Control PWM */ -void WEAK QEI_IRQHandler(void); /* Quadrature Encoder Interface */ -void WEAK PLL1_IRQHandler(void); /* PLL1 (USB PLL) */ - - -/* Exported constants --------------------------------------------------------*/ -extern unsigned long __etext; -extern unsigned long __sidata; /* start address for the initialization values of the .data section. defined in linker script */ -extern unsigned long __data_start__; /* start address for the .data section. defined in linker script */ -extern unsigned long __data_end__; /* end address for the .data section. defined in linker script */ - -extern unsigned long __bss_start__; /* start address for the .bss section. defined in linker script */ -extern unsigned long __bss_end__; /* end address for the .bss section. defined in linker script */ - -extern void _estack; /* init value for the stack pointer. defined in linker script */ - - -/* function prototypes ------------------------------------------------------*/ -void Reset_Handler(void) __attribute__((__interrupt__)); -extern void _CPUregTestPOST (void); - -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ -#define STACK_SIZE 0x00000200 - -__attribute__ ((section(".stackarea"))) -/* static */ unsigned long pulStack[STACK_SIZE]; - - -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = + * After a system reset, the following steps are necessary and carried out: + * 1. load data section from flash to ram + * 2. overwrite uninitialized data section (BSS) with zeros + * 3. initialize the newlib + * 4. initialize the board (sync clock, setup std-IO) + * 5. initialize and start RIOTs kernel + */ +void reset_handler(void) { - /* &_estack, // The initial stack pointer */ - (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), // The initial stack pointer - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ + uint32_t *dst; + uint32_t *src = &_etext; - // External Interrupts - WDT_IRQHandler, /* Watchdog Timer */ - TIMER0_IRQHandler, /* Timer0 */ - TIMER1_IRQHandler, /* Timer1 */ - TIMER2_IRQHandler, /* Timer2 */ - TIMER3_IRQHandler, /* Timer3 */ - UART0_IRQHandler, /* UART0 */ - UART1_IRQHandler, /* UART1 */ - UART2_IRQHandler, /* UART2 */ - UART3_IRQHandler, /* UART3 */ - PWM1_IRQHandler, /* PWM1 */ - I2C0_IRQHandler, /* I2C0 */ - I2C1_IRQHandler, /* I2C1 */ - I2C2_IRQHandler, /* I2C2 */ - SPI_IRQHandler, /* SPI */ - SSP0_IRQHandler, /* SSP0 */ - SSP1_IRQHandler, /* SSP1 */ - PLL0_IRQHandler, /* PLL0 (Main PLL) */ - RTC_IRQHandler, /* Real Time Clock */ - EINT0_IRQHandler, /* External Interrupt 0 */ - EINT1_IRQHandler, /* External Interrupt 1 */ - EINT2_IRQHandler, /* External Interrupt 2 */ - EINT3_IRQHandler, /* External Interrupt 3 */ - ADC_IRQHandler, /* A/D Converter */ - BOD_IRQHandler, /* Brown Out Detect */ - USB_IRQHandler, /* USB */ - CAN_IRQHandler, /* CAN */ - DMA_IRQHandler, /* GP DMA */ - I2S_IRQHandler, /* I2S */ - ENET_IRQHandler, /* Ethernet */ - RIT_IRQHandler, /* Repetitive Interrupt Timer */ - MCPWM_IRQHandler, /* Motor Control PWM */ - QEI_IRQHandler, /* Quadrature Encoder Interface */ - PLL1_IRQHandler, /* PLL1 (USB PLL) */ -}; - -/******************************************************************************* -* Function Name : Reset_Handler -* Description : This is the code that gets called when the processor first starts execution -* following a reset event. Only the absolutely necessary set is performed, -* after which the application supplied main() routine is called. -* Input : -* Output : -* Return : -*******************************************************************************/ -void Reset_Handler(void) -{ - unsigned long *pulDest; - - /* - * This used for cleaning AHBRAM0 section - */ -#if 0 - for (pulDest = ((unsigned long *)AHBRAM0_BASE); \ - pulDest < ((unsigned long *)(AHBRAM0_BASE + AHBRAM0_SIZE)); \ - pulDest++){ - *(pulDest++) = 0; - } -#endif - - /* - * This used for cleaning AHBRAM1 section - */ -#if 0 - for (pulDest = ((unsigned long *)AHBRAM1_BASE); \ - pulDest < ((unsigned long *)(AHBRAM1_BASE + AHBRAM1_SIZE)); \ - pulDest++){ - *(pulDest++) = 0; - } -#endif - - /* - * Copy the data segment initializers from flash to SRAM in ROM mode - */ -#if (__RAM_MODE__==0) - unsigned long *pulSrc = &__sidata; - for(pulDest = &__data_start__; pulDest < &__data_end__; ) - { - *(pulDest++) = *(pulSrc++); - } -#endif - - - /* - * Zero fill the bss segment. - */ - for(pulDest = &__bss_start__; pulDest < &__bss_end__; ) - { - *(pulDest++) = 0; + /* load data section from flash to ram */ + for (dst = &_srelocate; dst < &_erelocate; ) { + *(dst++) = *(src++); } - /* - * Call IEC60335 CPU register tests POST - */ - // __ASM volatile ("bl _CPUregTestPOST \t\n"); + /* default bss section to zero */ + for (dst = &_szero; dst < &_ezero; ) { + *(dst++) = 0; + } - /* - * Call the application's entry point. - */ + /* initialize the board and startup the kernel */ board_init(); + /* initialize std-c library (this should be done after board_init) */ + __libc_init_array(); + /* startup the kernel */ kernel_init(); } -/***************************************************************************** - * - * Provide weak aliases for each Exception handler to the default_handler. - * As they are weak aliases, any function with the same name will override - * this definition. - * - ****************************************************************************/ -#pragma weak MemManage_Handler = default_handler /* MPU Fault Handler */ -#pragma weak BusFault_Handler = default_handler /* Bus Fault Handler */ -#pragma weak UsageFault_Handler = default_handler /* Usage Fault Handler */ -#pragma weak SVC_Handler = default_handler /* SVCall Handler */ -#pragma weak DebugMon_Handler = default_handler /* Debug Monitor Handler */ -#pragma weak PendSV_Handler = default_handler /* PendSV Handler */ -#pragma weak SysTick_Handler = default_handler /* SysTick Handler */ - -/* External interrupt vector handler */ -#pragma weak WDT_IRQHandler = default_handler /* Watchdog Timer */ -#pragma weak TIMER0_IRQHandler = default_handler /* Timer0 */ -#pragma weak TIMER1_IRQHandler = default_handler /* Timer1 */ -#pragma weak TIMER2_IRQHandler = default_handler /* Timer2 */ -#pragma weak TIMER3_IRQHandler = default_handler /* Timer3 */ -#pragma weak UART0_IRQHandler = default_handler /* UART0 */ -#pragma weak UART1_IRQHandler = default_handler /* UART1 */ -#pragma weak UART2_IRQHandler = default_handler /* UART2 */ -#pragma weak UART3_IRQHandler = default_handler /* UART3 */ -#pragma weak PWM1_IRQHandler = default_handler /* PWM1 */ -#pragma weak I2C0_IRQHandler = default_handler /* I2C0 */ -#pragma weak I2C1_IRQHandler = default_handler /* I2C1 */ -#pragma weak I2C2_IRQHandler = default_handler /* I2C2 */ -#pragma weak SPI_IRQHandler = default_handler /* SPI */ -#pragma weak SSP0_IRQHandler = default_handler /* SSP0 */ -#pragma weak SSP1_IRQHandler = default_handler /* SSP1 */ -#pragma weak PLL0_IRQHandler = default_handler /* PLL0 (Main PLL) */ -#pragma weak RTC_IRQHandler = default_handler /* Real Time Clock */ -#pragma weak EINT0_IRQHandler = default_handler /* External Interrupt 0 */ -#pragma weak EINT1_IRQHandler = default_handler /* External Interrupt 1 */ -#pragma weak EINT2_IRQHandler = default_handler /* External Interrupt 2 */ -#pragma weak EINT3_IRQHandler = default_handler /* External Interrupt 3 */ -#pragma weak ADC_IRQHandler = default_handler /* A/D Converter */ -#pragma weak BOD_IRQHandler = default_handler /* Brown Out Detect */ -#pragma weak USB_IRQHandler = default_handler /* USB */ -#pragma weak CAN_IRQHandler = default_handler /* CAN */ -#pragma weak DMA_IRQHandler = default_handler /* GP DMA */ -#pragma weak I2S_IRQHandler = default_handler /* I2S */ -#pragma weak ENET_IRQHandler = default_handler /* Ethernet */ -#pragma weak RIT_IRQHandler = default_handler /* Repetitive Interrupt Timer */ -#pragma weak MCPWM_IRQHandler = default_handler /* Motor Control PWM */ -#pragma weak QEI_IRQHandler = default_handler /* Quadrature Encoder Interface */ -#pragma weak PLL1_IRQHandler = default_handler /* PLL1 (USB PLL) */ - -/***************************************************************************** - * - * This is the code that gets called when the processor receives an unexpected - * interrupt. This simply enters an infinite loop, preserving the system state - * for examination by a debugger. - * - ****************************************************************************/ -void default_handler(void) { - /* Go into an infinite loop. */ - while (1) { - } +/** + * @brief Default handler is called in case no interrupt handler was defined + */ +void dummy_handler(void) +{ + while (1) {asm ("nop");} } + +void isr_nmi(void) +{ + while (1) {asm ("nop");} +} + +void isr_mem_manage(void) +{ + while (1) {asm ("nop");} +} + +void isr_debug_mon(void) +{ + while (1) {asm ("nop");} +} + +void isr_hard_fault(void) +{ + puts("##### HARD FAULT #####"); + while (1) {asm ("nop");} +} + +void isr_bus_fault(void) +{ + puts("##### BUS FAULT #####"); + while (1) {asm ("nop");} +} + +void isr_usage_fault(void) +{ + puts("##### USAGE FAULT #####"); + while (1) {asm ("nop");} +} + +/* Cortex-M specific interrupt vectors */ +void isr_svc(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_pendsv(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_systick(void) __attribute__ ((weak, alias("dummy_handler"))); + +/* LPC1768 specific interrupt vector */ +void isr_wdt(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_timer0(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_timer1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_timer2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_timer3(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_uart0(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_uart1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_uart2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_uart3(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_pwm1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_i2c0(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_i2c1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_i2c2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_spi(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_ssp0(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_ssp1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_pll0(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_rtc(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_eint0(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_eint1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_eint2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_eint3(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_adc(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_bod(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_usb(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_can(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_i2s(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_enet(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_rit(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_mcpwm(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_qei(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_pll1(void) __attribute__ ((weak, alias("dummy_handler"))); + + +/* interrupt vector table */ +__attribute__ ((section(".vectors"))) +const void *interrupt_vector[] = { + /* Stack pointer */ + (void*) (&_estack), /* pointer to the top of the empty stack */ + /* Cortex-M handlers */ + (void*) reset_handler, /* entry point of the program */ + (void*) isr_nmi, /* non maskable interrupt handler */ + (void*) isr_hard_fault, /* if you end up here its not good */ + (void*) isr_mem_manage, /* called on memory fault */ + (void*) isr_bus_fault, /* called on bus fault */ + (void*) isr_usage_fault, /* callee on usage fault */ + (void*) (0UL), /* reserved */ + (void*) (0UL), /* reserved */ + (void*) (0UL), /* reserved */ + (void*) (0UL), /* reserved */ + (void*) isr_svc, /* system call interrupt */ + (void*) isr_debug_mon, /* debug monitor interrupt */ + (void*) (0UL), /* reserved */ + (void*) isr_pendsv, /* pendSV interrupt, used for task switching in RIOT */ + (void*) isr_systick, /* SysTick interrupt, not used in RIOT */ + /* LPC specific peripheral handlers */ + (void*) isr_wdt, /* watchdog timer */ + (void*) isr_timer0, /* timer0 */ + (void*) isr_timer1, /* timer1 */ + (void*) isr_timer2, /* timer2 */ + (void*) isr_timer3, /* timer3 */ + (void*) isr_uart0, /* uart0 */ + (void*) isr_uart1, /* uart1 */ + (void*) isr_uart2, /* uart2 */ + (void*) isr_uart3, /* uart3 */ + (void*) isr_pwm1, /* pwm1 */ + (void*) isr_i2c0, /* i2c0 */ + (void*) isr_i2c1, /* i2c1 */ + (void*) isr_i2c2, /* i2c2 */ + (void*) isr_spi, /* spi */ + (void*) isr_ssp0, /* ssp0 */ + (void*) isr_ssp1, /* ssp1 */ + (void*) isr_pll0, /* pll0 (main pll) */ + (void*) isr_rtc, /* real time clock */ + (void*) isr_eint0, /* external interrupt 0 */ + (void*) isr_eint1, /* external interrupt 1 */ + (void*) isr_eint2, /* external interrupt 2 */ + (void*) isr_eint3, /* external interrupt 3 */ + (void*) isr_adc, /* a/d converter */ + (void*) isr_bod, /* brown out detect */ + (void*) isr_usb, /* usb */ + (void*) isr_can, /* can */ + (void*) isr_dma, /* gp dma */ + (void*) isr_i2s, /* i2s */ + (void*) isr_enet, /* ethernet */ + (void*) isr_rit, /* repetitive interrupt timer */ + (void*) isr_mcpwm, /* motor control pwm */ + (void*) isr_qei, /* quadrature encoder interface */ + (void*) isr_pll1, /* pll1 (usb pll) */ +}; diff --git a/cpu/lpc1768/syscalls.c b/cpu/lpc1768/syscalls.c index 3d6fa2808f..c38c66652c 100644 --- a/cpu/lpc1768/syscalls.c +++ b/cpu/lpc1768/syscalls.c @@ -1,246 +1,329 @@ -/** - * Syscall implementation for NXP LPC1768 - * - * Copyright (C) 2013 Oliver Hahm +/* + * Copyright (C) 2014 Freie Universität Berlin * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. - * - * @ingroup lpc1768 + */ + +/** + * @ingroup cpu_lpc1768 * @{ - * @file syscalls.c - * @author Oliver Hahm - * @author Alaeddine Weslati + * + * @file + * @brief NewLib system calls implementations for LPC1768 + * + * @author Michael Baar + * @author Stefan Pfeiffer + * @author Hauke Petersen + * @author Oliver Hahm + * @author Alaeddine Weslati + * * @} */ #include #include +#include #include #include #include #include -#include + +#include "board.h" +#include "thread.h" #include "kernel.h" +#include "mutex.h" +#include "ringbuffer.h" #include "irq.h" -#ifdef MODULE_VTIMER -#include "vtimer.h" +#include "periph/uart.h" + +#ifdef MODULE_UART0 +#include "board_uart0.h" #endif /** - * @name Heaps (defined in linker script) - * @{ + * manage the heap */ -#define NUM_HEAPS 1 +extern char _sheap; /* start of the heap */ +extern char _eheap; /* end of the heap */ +caddr_t heap_top = (caddr_t)&_sheap + 4; -#define DEBUG_SYSCALLS 0 -#if DEBUG_SYSCALLS -#define PRINTF(...) printf(__VA_ARGS__) -#else -#define PRINTF(...) +#ifndef MODULE_UART0 +/** + * @brief use mutex for waiting on incoming UART chars + */ +static mutex_t uart_rx_mutex; +static char rx_buf_mem[STDIO_RX_BUFSIZE]; +static ringbuffer_t rx_buf; #endif -extern uintptr_t __heap_start; ///< start of heap memory space -extern uintptr_t __heap_max; ///< maximum for end of heap memory space - -/// current position in heap -static caddr_t heap[NUM_HEAPS] = {(caddr_t)&__heap_start}; -/// maximum position in heap -static const caddr_t heap_max[NUM_HEAPS] = {(caddr_t)&__heap_max}; -// start position in heap -static const caddr_t heap_start[NUM_HEAPS] = {(caddr_t)&__heap_start}; -// current heap in use -volatile static uint8_t iUsedHeap = 0; - -/** @} */ - -/*-----------------------------------------------------------------------------------*/ -void heap_stats(void) { - for(int i = 0; i < NUM_HEAPS; i++) - printf("# heap %i: %p -- %p -> %p (%li of %li free)\n", i, heap_start[i], heap[i], heap_max[i], - (uint32_t)heap_max[i] - (uint32_t)heap[i], (uint32_t)heap_max[i] - (uint32_t)heap_start[i]); -} -/*-----------------------------------------------------------------------------------*/ -void __assert_func(const char *file, int line, const char *func, const char *failedexpr) +/** + * @brief Receive a new character from the UART and put it into the receive buffer + */ +void rx_cb(void *arg, char data) { - printf("#! assertion %s failed\n\t%s() in %s:%d\n", failedexpr, func, file, line ); - _exit(3); -} -/*-----------------------------------------------------------------------------------*/ -void __assert(const char *file, int line, const char *failedexpr) -{ - __assert_func(file, line, "?", failedexpr); -} -/*-----------------------------------------------------------------------------------*/ -caddr_t _sbrk_r(struct _reent *r, ptrdiff_t incr) -{ - if(incr < 0) - { - puts("[syscalls] Negative Values for _sbrk_r are not supported"); - r->_errno = ENOMEM; - return NULL; +#ifndef MODULE_UART0 + (void)arg; + + ringbuffer_add_one(&rx_buf, data); + mutex_unlock(&uart_rx_mutex); +#else + if (uart0_handler_pid) { + uart0_handle_incoming(data); + + uart0_notify_thread(); } - - uint32_t cpsr = disableIRQ(); - - /* check all heaps for a chunk of the requested size */ - for( ; iUsedHeap < NUM_HEAPS; iUsedHeap++ ) { - caddr_t new_heap = heap[iUsedHeap] + incr; - - if( new_heap <= heap_max[iUsedHeap] ) { - caddr_t prev_heap = heap[iUsedHeap]; - heap[iUsedHeap] = new_heap; - - r->_errno = 0; - restoreIRQ(cpsr); - return prev_heap; - } - } - restoreIRQ(cpsr); - - r->_errno = ENOMEM; - return NULL; +#endif } -/*---------------------------------------------------------------------------*/ -int _isatty_r(struct _reent *r, int fd) + +/** + * @brief Initialize NewLib, called by __libc_init_array() from the startup script + */ +void _init(void) { - r->_errno = 0; - if( fd == STDOUT_FILENO || fd == STDERR_FILENO ) - return 1; - else - return 0; +#ifndef MODULE_UART0 + mutex_init(&uart_rx_mutex); + ringbuffer_init(&rx_buf, rx_buf_mem, STDIO_RX_BUFSIZE); +#endif + uart_init(STDIO, STDIO_BAUDRATE, rx_cb, 0, 0); } -/*---------------------------------------------------------------------------*/ -_off_t _lseek_r(struct _reent *r, int fd, _off_t pos, int whence) + +/** + * @brief Free resources on NewLib de-initialization, not used for RIOT + */ +void _fini(void) { - _off_t result = -1; - PRINTF("lseek [%i] pos %li whence %i\n", fd, pos, whence); - - r->_errno = ENODEV; - - PRINTF("lseek returned %li (0 is success)\n", result); - return result; + /* nothing to do here */ } -/*---------------------------------------------------------------------------*/ -int _open_r(struct _reent *r, const char *name, int mode) -{ - int ret = -1; - PRINTF("open '%s' mode %#x\n", name, mode); - r->_errno = ENODEV; // no such device - - PRINTF("open [%i] errno %i\n", ret, r->_errno); - return ret; -} -/*---------------------------------------------------------------------------*/ -int _stat_r(struct _reent *r, char *name, struct stat *st) -{ - int ret = -1; - PRINTF("_stat_r '%s' \n", name); - r->_errno = ENODEV; // no such device - PRINTF("_stat_r [%i] errno %i\n", ret, r->_errno); - return ret; -} -/*---------------------------------------------------------------------------*/ -int _fstat_r(struct _reent *r, int fd, struct stat * st) -{ - int ret = -1; - - r->_errno = 0; - memset(st, 0, sizeof(*st)); - if (fd == STDOUT_FILENO || fd == STDERR_FILENO) { - st->st_mode = S_IFCHR; - ret = 0; - } - else { - r->_errno = ENODEV; - } - return ret; -} -/*---------------------------------------------------------------------------*/ -int _write_r(struct _reent *r, int fd, const void *data, unsigned int count) -{ - int result = EOF; - r->_errno = EBADF; - - switch(fd) { - case STDOUT_FILENO: - case STDERR_FILENO: - { - //FIXME impl fw_puts - //char* chars = (char*) data; - for(int i = 0;i < count;i++) { - //USART_SendData(USART2, chars[i]); - - /* Loop until the end of transmission */ - //while (USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET){} - } - - return count; - //result = fw_puts((char*)data, count); - } - break; - - default: - break; - } - - return result; -} -/*---------------------------------------------------------------------------*/ -int _read_r(struct _reent *r, int fd, void *buffer, unsigned int count) -{ - int result = -1; - r->_errno = EBADF; - return result; -} -/*---------------------------------------------------------------------------*/ -int _close_r(struct _reent *r, int fd) -{ - int ret = -1; - r->_errno = EBADF; - return ret; -} -/*---------------------------------------------------------------------------*/ -int _unlink_r(struct _reent *r, char* path) -{ - int ret = -1; - r->_errno = ENODEV; - return ret; -} -/*---------------------------------------------------------------------------*/ +/** + * @brief Exit a program without cleaning up files + * + * If your system doesn't provide this, it is best to avoid linking with subroutines that + * require it (exit, system). + * + * @param n the exit code, 0 for all OK, >0 for not OK + */ void _exit(int n) { printf("#! exit %i: resetting\n", n); - - //FIXME write out all peripherie buffers stdout flush NVIC_SystemReset(); while(1); } -/*---------------------------------------------------------------------------*/ -pid_t _getpid(void) + +/** + * @brief Allocate memory from the heap. + * + * The current heap implementation is very rudimentary, it is only able to allocate + * memory. But it does not + * - have any means to free memory again + * + * @return [description] + */ +caddr_t _sbrk_r(struct _reent *r, ptrdiff_t incr) +{ + unsigned int state = disableIRQ(); + caddr_t res = heap_top; + + if (((incr > 0) && ((heap_top + incr > &_eheap) || (heap_top + incr < res))) || + ((incr < 0) && ((heap_top + incr < &_sheap) || (heap_top + incr > res)))) { + r->_errno = ENOMEM; + res = (void *) -1; + } + else { + heap_top += incr; + } + + restoreIRQ(state); + return res; +} + +/** + * @brief Get the process-ID of the current thread + * + * @return the process ID of the current thread + */ +int _getpid(void) { return sched_active_pid; } -/*---------------------------------------------------------------------------*/ + +/** + * @brief Send a signal to a given thread + * + * @param r TODO + * @param pid TODO + * @param sig TODO + * + * @return TODO + */ __attribute__ ((weak)) int _kill_r(struct _reent *r, int pid, int sig) { r->_errno = ESRCH; /* not implemented yet */ return -1; } -/*---------------------------------------------------------------------------*/ -#ifdef MODULE_VTIMER -int _gettimeofday(struct timeval *tp, void *restrict tzp) { - (void) tzp; - vtimer_gettimeofday(tp); - return 0; -} -#endif -void _init(void){} -void _fini(void){} +/** + * @brief Open a file + * + * @param r TODO + * @param name TODO + * @param mode TODO + * + * @return TODO + */ +int _open_r(struct _reent *r, const char *name, int mode) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Read from a file + * + * All input is read from UART_0. The function will block until a byte is actually read. + * + * Note: the read function does not buffer - data will be lost if the function is not + * called fast enough. + * + * TODO: implement more sophisticated read call. + * + * @param r TODO + * @param fd TODO + * @param buffer TODO + * @param int TODO + * + * @return TODO + */ +int _read_r(struct _reent *r, int fd, void *buffer, unsigned int count) +{ +#ifndef MODULE_UART0 + while (rx_buf.avail == 0) { + mutex_lock(&uart_rx_mutex); + } + return ringbuffer_get(&rx_buf, (char*)buffer, rx_buf.avail); +#else + char *res = (char*)buffer; + res[0] = (char)uart0_readc(); + return 1; +#endif +} + +/** + * @brief Write characters to a file + * + * All output is currently directed to UART_0, independent of the given file descriptor. + * The write call will further block until the byte is actually written to the UART. + * + * TODO: implement more sophisticated write call. + * + * @param r TODO + * @param fd TODO + * @param data TODO + * @param int TODO + * + * @return TODO + */ +int _write_r(struct _reent *r, int fd, const void *data, unsigned int count) +{ + int i = 0; + + while (i < count) { + uart_write_blocking(STDIO, ((char*)data)[i++]); + } + + return i; +} + +/** + * @brief Close a file + * + * @param r TODO + * @param fd TODO + * + * @return TODO + */ +int _close_r(struct _reent *r, int fd) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Set position in a file + * + * @param r TODO + * @param fd TODO + * @param pos TODO + * @param dir TODO + * + * @return TODO + */ +_off_t _lseek_r(struct _reent *r, int fd, _off_t pos, int dir) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Status of an open file + * + * @param r TODO + * @param fd TODO + * @param stat TODO + * + * @return TODO + */ +int _fstat_r(struct _reent *r, int fd, struct stat * st) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Status of a file (by name) + * + * @param r TODO + * @param name TODO + * @param stat TODO + * + * @return TODO + */ +int _stat_r(struct _reent *r, char *name, struct stat *st) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Query whether output stream is a terminal + * + * @param r TODO + * @param fd TODO + * + * @return TODO + */ +int _isatty_r(struct _reent *r, int fd) +{ + r->_errno = 0; + return -1; +} + +/** + * @brief Remove a file's directory entry + * + * @param r TODO + * @param path TODO + * + * @return TODO + */ +int _unlink_r(struct _reent *r, char* path) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} /** * @brief Send a signal to a thread From 764207e02e4db23574afd9d77ace0c275e2df6c3 Mon Sep 17 00:00:00 2001 From: Hauke Petersen Date: Wed, 19 Nov 2014 16:34:45 +0100 Subject: [PATCH 2/2] board/mbed_lpc1768: heavy clean-up - removed legacy code - added default defines - created periph_conf.h --- boards/mbed_lpc1768/Makefile | 3 +- boards/mbed_lpc1768/Makefile.include | 5 +- boards/mbed_lpc1768/board.c | 55 +++++++++ boards/mbed_lpc1768/hwtimer_board.c | 67 ----------- boards/mbed_lpc1768/include/board.h | 105 +++++++++++++----- boards/mbed_lpc1768/include/periph_conf.h | 72 ++++++++++++ boards/mbed_lpc1768/include/system_LPC17xx.h | 56 ---------- .../mbed_lpc1768/{board_init.c => system.c} | 37 +----- 8 files changed, 211 insertions(+), 189 deletions(-) create mode 100644 boards/mbed_lpc1768/board.c delete mode 100644 boards/mbed_lpc1768/hwtimer_board.c create mode 100644 boards/mbed_lpc1768/include/periph_conf.h delete mode 100644 boards/mbed_lpc1768/include/system_LPC17xx.h rename boards/mbed_lpc1768/{board_init.c => system.c} (97%) diff --git a/boards/mbed_lpc1768/Makefile b/boards/mbed_lpc1768/Makefile index ff5489888b..37891de8e6 100644 --- a/boards/mbed_lpc1768/Makefile +++ b/boards/mbed_lpc1768/Makefile @@ -1,3 +1,4 @@ -MODULE =$(BOARD)_base +# tell the Makefile.base which module to build +MODULE = $(BOARD)_base include $(RIOTBASE)/Makefile.base diff --git a/boards/mbed_lpc1768/Makefile.include b/boards/mbed_lpc1768/Makefile.include index 7f08a0068a..243cfb6ca0 100644 --- a/boards/mbed_lpc1768/Makefile.include +++ b/boards/mbed_lpc1768/Makefile.include @@ -34,7 +34,7 @@ export CFLAGS += -ggdb -g3 -std=gnu99 -Os -Wall -Wstrict-prototypes $(CPU_USAGE) export CFLAGS += -ffunction-sections -fdata-sections -fno-builtin export ASFLAGS += -ggdb -g3 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian export LINKFLAGS += -g3 -ggdb -std=gnu99 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles -export LINKFLAGS += -T$(RIOTCPU)/$(CPU)/LPC1768.ld +export LINKFLAGS += -T$(LINKERSCRIPT) export OFLAGS = -O binary export FFLAGS = export DEBUGGER_FLAGS = @@ -50,5 +50,4 @@ export LINKFLAGS += -specs=nano.specs -lc -lnosys endif # export board specific includes to the global includes-listing -export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/ -I$(RIOTCPU)/$(CPU)/include -export UNDEF += $(BINDIR)cpu/startup.o +export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/ diff --git a/boards/mbed_lpc1768/board.c b/boards/mbed_lpc1768/board.c new file mode 100644 index 0000000000..01f287d465 --- /dev/null +++ b/boards/mbed_lpc1768/board.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup board_mbed_lpc1768 + * @{ + * + * @file + * @brief Board specific implementations for the mbed LPC1768 board + * + * @author Hauke Petersen + * + * @} + */ + +#include "board.h" + +static void leds_init(void); +extern void SystemInit(void); + +void board_init(void) +{ + /* initialize core clocks via CMSIS function */ + SystemInit(); + /* initialize the CPU */ + cpu_init(); + /* initialize the boards LEDs */ + leds_init(); +} + +/** + * @brief Initialize the boards on-board LEDs (LED1 to LED4) + * + * The LED initialization is hard-coded in this function. As the LEDs are soldered + * onto the board they are fixed to their CPU pins. + * + * The LEDs are connected to the following pins: + * - LED1: P1.18 + * - LED2: P1.20 + * - LED3: P1.21 + * - LED4: P1.23 + */ +static void leds_init(void) +{ + /* configure LED pins as output */ + LED_PORT->FIODIR |= (LED1_PIN | LED2_PIN | LED3_PIN | LED4_PIN); + + /* clear all LEDs */ + LED_PORT->FIOCLR = (LED1_PIN | LED2_PIN | LED3_PIN | LED4_PIN); +} diff --git a/boards/mbed_lpc1768/hwtimer_board.c b/boards/mbed_lpc1768/hwtimer_board.c deleted file mode 100644 index 3ca6f99a65..0000000000 --- a/boards/mbed_lpc1768/hwtimer_board.c +++ /dev/null @@ -1,67 +0,0 @@ -/** - * MBED LPC1768 board hwtimer_arch.h implementation stub - * - * TODO: implement - * - * Copyright (C) 2014 Ludwig Ortmann - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - * - * @ingroup hwtimer - * @ingroup mbed_lpc1768 - * @{ - * @author Ludwig Ortmann - * @file - * @} - */ - -#include - -#include "arch/hwtimer_arch.h" - -#define ENABLE_DEBUG (0) -#include "debug.h" - -void hwtimer_arch_enable_interrupt(void) -{ - DEBUG("hwtimer_arch_enable_interrupt(): not implemented\n"); - return; -} - -void hwtimer_arch_disable_interrupt(void) -{ - DEBUG("hwtimer_arch_disable_interrupt(): not implemented\n"); - return; -} - -void hwtimer_arch_unset(short timer) -{ - DEBUG("hwtimer_arch_unset(%i): not implemented\n", timer); - return; -} - -void hwtimer_arch_set(unsigned long offset, short timer) -{ - DEBUG("hwtimer_arch_set(%lu, %i): not implemented\n", offset, timer); - return; -} - -void hwtimer_arch_set_absolute(unsigned long value, short timer) -{ - DEBUG("hwtimer_arch_set_absolute(%lu, %i): not implemented\n", value, timer); - return; -} - -unsigned long hwtimer_arch_now(void) -{ - DEBUG("hwtimer_arch_now(): not implemented\n"); - return 0; -} - -void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) -{ - DEBUG("hwtimer_arch_init(%p, %" PRIu32 "): not implemented\n", handler, fcpu); - return; -} diff --git a/boards/mbed_lpc1768/include/board.h b/boards/mbed_lpc1768/include/board.h index 11e45244d7..2ef6cfb25d 100644 --- a/boards/mbed_lpc1768/include/board.h +++ b/boards/mbed_lpc1768/include/board.h @@ -1,55 +1,106 @@ /* - * Copyright 2014 INRIA + * Copyright (C) 2014 INRIA + * Copyright (C) 2014 Freie Universität Berlin * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup board_mbed_lpc1768 mbed LPC1768 development kit + * @ingroup boards + * @brief Support for the mbed LPC1762 board + * @{ + * + * @file + * @brief Board specific definitions for the mbed_lpc1768 board + * + * @author Oliver Hahm + * @author Hauke Petersen */ #ifndef __BOARD_H #define __BOARD_H -/** - * @file - * @author Oliver Hahm - * - * @defgroup mbed_lpc1768 mbed NXP LPC1768 development kit - * @ingroup boards - * @brief Support for the mbed NXP LPC1768 board. - * @{ - */ - #include + #include "bitarithm.h" +#include "cpu.h" #ifdef __cplusplus extern "C" { #endif -#define F_CPU (96000000) +/** + * @name The nominal CPU core clock in this board + */ +#define F_CPU (96000000) +/** + * @name Assign the peripheral timer to be used as hardware timer + */ +#define HW_TIMER TIMER_0 -#define PIN_LED1 (BIT18) -#define PIN_LED2 (BIT20) -#define PIN_LED3 (BIT21) -#define PIN_LED4 (BIT23) +/** + * @name Assign the UART interface to be used for stdio + * @{ + */ +#define STDIO UART_0 +#define STDIO_BAUDRATE (115200U) +#define STDIO_RX_BUFSIZE (64U) +/** @} */ -#define LED_ON(led_nr) (LPC_GPIO1->FIOSET = PIN_LED##led_nr) -#define LED_OFF(led_nr) (LPC_GPIO1->FIOCLR = PIN_LED##led_nr) -#define LED_TOGGLE(led_nr) (LPC_GPIO1->FIOPIN ^= PIN_LED##led_nr) +/** + * @name LED pin definitions + * @{ + */ +#define LED_PORT LPC_GPIO1 +#define LED1_PIN BIT18 +#define LED2_PIN BIT20 +#define LED3_PIN BIT21 +#define LED4_PIN BIT23 +/** @} */ +/** + * @name Macros for controlling the on-board LEDs. + * @{ + */ +#define LED1_ON (LED_PORT->FIOSET = LED1_PIN) +#define LED1_OFF (LED_PORT->FIOCLR = LED1_PIN) +#define LED1_TOGGLE (LED_PORT->FIOPIN ^= LED1_PIN) +#define LED2_ON (LED_PORT->FIOSET = LED2_PIN) +#define LED2_OFF (LED_PORT->FIOCLR = LED2_PIN) +#define LED2_TOGGLE (LED_PORT->FIOPIN ^= LED2_PIN) +#define LED3_ON (LED_PORT->FIOSET = LED3_PIN) +#define LED3_OFF (LED_PORT->FIOCLR = LED3_PIN) +#define LED3_TOGGLE (LED_PORT->FIOPIN ^= LED3_PIN) +#define LED4_ON (LED_PORT->FIOSET = LED4_PIN) +#define LED4_OFF (LED_PORT->FIOCLR = LED4_PIN) +#define LED4_TOGGLE (LED_PORT->FIOPIN ^= LED4_PIN) + +/* for compatibility to other boards */ +#define LED_GREEN_ON LED1_ON +#define LED_GREEN_OFF LED1_OFF +#define LED_GREEN_TOGGLE LED1_TOGGLE +#define LED_RED_ON LED4_ON +#define LED_RED_OFF LED4_OFF +#define LED_RED_TOGGLE LED4_TOGGLE +/** @} */ + +/** + * @name define radio packet length + */ typedef uint8_t radio_packet_length_t; /** - * @brief Busy waiting function (while hwtimer is not available at boot time) - * - * @param[in] t The waiting cycles + * @brief Initialize board specific hardware, include clocks, LEDs and stdio */ -void loop_delay(uint32_t t); +void board_init(void); #ifdef __cplusplus } #endif -/** @} */ #endif /* __BOARD_H */ +/** @} */ diff --git a/boards/mbed_lpc1768/include/periph_conf.h b/boards/mbed_lpc1768/include/periph_conf.h new file mode 100644 index 0000000000..d84f57852f --- /dev/null +++ b/boards/mbed_lpc1768/include/periph_conf.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup board_mbed_lpc1768 + * @{ + * + * @file + * @brief Peripheral MCU configuration for the mbed LPC1768 board + * + * @author Hauke Petersen + */ + +#ifndef __PERIPH_CONF_H +#define __PERIPH_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Timer configuration + * @{ + */ +#define TIMER_NUMOF (1U) +#define TIMER_0_EN 1 +#define TIMER_1_EN 0 +#define TIMER_IRQ_PRIO 1 + +/* Timer 0 configuration */ +#define TIMER_0_DEV LPC_TIMER0 +#define TIMER_0_CHANNELS 4 +#define TIMER_0_PRESCALER (67U) +#define TIMER_0_MAX_VALUE (0xffffffff) +#define TIMER_0_CLKEN() +#define TIMER_0_ISR isr_timer0 +#define TIMER_0_IRQ_CHAN TIMER0_IRQn +/** @} */ + +/** + * @brief UART configuration + * @{ + */ +#define UART_NUMOF (1U) +#define UART_0_EN 1 +#define UART_1_EN 0 +#define UART_IRQ_PRIO 1 + +/* UART 0 device configuration */ +#define UART_0_DEV LPC_UART2 +#define UART_0_CLKEN() +#define UART_0_IRQ UART0_IRQn +#define UART_0_ISR isr_uart0 +/* UART 0 pin configuration */ +#define UART_0_PORT +#define UART_0_PORT_CLKEN() +#define UART_0_RX_PIN +#define UART_0_TX_PIN +#define UART_0_AF +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PERIPH_CONF_H */ +/** @} */ diff --git a/boards/mbed_lpc1768/include/system_LPC17xx.h b/boards/mbed_lpc1768/include/system_LPC17xx.h deleted file mode 100644 index b7259c3951..0000000000 --- a/boards/mbed_lpc1768/include/system_LPC17xx.h +++ /dev/null @@ -1,56 +0,0 @@ -/****************************************************************************** - * @file: system_LPC17xx.h - * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * for the NXP LPC17xx Device Series - * @version: V1.03 - * @date: 09. November 2013 - * - * @note: Integrated and adopted for RIOT by Oliver Hahm. - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * Copyright (C) 2013 Oliver Hahm - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M3 - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC17xx_H -#define __SYSTEM_LPC17xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t system_clock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void board_init(void); - -/** - * Update system_clock variable - * - * @brief Updates the system_clock with current core Clock - * retrieved from cpu registers. - */ -extern void clock_update(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC17xx_H */ diff --git a/boards/mbed_lpc1768/board_init.c b/boards/mbed_lpc1768/system.c similarity index 97% rename from boards/mbed_lpc1768/board_init.c rename to boards/mbed_lpc1768/system.c index f6562c9a11..4bd55de248 100644 --- a/boards/mbed_lpc1768/board_init.c +++ b/boards/mbed_lpc1768/system.c @@ -23,9 +23,6 @@ * ******************************************************************************/ - -#include -#include "board.h" #include "LPC17xx.h" /*--------------------- Clock Configuration ---------------------------------- @@ -409,28 +406,6 @@ #endif #endif -#define BLINK_DELAY (1000000) - -void loop_delay(uint32_t t) -{ - for (uint32_t delay = 0; delay < t; delay++) { - __asm("NOP"); - } -} - -void bl_blink(void) -{ - LED_ON(1); - LED_ON(2); - LED_ON(3); - LED_ON(4); - loop_delay(BLINK_DELAY); - LED_OFF(1); - LED_OFF(2); - LED_OFF(3); - LED_OFF(4); -} - /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ @@ -440,7 +415,7 @@ uint32_t system_clock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ /*---------------------------------------------------------------------------- Clock functions *----------------------------------------------------------------------------*/ -void clock_update(void) /* Get Core Clock Frequency */ +void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ { /* Determine clock frequency according to clock register values */ if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ @@ -493,7 +468,7 @@ void clock_update(void) /* Get Core Clock Frequency */ * @brief Setup the microcontroller system. * Initialize the System. */ -void board_init(void) +void SystemInit(void) { #if (CLOCK_SETUP) /* Clock Setup */ LPC_SC->SCS = SCS_Val; @@ -557,12 +532,4 @@ void board_init(void) #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; #endif - - /* Initialize LED pins */ - LPC_GPIO1->FIODIR |= PIN_LED1; - LPC_GPIO1->FIODIR |= PIN_LED2; - LPC_GPIO1->FIODIR |= PIN_LED3; - LPC_GPIO1->FIODIR |= PIN_LED4; - - bl_blink(); }