mirror of
https://github.com/RIOT-OS/RIOT.git
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boards/stm32f2/4/7: rework common clock configuration
This commit is contained in:
Alexandre Abadie
parent
0d786e3dbb
commit
c448470b0d
@ -1,64 +0,0 @@
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/*
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* Copyright (C) 2016-2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32F2 clock to 120MHz using PLL
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Aurelien Gonce <aurelien.gonce@altran.fr>
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* @author Toon Stegen <toon.stegen@altran.com>
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*/
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#ifndef F2_CFG_CLOCK_120_8_1_H
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#define F2_CFG_CLOCK_120_8_1_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 120MHz */
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#define CLOCK_CORECLOCK (120000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 30MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 60MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (120)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (5)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* F2_CFG_CLOCK_120_8_1_H */
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/** @} */
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90
boards/common/stm32/include/f2f4f7/cfg_clock_common.h
Normal file
90
boards/common/stm32/include/f2f4f7/cfg_clock_common.h
Normal file
@ -0,0 +1,90 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2018-2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Base STM32F4 clock configuration
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F2F4F7_CFG_CLOCK_COMMON_H
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#define F2F4F7_CFG_CLOCK_COMMON_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock common configuration
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* @{
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*/
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/* Select the desired system clock source between PLL, HSE or HSI */
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#ifndef CONFIG_USE_CLOCK_PLL
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CONFIG_USE_CLOCK_PLL 0
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#else
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#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#ifndef CONFIG_USE_CLOCK_HSE
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#define CONFIG_USE_CLOCK_HSE 0
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#endif /* CONFIG_USE_CLOCK_HSE */
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#ifndef CONFIG_USE_CLOCK_HSI
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#define CONFIG_USE_CLOCK_HSI 0
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#endif /* CONFIG_USE_CLOCK_HSI */
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#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
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(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
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#error "Cannot use PLL as clock source with other clock configurations"
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#endif
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
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(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
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#error "Cannot use HSE as clock source with other clock configurations"
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#endif
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
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(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
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#error "Cannot use HSI as clock source with other clock configurations"
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#endif
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 0
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#endif
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#ifndef CLOCK_HSE
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#define CLOCK_HSE MHZ(8)
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#endif
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 0
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#endif
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#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
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#define CLOCK_LSE (1)
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#else
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#define CLOCK_LSE (0)
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#endif
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#define CLOCK_HSI MHZ(16)
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#ifdef __cplusplus
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}
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#endif
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#endif /* F2F4F7_CFG_CLOCK_COMMON_H */
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/** @} */
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81
boards/common/stm32/include/f2f4f7/cfg_clock_default_100.h
Normal file
81
boards/common/stm32/include/f2f4f7/cfg_clock_default_100.h
Normal file
@ -0,0 +1,81 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2018-2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Default STM32F4 clock configuration for 100MHz boards
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F2F4F7_CFG_CLOCK_DEFAULT_100_H
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#define F2F4F7_CFG_CLOCK_DEFAULT_100_H
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#include "f2f4f7/cfg_clock_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock PLL settings (100MHz)
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* @{
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*/
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/* The following parameters configure a 100MHz system clock with HSE (8MHz or
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16MHz) or HSI (16MHz) as PLL input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (4)
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
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#define CONFIG_CLOCK_PLL_N (100)
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#else
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#define CONFIG_CLOCK_PLL_N (50)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_P
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#define CONFIG_CLOCK_PLL_P (2)
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (4)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (4)
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#endif
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/** @} */
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/**
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* @name Clock bus settings (APB1 and APB2)
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*/
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (2) /* max 50MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (1) /* max 100MHz */
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#include "f2f4f7/cfg_clock_values.h"
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#if CLOCK_CORECLOCK > MHZ(100)
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#error "SYSCLK cannot exceed 100MHz"
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#endif
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#endif /* F2F4F7_CFG_CLOCK_DEFAULT_100_H */
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/** @} */
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78
boards/common/stm32/include/f2f4f7/cfg_clock_default_120.h
Normal file
78
boards/common/stm32/include/f2f4f7/cfg_clock_default_120.h
Normal file
@ -0,0 +1,78 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2018-2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Default STM32F2/4/7 clock configuration for 120MHz boards
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F2F4F7_CFG_CLOCK_DEFAULT_120_H
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#define F2F4F7_CFG_CLOCK_DEFAULT_120_H
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#include "f2f4f7/cfg_clock_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock PLL settings (120MHz)
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* @{
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*/
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/* The following parameters configure a 120MHz system clock with HSE (8MHz or
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16MHz) or HSI (16MHz) as PLL input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (4)
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
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#define CONFIG_CLOCK_PLL_N (120)
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#else
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#define CONFIG_CLOCK_PLL_N (60)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_P
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#define CONFIG_CLOCK_PLL_P (2)
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (5)
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#endif
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/** @} */
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/**
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* @name Clock bus settings (APB1 and APB2)
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*/
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (4) /* max 30MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (2) /* max 60MHz */
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#include "f2f4f7/cfg_clock_values.h"
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#if CLOCK_CORECLOCK > MHZ(120)
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#error "SYSCLK cannot exceed 120MHz"
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#endif
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#endif /* F2F4F7_CFG_CLOCK_DEFAULT_120_H */
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/** @} */
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90
boards/common/stm32/include/f2f4f7/cfg_clock_default_168.h
Normal file
90
boards/common/stm32/include/f2f4f7/cfg_clock_default_168.h
Normal file
@ -0,0 +1,90 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2018-2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Default STM32F4 clock configuration for 168MHz boards
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F2F4F7_CFG_CLOCK_DEFAULT_168_H
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#define F2F4F7_CFG_CLOCK_DEFAULT_168_H
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#include "f2f4f7/cfg_clock_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock PLL settings (180MHz)
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*
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* The PLL settings provided here can be used for USB on CPU with a max
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* frequency of 180MHz.
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* @{
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*/
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/* The following parameters configure a 168MHz system clock with HSE
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(8MHz, 12MHz or 16MHz) or HSI (16MHz) as PLL input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
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#define CONFIG_CLOCK_PLL_M (12)
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#else
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#define CONFIG_CLOCK_PLL_M (4)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
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#define CONFIG_CLOCK_PLL_N (336)
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#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
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#define CONFIG_CLOCK_PLL_N (168)
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#else
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#define CONFIG_CLOCK_PLL_N (84)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_P
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#define CONFIG_CLOCK_PLL_P (2)
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (7)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (0)
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#endif
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/** @} */
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/**
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* @name Clock bus settings (APB1 and APB2)
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*/
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#include "f2f4f7/cfg_clock_values.h"
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#if CLOCK_CORECLOCK > MHZ(180)
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#error "SYSCLK cannot exceed 180MHz"
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#endif
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#endif /* F2F4F7_CFG_CLOCK_DEFAULT_168_H */
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/** @} */
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81
boards/common/stm32/include/f2f4f7/cfg_clock_default_180.h
Normal file
81
boards/common/stm32/include/f2f4f7/cfg_clock_default_180.h
Normal file
@ -0,0 +1,81 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
|
||||
* 2017 OTA keys S.A.
|
||||
* 2018-2020 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Default STM32F4 clock configuration for 180MHz boards
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F2F4F7_CFG_CLOCK_DEFAULT_180_H
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#define F2F4F7_CFG_CLOCK_DEFAULT_180_H
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#include "f2f4f7/cfg_clock_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock PLL settings (180MHz)
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* @{
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*/
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/* The following parameters configure a 180MHz system clock with HSE (8MHz or
|
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16MHz) or HSI (16MHz) as PLL input clock */
|
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#ifndef CONFIG_CLOCK_PLL_M
|
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#define CONFIG_CLOCK_PLL_M (4)
|
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
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#define CONFIG_CLOCK_PLL_N (180)
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#else
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#define CONFIG_CLOCK_PLL_N (90)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_P
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#define CONFIG_CLOCK_PLL_P (2)
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (8)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (8)
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#endif
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/** @} */
|
||||
|
||||
/**
|
||||
* @name Clock bus settings (APB1 and APB2)
|
||||
*/
|
||||
#ifndef CONFIG_CLOCK_APB1_DIV
|
||||
#define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_APB2_DIV
|
||||
#define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#include "f2f4f7/cfg_clock_values.h"
|
||||
|
||||
#if CLOCK_CORECLOCK > MHZ(180)
|
||||
#error "SYSCLK cannot exceed 180MHz"
|
||||
#endif
|
||||
|
||||
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_180_H */
|
||||
/** @} */
|
||||
87
boards/common/stm32/include/f2f4f7/cfg_clock_default_216.h
Normal file
87
boards/common/stm32/include/f2f4f7/cfg_clock_default_216.h
Normal file
@ -0,0 +1,87 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
* 2017 OTA keys S.A.
|
||||
* 2018-2020 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Default STM32F7 clock configuration for 216MHz boards
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_216_H
|
||||
#define F2F4F7_CFG_CLOCK_DEFAULT_216_H
|
||||
|
||||
#include "f2f4f7/cfg_clock_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock PLL settings (216MHz)
|
||||
* @{
|
||||
*/
|
||||
/* The following parameters configure a 216MHz system clock with HSE (8MHz,
|
||||
16MHz or 25MHz) or HSI (16MHz) as PLL input clock */
|
||||
#ifndef CONFIG_CLOCK_PLL_M
|
||||
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
|
||||
#define CONFIG_CLOCK_PLL_M (25)
|
||||
#else
|
||||
#define CONFIG_CLOCK_PLL_M (4)
|
||||
#endif
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_N
|
||||
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
|
||||
#define CONFIG_CLOCK_PLL_N (432)
|
||||
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
|
||||
#define CONFIG_CLOCK_PLL_N (216)
|
||||
#else
|
||||
#define CONFIG_CLOCK_PLL_N (108)
|
||||
#endif
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_P
|
||||
#define CONFIG_CLOCK_PLL_P (2)
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_Q
|
||||
#define CONFIG_CLOCK_PLL_Q (9)
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_R
|
||||
#define CONFIG_CLOCK_PLL_R (8)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Clock bus settings (APB1 and APB2)
|
||||
*/
|
||||
#ifndef CONFIG_CLOCK_APB1_DIV
|
||||
#define CONFIG_CLOCK_APB1_DIV (4) /* max 54MHz */
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_APB2_DIV
|
||||
#define CONFIG_CLOCK_APB2_DIV (2) /* max 108MHz */
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#include "f2f4f7/cfg_clock_values.h"
|
||||
|
||||
#if CLOCK_CORECLOCK > MHZ(216)
|
||||
#error "SYSCLK cannot exceed 216MHz"
|
||||
#endif
|
||||
|
||||
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_216_H */
|
||||
/** @} */
|
||||
81
boards/common/stm32/include/f2f4f7/cfg_clock_default_84.h
Normal file
81
boards/common/stm32/include/f2f4f7/cfg_clock_default_84.h
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
* 2017 OTA keys S.A.
|
||||
* 2018-2020 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Default STM32F4 clock configuration for 84MHz boards
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_84_H
|
||||
#define F2F4F7_CFG_CLOCK_DEFAULT_84_H
|
||||
|
||||
#include "f2f4f7/cfg_clock_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock PLL settings (84MHz)
|
||||
* @{
|
||||
*/
|
||||
/* The following parameters configure a 84MHz system clock with HSE (8MHz or
|
||||
16MHz) or HSI (16MHz) as PLL input clock */
|
||||
#ifndef CONFIG_CLOCK_PLL_M
|
||||
#define CONFIG_CLOCK_PLL_M (4)
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_N
|
||||
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
|
||||
#define CONFIG_CLOCK_PLL_N (168)
|
||||
#else
|
||||
#define CONFIG_CLOCK_PLL_N (84)
|
||||
#endif
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_P
|
||||
#define CONFIG_CLOCK_PLL_P (4)
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_Q
|
||||
#define CONFIG_CLOCK_PLL_Q (7)
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_R
|
||||
#define CONFIG_CLOCK_PLL_R (0)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Clock bus settings (APB1 and APB2)
|
||||
*/
|
||||
#ifndef CONFIG_CLOCK_APB1_DIV
|
||||
#define CONFIG_CLOCK_APB1_DIV (2) /* max 42MHz */
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_APB2_DIV
|
||||
#define CONFIG_CLOCK_APB2_DIV (1) /* max 84MHz */
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#include "f2f4f7/cfg_clock_values.h"
|
||||
|
||||
#if CLOCK_CORECLOCK > MHZ(84)
|
||||
#error "SYSCLK cannot exceed 84MHz"
|
||||
#endif
|
||||
|
||||
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_84_H */
|
||||
/** @} */
|
||||
90
boards/common/stm32/include/f2f4f7/cfg_clock_default_96.h
Normal file
90
boards/common/stm32/include/f2f4f7/cfg_clock_default_96.h
Normal file
@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
* 2017 OTA keys S.A.
|
||||
* 2018-2020 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Default STM32F4 clock configuration for 96MHz boards
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_96_H
|
||||
#define F2F4F7_CFG_CLOCK_DEFAULT_96_H
|
||||
|
||||
#include "f2f4f7/cfg_clock_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock PLL settings (100MHz)
|
||||
*
|
||||
* The PLL settings provided here can be used for USB on CPU with a max
|
||||
* frequency of 100MHz.
|
||||
* @{
|
||||
*/
|
||||
/* The following parameters configure a 96MHz system clock with HSE (8MHz, 16MHz or
|
||||
25MHz) or HSI (16MHz) as PLL input clock */
|
||||
#ifndef CONFIG_CLOCK_PLL_M
|
||||
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
|
||||
#define CONFIG_CLOCK_PLL_M (25)
|
||||
#else
|
||||
#define CONFIG_CLOCK_PLL_M (4)
|
||||
#endif
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_N
|
||||
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
|
||||
#define CONFIG_CLOCK_PLL_N (192)
|
||||
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
|
||||
#define CONFIG_CLOCK_PLL_N (96)
|
||||
#else
|
||||
#define CONFIG_CLOCK_PLL_N (48)
|
||||
#endif
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_P
|
||||
#define CONFIG_CLOCK_PLL_P (2)
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_Q
|
||||
#define CONFIG_CLOCK_PLL_Q (4)
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_PLL_R
|
||||
#define CONFIG_CLOCK_PLL_R (4)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Clock bus settings (APB1 and APB2)
|
||||
*/
|
||||
#ifndef CONFIG_CLOCK_APB1_DIV
|
||||
#define CONFIG_CLOCK_APB1_DIV (2) /* max 50MHz */
|
||||
#endif
|
||||
#ifndef CONFIG_CLOCK_APB2_DIV
|
||||
#define CONFIG_CLOCK_APB2_DIV (1) /* max 100MHz */
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#include "f2f4f7/cfg_clock_values.h"
|
||||
|
||||
#if CLOCK_CORECLOCK > MHZ(100)
|
||||
#error "SYSCLK cannot exceed 100MHz"
|
||||
#endif
|
||||
|
||||
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_96_H */
|
||||
/** @} */
|
||||
66
boards/common/stm32/include/f2f4f7/cfg_clock_values.h
Normal file
66
boards/common/stm32/include/f2f4f7/cfg_clock_values.h
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
* 2017 OTA keys S.A.
|
||||
* 2018-2020 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief STM32F4 clock values definitions
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef F2F4F7_CFG_CLOCK_VALUES_H
|
||||
#define F2F4F7_CFG_CLOCK_VALUES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock values
|
||||
* @{
|
||||
*/
|
||||
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
|
||||
#define CLOCK_PLL_SRC (CLOCK_HSE)
|
||||
#else /* CLOCK_HSI */
|
||||
#define CLOCK_PLL_SRC (CLOCK_HSI)
|
||||
#endif
|
||||
|
||||
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
|
||||
#define CLOCK_CORECLOCK (CLOCK_HSI)
|
||||
|
||||
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
|
||||
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
|
||||
#error "The board doesn't provide an HSE oscillator"
|
||||
#endif
|
||||
#define CLOCK_CORECLOCK (CLOCK_HSE)
|
||||
|
||||
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
|
||||
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)
|
||||
#endif /* CONFIG_USE_CLOCK_PLL */
|
||||
|
||||
#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)
|
||||
|
||||
#define CLOCK_AHB CLOCK_CORECLOCK
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV)
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV)
|
||||
/** @} */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F2F4F7_CFG_CLOCK_VALUES_H */
|
||||
/** @} */
|
||||
@ -1,77 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
* 2017 OTA keys S.A.
|
||||
* 2018 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F4 clock to 100MHz using PLL
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef F4_CFG_CLOCK_100_8_1_H
|
||||
#define F4_CFG_CLOCK_100_8_1_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 100MHz */
|
||||
#define CLOCK_CORECLOCK (100000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (8000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (200)
|
||||
#define CLOCK_PLL_P (4)
|
||||
#define CLOCK_PLL_Q (0)
|
||||
|
||||
/* PLL I2S configuration */
|
||||
#define CLOCK_ENABLE_PLL_I2S (1)
|
||||
#define CLOCK_PLL_I2S_SRC (0)
|
||||
#define CLOCK_PLL_I2S_M (4)
|
||||
#define CLOCK_PLL_I2S_N (216)
|
||||
#define CLOCK_PLL_I2S_P (0)
|
||||
#define CLOCK_PLL_I2S_Q (9)
|
||||
|
||||
/* Use alternative source for 48MHz clock */
|
||||
#define CLOCK_USE_ALT_48MHZ (1)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F4_CFG_CLOCK_100_8_1_H */
|
||||
/** @} */
|
||||
@ -1,62 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F4 clock to 168MHz using PLL
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef F4_CFG_CLOCK_168_16_0_H
|
||||
#define F4_CFG_CLOCK_168_16_0_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 168MHz */
|
||||
#define CLOCK_CORECLOCK (168000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (16000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (0)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (8)
|
||||
#define CLOCK_PLL_N (168)
|
||||
#define CLOCK_PLL_P (2)
|
||||
#define CLOCK_PLL_Q (7)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F4_CFG_CLOCK_168_16_0_H */
|
||||
/** @} */
|
||||
@ -1,41 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F4 clock to 168MHz using PLL and without LSE
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef F4_CFG_CLOCK_168_8_0_H
|
||||
#define F4_CFG_CLOCK_168_8_0_H
|
||||
|
||||
#include "f4/cfg_clock_168_8_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief LSE clock settings
|
||||
*
|
||||
* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz)
|
||||
*/
|
||||
#define CLOCK_LSE (0)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F4_CFG_CLOCK_168_8_0_H */
|
||||
/** @} */
|
||||
@ -1,41 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F4 clock to 168MHz using PLL with LSE
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef F4_CFG_CLOCK_168_8_1_H
|
||||
#define F4_CFG_CLOCK_168_8_1_H
|
||||
|
||||
#include "f4/cfg_clock_168_8_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief LSE clock settings
|
||||
*
|
||||
* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz)
|
||||
*/
|
||||
#define CLOCK_LSE (1)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F4_CFG_CLOCK_168_8_1_H */
|
||||
/** @} */
|
||||
@ -1,59 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F4 clock to 168MHz using PLL
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef F4_CFG_CLOCK_168_8_COMMON_H
|
||||
#define F4_CFG_CLOCK_168_8_COMMON_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 168MHz */
|
||||
#define CLOCK_CORECLOCK (168000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (8000000U)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (168)
|
||||
#define CLOCK_PLL_P (2)
|
||||
#define CLOCK_PLL_Q (7)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F4_CFG_CLOCK_168_8_COMMON_H */
|
||||
/** @} */
|
||||
@ -1,72 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F4 clock to 180MHz using PLL
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef F4_CFG_CLOCK_180_8_1_H
|
||||
#define F4_CFG_CLOCK_180_8_1_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 180MHz */
|
||||
#define CLOCK_CORECLOCK (180000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (8000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (180)
|
||||
#define CLOCK_PLL_P (2)
|
||||
#define CLOCK_PLL_Q (0)
|
||||
|
||||
/* PLL SAI configuration */
|
||||
#define CLOCK_ENABLE_PLL_SAI (1)
|
||||
#define CLOCK_PLL_SAI_M (4)
|
||||
#define CLOCK_PLL_SAI_N (192)
|
||||
#define CLOCK_PLL_SAI_P (8)
|
||||
#define CLOCK_PLL_SAI_Q (0)
|
||||
|
||||
/* Use alternative source for 48MHz clock */
|
||||
#define CLOCK_USE_ALT_48MHZ (1)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F4_CFG_CLOCK_180_8_1_H */
|
||||
/** @} */
|
||||
@ -1,64 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
* 2018 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F4 clock to 84MHz using PLL
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef F4_CFG_CLOCK_84_8_1_H
|
||||
#define F4_CFG_CLOCK_84_8_1_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 84MHz */
|
||||
#define CLOCK_CORECLOCK (84000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (8000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (168)
|
||||
#define CLOCK_PLL_P (4)
|
||||
#define CLOCK_PLL_Q (7)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F4_CFG_CLOCK_84_8_1_H */
|
||||
/** @} */
|
||||
@ -1,66 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
* 2017 OTA keys S.A.
|
||||
* 2018 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F4 clock to 96MHz using PLL
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef F4_CFG_CLOCK_96_25_1_H
|
||||
#define F4_CFG_CLOCK_96_25_1_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 100MHz */
|
||||
#define CLOCK_CORECLOCK (96000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (25000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1U)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (25)
|
||||
#define CLOCK_PLL_N (384)
|
||||
#define CLOCK_PLL_P (4)
|
||||
#define CLOCK_PLL_Q (8)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F4_CFG_CLOCK_96_25_1_H */
|
||||
/** @} */
|
||||
@ -1,64 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Freie Universität Berlin
|
||||
* 2018 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F4 clock to 96MHz using PLL
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef F4_CFG_CLOCK_96_8_1_H
|
||||
#define F4_CFG_CLOCK_96_8_1_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 100MHz */
|
||||
#define CLOCK_CORECLOCK (96000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (8000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (192)
|
||||
#define CLOCK_PLL_P (4)
|
||||
#define CLOCK_PLL_Q (8)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F4_CFG_CLOCK_96_8_1_H */
|
||||
/** @} */
|
||||
@ -1,59 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2019 Otto-von-Guericke-Universität Magdeburg
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_common_stm32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configure STM32F7 clock to 216MHz and 8MHz HSE using PLL with
|
||||
* LSE
|
||||
*
|
||||
* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef F7_CFG_CLOCK_216_8_1_H
|
||||
#define F7_CFG_CLOCK_216_8_1_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 216MHz */
|
||||
#define CLOCK_CORECLOCK (216000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (8000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1U)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (216)
|
||||
#define CLOCK_PLL_P (2)
|
||||
#define CLOCK_PLL_Q (9)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* F7_CFG_CLOCK_216_8_1_H */
|
||||
/** @} */
|
||||
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Block a user