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Merge pull request #1825 from haukepetersen/fix_sam3x_misc

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cpu/sam3x8e: general fixes
This commit is contained in:
Ludwig Ortmann 2014-10-30 08:04:47 -07:00
commit c6ff614d59
4 changed files with 59 additions and 38 deletions
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3
cpu/sam3x8e/cpu.c
View File

@ -26,4 +26,7 @@ void cpu_init(void)
{
/* disable the watchdog timer */
WDT->WDT_MR |= WDT_MR_WDDIS;
/* set PendSV interrupt priority to lowest possible value */
NVIC_SetPriority(PendSV_IRQn, 0xff);
}

1
cpu/sam3x8e/hwtimer_arch.c
View File

@ -69,5 +69,4 @@ unsigned long hwtimer_arch_now(void)
void irq_handler(int channel)
{
timeout_handler((short)(channel));
thread_yield();
}

79
cpu/sam3x8e/periph/timer.c
View File

@ -23,7 +23,8 @@
#include "board.h"
#include "cpu.h"
#include "sched.h"
#include "thread.h"
#include "periph/timer.h"
#include "periph_conf.h"
@ -35,7 +36,7 @@ typedef struct {
/**
* @brief Timer state memory
*/
timer_conf_t config[TIMER_NUMOF];
static timer_conf_t timer_config[TIMER_NUMOF];
/**
@ -90,7 +91,7 @@ int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
}
/* save callback */
config[dev].cb = callback;
timer_config[dev].cb = callback;
/* configure the timer block by connecting TIOA2 to XC0 and XC1 */
tim->TC_BMR = TC_BMR_TC0XC0S_TIOA2 | TC_BMR_TC1XC1S_TIOA2;
@ -398,42 +399,46 @@ void timer_reset(tim_t dev)
#if TIMER_0_EN
__attribute__ ((naked))
void TIMER_0_ISR1(void)
__attribute__ ((naked)) void TIMER_0_ISR1(void)
{
ISR_ENTER();
uint32_t status = TIMER_0_DEV->TC_CHANNEL[0].TC_SR;
if (status & TC_SR_CPAS) {
TIMER_0_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPAS;
config[TIMER_0].cb(0);
timer_config[TIMER_0].cb(0);
}
else if (status & TC_SR_CPBS) {
TIMER_0_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPBS;
config[TIMER_0].cb(1);
timer_config[TIMER_0].cb(1);
}
else if (status & TC_SR_CPCS) {
TIMER_0_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPCS;
config[TIMER_0].cb(2);
timer_config[TIMER_0].cb(2);
}
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}
__attribute__ ((naked))
void TIMER_0_ISR2(void)
__attribute__ ((naked)) void TIMER_0_ISR2(void)
{
ISR_ENTER();
uint32_t status = TIMER_0_DEV->TC_CHANNEL[1].TC_SR;
if (status & TC_SR_CPAS) {
TIMER_0_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPAS;
config[TIMER_0].cb(3);
timer_config[TIMER_0].cb(3);
}
else if (status & TC_SR_CPBS) {
TIMER_0_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPBS;
config[TIMER_0].cb(4);
timer_config[TIMER_0].cb(4);
}
else if (status & TC_SR_CPCS) {
TIMER_0_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPCS;
config[TIMER_0].cb(5);
timer_config[TIMER_0].cb(5);
}
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}
@ -441,42 +446,46 @@ void TIMER_0_ISR2(void)
#if TIMER_1_EN
__attribute__ ((naked))
void TIMER_1_ISR1(void)
__attribute__ ((naked)) void TIMER_1_ISR1(void)
{
ISR_ENTER();
uint32_t status = TIMER_1_DEV->TC_CHANNEL[0].TC_SR;
if (status & TC_SR_CPAS) {
TIMER_1_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPAS;
config[TIMER_1].cb(0);
timer_config[TIMER_1].cb(0);
}
if (status & TC_SR_CPBS) {
TIMER_1_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPBS;
config[TIMER_1].cb(1);
timer_config[TIMER_1].cb(1);
}
if (status & TC_SR_CPCS) {
TIMER_1_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPCS;
config[TIMER_1].cb(2);
timer_config[TIMER_1].cb(2);
}
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}
__attribute__ ((naked))
void TIMER_1_ISR2(void)
__attribute__ ((naked)) void TIMER_1_ISR2(void)
{
ISR_ENTER();
uint32_t status = TIMER_1_DEV->TC_CHANNEL[1].TC_SR;
if (status & TC_SR_CPAS) {
TIMER_1_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPAS;
config[TIMER_1].cb(3);
timer_config[TIMER_1].cb(3);
}
if (status & TC_SR_CPBS) {
TIMER_1_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPBS;
config[TIMER_1].cb(4);
timer_config[TIMER_1].cb(4);
}
if (status & TC_SR_CPCS) {
TIMER_1_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPCS;
config[TIMER_1].cb(5);
timer_config[TIMER_1].cb(5);
}
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}
@ -484,42 +493,46 @@ void TIMER_1_ISR2(void)
#if TIMER_2_EN
__attribute__ ((naked))
void TIMER_2_ISR1(void)
__attribute__ ((naked)) void TIMER_2_ISR1(void)
{
ISR_ENTER();
uint32_t status = TIMER_2_DEV->TC_CHANNEL[0].TC_SR;
if (status & TC_SR_CPAS) {
TIMER_2_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPAS;
config[TIMER_2].cb(0);
timer_config[TIMER_2].cb(0);
}
else if (status & TC_SR_CPBS) {
TIMER_2_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPBS;
config[TIMER_2].cb(1);
timer_config[TIMER_2].cb(1);
}
else if (status & TC_SR_CPCS) {
TIMER_2_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPCS;
config[TIMER_2].cb(2);
timer_config[TIMER_2].cb(2);
}
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}
__attribute__ ((naked))
void TIMER_2_ISR2(void)
__attribute__ ((naked)) void TIMER_2_ISR2(void)
{
ISR_ENTER();
uint32_t status = TIMER_2_DEV->TC_CHANNEL[1].TC_SR;
if (status & TC_SR_CPAS) {
TIMER_2_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPAS;
config[TIMER_2].cb(3);
timer_config[TIMER_2].cb(3);
}
else if (status & TC_SR_CPBS) {
TIMER_2_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPBS;
config[TIMER_2].cb(4);
timer_config[TIMER_2].cb(4);
}
else if (status & TC_SR_CPCS) {
TIMER_2_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPCS;
config[TIMER_2].cb(5);
timer_config[TIMER_2].cb(5);
}
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}

14
cpu/sam3x8e/startup.c
View File

@ -18,8 +18,10 @@
* @}
*/
#include <stdio.h>
#include <stdint.h>
#include "board.h"
/**
* memory markers as defined in the linker script
@ -34,7 +36,6 @@ extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/**
* @brief functions for initializing the board, std-lib and kernel
*/
@ -83,7 +84,6 @@ void dummy_handler(void)
while (1) {asm ("nop");}
}
void isr_nmi(void)
{
while (1) {asm ("nop");}
@ -101,7 +101,13 @@ void isr_debug_mon(void)
void isr_hard_fault(void)
{
while (1) {asm ("nop");}
puts("\n### HARD FAULT ###\n");
while (1) {
LED_RED_TOGGLE;
for (int i = 0; i < 2000000; i++) {
asm ("nop");
}
}
}
void isr_bus_fault(void)
@ -184,7 +190,7 @@ const void *interrupt_vector[] = {
(void*) (0UL), /* Reserved */
(void*) isr_pendsv, /* pendSV interrupt, used for task switching in RIOT */
(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
/* STM specific peripheral handlers */
/* SAM3X8E specific peripheral handlers */
(void*) isr_supc, /* 0 supply controller */
(void*) isr_rstc, /* 1 reset controller */
(void*) isr_rtc, /* 2 real time clock */