From cb4cdee0efdc1b069dd6d341ee0c386ce0a27013 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Wed, 20 Feb 2019 19:13:28 +0100 Subject: [PATCH] boards/common: introduce common code for kw41z boards --- boards/common/kw41z/Makefile | 3 + boards/common/kw41z/Makefile.dep | 6 + boards/common/kw41z/Makefile.features | 8 + boards/common/kw41z/Makefile.include | 13 ++ boards/common/kw41z/board.c | 33 ++++ boards/common/kw41z/include/board_common.h | 44 +++++ boards/common/kw41z/include/cfg_i2c_default.h | 55 ++++++ .../common/kw41z/include/periph_conf_common.h | 181 ++++++++++++++++++ boards/common/kw41z/led_init.c | 44 +++++ 9 files changed, 387 insertions(+) create mode 100644 boards/common/kw41z/Makefile create mode 100644 boards/common/kw41z/Makefile.dep create mode 100644 boards/common/kw41z/Makefile.features create mode 100644 boards/common/kw41z/Makefile.include create mode 100644 boards/common/kw41z/board.c create mode 100644 boards/common/kw41z/include/board_common.h create mode 100644 boards/common/kw41z/include/cfg_i2c_default.h create mode 100644 boards/common/kw41z/include/periph_conf_common.h create mode 100644 boards/common/kw41z/led_init.c diff --git a/boards/common/kw41z/Makefile b/boards/common/kw41z/Makefile new file mode 100644 index 0000000000..17c0db3789 --- /dev/null +++ b/boards/common/kw41z/Makefile @@ -0,0 +1,3 @@ +MODULE = boards_common_kw41z + +include $(RIOTBASE)/Makefile.base diff --git a/boards/common/kw41z/Makefile.dep b/boards/common/kw41z/Makefile.dep new file mode 100644 index 0000000000..72bad09a72 --- /dev/null +++ b/boards/common/kw41z/Makefile.dep @@ -0,0 +1,6 @@ +ifneq (,$(filter saul_default,$(USEMODULE))) + USEMODULE += saul_adc + USEMODULE += saul_gpio +endif + +include $(RIOTCPU)/kinetis/Makefile.dep diff --git a/boards/common/kw41z/Makefile.features b/boards/common/kw41z/Makefile.features new file mode 100644 index 0000000000..5772c683b5 --- /dev/null +++ b/boards/common/kw41z/Makefile.features @@ -0,0 +1,8 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_rtt +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +include $(RIOTCPU)/kinetis/Makefile.features diff --git a/boards/common/kw41z/Makefile.include b/boards/common/kw41z/Makefile.include new file mode 100644 index 0000000000..3957633b96 --- /dev/null +++ b/boards/common/kw41z/Makefile.include @@ -0,0 +1,13 @@ +# define the cpu used by the board +export CPU = kinetis +export CPU_MODEL = mkw41z512vht4 + +# include this module into the build +INCLUDES += -I$(RIOTBOARD)/common/kw41z/include +USEMODULE += boards_common_kw41z + +# This board comes with OpenSDA configured for JLink compatibility +export DEBUG_ADAPTER ?= jlink + +# Include default FRDM board config +include $(RIOTBOARD)/common/frdm/Makefile.include diff --git a/boards/common/kw41z/board.c b/boards/common/kw41z/board.c new file mode 100644 index 0000000000..10ee65ba07 --- /dev/null +++ b/boards/common/kw41z/board.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2017 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_common_kw41z + * @{ + * + * @file + * @brief Board specific initialization for the FRDM-KW41Z + * + * @author Joakim Nohlgård + * + * @} + */ + +#include "board.h" +#include "periph/gpio.h" + +void led_init(void); + +void board_init(void) +{ + /* initialize the CPU core */ + cpu_init(); + + /* initialize LEDs */ + led_init(); +} diff --git a/boards/common/kw41z/include/board_common.h b/boards/common/kw41z/include/board_common.h new file mode 100644 index 0000000000..da80e0b72c --- /dev/null +++ b/boards/common/kw41z/include/board_common.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2017 Eistec AB + * 2019 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup boards_common_kw41z KW41Z common + * @ingroup boards_common + * @brief Shared files and configuration for KW41Z based boards. + * @{ + * + * @file + * @brief Shared configuration for some kw41z-based boards + * + * @author Joakim Nohlgård + * @author Alexandre Abadie + */ + +#ifndef BOARD_COMMON_H +#define BOARD_COMMON_H + +#include "cpu.h" +#include "periph_conf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief Initialize board specific hardware, including clock, LEDs and standard I/O + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_COMMON_H */ +/** @} */ diff --git a/boards/common/kw41z/include/cfg_i2c_default.h b/boards/common/kw41z/include/cfg_i2c_default.h new file mode 100644 index 0000000000..cd04ab0ebd --- /dev/null +++ b/boards/common/kw41z/include/cfg_i2c_default.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2017 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_common_kw41z + * @{ + * + * @file + * @name Default I2C configuration for KW41Z based boards + * + * @author Joakim Nohlgård + */ + +#ifndef CFG_I2C_DEFAULT_H +#define CFG_I2C_DEFAULT_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** +* @name I2C configuration +* @{ +*/ +static const i2c_conf_t i2c_config[] = { + { + .i2c = I2C1, + .scl_pin = GPIO_PIN(PORT_C, 2), + .sda_pin = GPIO_PIN(PORT_C, 3), + .freq = CLOCK_CORECLOCK, + .speed = I2C_SPEED_FAST, + .irqn = I2C1_IRQn, + .scl_pcr = (PORT_PCR_MUX(3)), + .sda_pcr = (PORT_PCR_MUX(3)), + }, +}; +#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) +#define I2C_0_ISR (isr_i2c1) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CFG_I2C_DEFAULT_H */ +/** @} */ diff --git a/boards/common/kw41z/include/periph_conf_common.h b/boards/common/kw41z/include/periph_conf_common.h new file mode 100644 index 0000000000..82de9a3c2f --- /dev/null +++ b/boards/common/kw41z/include/periph_conf_common.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2017 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_common_kw41z + * @{ + * + * @file + * @name Common peripheral MCU configuration for KW41Z based boards + * + * @author Joakim Nohlgård + */ + +#ifndef PERIPH_CONF_COMMON_H +#define PERIPH_CONF_COMMON_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @name Clock system configuration + * @{ + */ +static const clock_config_t clock_config = { + /* + * This configuration results in the system running with the internal clock + * with the following clock frequencies: + * Core: 48 MHz + * Bus: 24 MHz + * Flash: 24 MHz + */ + .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1), + /* unsure if this RTC load cap configuration is correct, but it matches the + * settings used by the example code in the NXP provided SDK */ + .rtc_clc = 0, + /* Use the 32 kHz oscillator as ERCLK32K. Note that the values here have a + * different mapping for the KW41Z than the values used in the Kinetis K series */ + .osc32ksel = SIM_SOPT1_OSC32KSEL(0), + .clock_flags = + KINETIS_CLOCK_OSC0_EN | /* Enable RSIM oscillator */ + KINETIS_CLOCK_RTCOSC_EN | + KINETIS_CLOCK_USE_FAST_IRC | + KINETIS_CLOCK_MCGIRCLK_EN | /* Used for LPUART clocking */ + KINETIS_CLOCK_MCGIRCLK_STOP_EN | + 0, + /* Using FEI mode by default, the external crystal settings below are only + * used if mode is changed to an external mode (PEE, FBE, or FEE) */ + .default_mode = KINETIS_MCG_MODE_FEI, + /* The crystal connected to RSIM OSC is 32 MHz */ + .erc_range = KINETIS_MCG_ERC_RANGE_VERY_HIGH, + .osc_clc = 0, /* no load cap configuration */ + .oscsel = MCG_C7_OSCSEL(0), /* Use RSIM for external clock */ + .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */ + .fll_frdiv = MCG_C1_FRDIV(0b101), /* Divide by 1024 */ + .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FEI FLL freq = 48 MHz */ + .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1280, /* FEE FLL freq = 40 MHz */ +}; +/* Radio xtal frequency, either 32 MHz or 26 MHz */ +#define CLOCK_RADIOXTAL (32000000ul) +/* CPU core clock, the MCG clock output frequency */ +#define CLOCK_CORECLOCK (48000000ul) +#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2) +#define CLOCK_MCGIRCLK (4000000ul) +/** @} */ + +/** + * @name Timer configuration + * @{ + */ +#define PIT_NUMOF (1U) +#define PIT_CONFIG { \ + { \ + .prescaler_ch = 0, \ + .count_ch = 1, \ + }, \ + } +#define LPTMR_NUMOF (1U) +#define LPTMR_CONFIG { \ + { \ + .dev = LPTMR0, \ + .irqn = LPTMR0_IRQn, \ + .src = 2, \ + .base_freq = 32768u, \ + } \ + } +#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF)) +#define PIT_BASECLOCK (CLOCK_BUSCLOCK) +#define LPTMR_ISR_0 isr_lptmr0 +/** @} */ + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = LPUART0, + .freq = CLOCK_MCGIRCLK, + .pin_rx = GPIO_PIN(PORT_C, 6), + .pin_tx = GPIO_PIN(PORT_C, 7), + .pcr_rx = PORT_PCR_MUX(4), + .pcr_tx = PORT_PCR_MUX(4), + .irqn = LPUART0_IRQn, + .scgc_addr = &SIM->SCGC5, + .scgc_bit = SIM_SCGC5_LPUART0_SHIFT, + .mode = UART_MODE_8N1, + .type = KINETIS_LPUART, + }, +}; +#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) +#define LPUART_0_ISR isr_lpuart0 +/* Use MCGIRCLK (internal reference 4 MHz clock) */ +#define LPUART_0_SRC 3 +/** @} */ + +/** + * @name SPI clock configuration + * + * Clock configuration values based on the configured 16Mhz module clock. + * + * Auto-generated by: + * cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c + * +* @{ +*/ +static const uint32_t spi_clk_config[] = { + ( + SPI_CTAR_PBR(2) | SPI_CTAR_BR(5) | /* -> 100000Hz */ + SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(4) | + SPI_CTAR_PASC(2) | SPI_CTAR_ASC(4) | + SPI_CTAR_PDT(2) | SPI_CTAR_DT(4) + ), + ( + SPI_CTAR_PBR(2) | SPI_CTAR_BR(3) | /* -> 400000Hz */ + SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(2) | + SPI_CTAR_PASC(2) | SPI_CTAR_ASC(2) | + SPI_CTAR_PDT(2) | SPI_CTAR_DT(2) + ), + ( + SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | /* -> 1000000Hz */ + SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(3) | + SPI_CTAR_PASC(0) | SPI_CTAR_ASC(3) | + SPI_CTAR_PDT(0) | SPI_CTAR_DT(3) + ), + ( + SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */ + SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) | + SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) | + SPI_CTAR_PDT(0) | SPI_CTAR_DT(1) + ), + ( + SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */ + SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(0) | + SPI_CTAR_PASC(0) | SPI_CTAR_ASC(0) | + SPI_CTAR_PDT(0) | SPI_CTAR_DT(0) + ) +}; +/** @} */ + +/** + * @name Random Number Generator configuration + * @{ + */ +#define KINETIS_TRNG TRNG +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_COMMON_H */ +/** @} */ diff --git a/boards/common/kw41z/led_init.c b/boards/common/kw41z/led_init.c new file mode 100644 index 0000000000..28fdc8659e --- /dev/null +++ b/boards/common/kw41z/led_init.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2019 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_kw41z + * @{ + * + * @file + * @brief Common led initialization for KW41Z based boards + * + * @author Alexandre Abadie + * + * @} + */ + +#include "board.h" +#include "cpu.h" +#include "periph/gpio.h" + +void led_init(void) +{ + /* initialize and turn off LEDs */ +#ifdef LED0_PIN + gpio_init(LED0_PIN, GPIO_OUT); + gpio_set(LED0_PIN); +#endif +#ifdef LED1_PIN + gpio_init(LED1_PIN, GPIO_OUT); + gpio_set(LED1_PIN); +#endif +#ifdef LED2_PIN + gpio_init(LED2_PIN, GPIO_OUT); + gpio_set(LED2_PIN); +#endif +#ifdef LED3_PIN + gpio_init(LED3_PIN, GPIO_OUT); + gpio_set(LED3_PIN); +#endif +}