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drivers/adxl345: update driver to the new I2C API

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Signed-off-by: dylad <dylan.laduranty@mesotic.com>
This commit is contained in:
dylad 2018-05-25 13:37:58 +02:00
parent c2eb316039
commit cfc826012f
1 changed files with 32 additions and 41 deletions
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73
drivers/adxl345/adxl345.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2017 Mesotic SAS
* Copyright (C) 2017-2018 Mesotic SAS
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -29,8 +29,6 @@
#define ENABLE_DEBUG (0)
#include "debug.h"
#define I2C_SPEED I2C_SPEED_NORMAL
#define BUS (dev->i2c)
#define ADDR (dev->addr)
@ -49,28 +47,21 @@ int adxl345_init(adxl345_t *dev, const adxl345_params_t* params)
/* Acquire exclusive access */
i2c_acquire(BUS);
/* Initialize I2C interface */
if (i2c_init_master(BUS, I2C_SPEED) < 0) {
i2c_release(BUS);
DEBUG("[adxl345] init - error: unable to initialize I2C bus\n");
return ADXL345_NOI2C;
}
/* test if the target device responds */
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_CHIP_ID_REG, &reg);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_CHIP_ID_REG, &reg, 0);
if (reg != ACCEL_ADXL345_CHIP_ID) {
i2c_release(BUS);
DEBUG("[adxl345] init - error: invalid id value [0x%02x]\n", (int)reg);
return ADXL345_NODEV;
}
/* configure the user offset */
i2c_write_regs(BUS, ADDR, ACCEL_ADXL345_OFFSET_X, dev->params->offset, 3);
i2c_write_regs(BUS, ADDR, ACCEL_ADXL345_OFFSET_X, dev->params->offset, 3, 0);
/* Basic device setup */
reg = (dev->params->full_res | dev->params->range);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_DATA_FORMAT, reg);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_BW_RATE, dev->params->rate);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_DATA_FORMAT, reg, 0);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_BW_RATE, dev->params->rate, 0);
/* Put device in measure mode */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, MEASURE_BIT);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, MEASURE_BIT, 0);
/* Release the bus */
i2c_release(BUS);
@ -87,7 +78,7 @@ void adxl345_read(const adxl345_t *dev, adxl345_data_t *data)
assert(dev && data);
i2c_acquire(BUS);
i2c_read_regs(BUS, ADDR, ACCEL_ADXL345_DATA_X0, result, 6);
i2c_read_regs(BUS, ADDR, ACCEL_ADXL345_DATA_X0, result, 6, 0);
i2c_release(BUS);
data->x = (((result[1] << 8)+result[0]) * dev->scale_factor);
@ -103,33 +94,33 @@ void adxl345_set_interrupt(const adxl345_t *dev)
i2c_acquire(BUS);
/* Set threshold */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_TAP, dev->interrupt.thres_tap);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_TAP, dev->interrupt.thres_tap, 0);
/* Set Map */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_INT_MAP, dev->interrupt.map);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_INT_MAP, dev->interrupt.map, 0);
/* Set Duration */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_DUR, dev->interrupt.thres_dur);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_DUR, dev->interrupt.thres_dur, 0);
/* Enable axes */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_AXES, dev->interrupt.tap_axes);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_AXES, dev->interrupt.tap_axes, 0);
/* Set source */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_INT_SOURCE, dev->interrupt.source);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_INT_SOURCE, dev->interrupt.source, 0);
/* Set latent threshold */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_LAT, dev->interrupt.thres_latent);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_LAT, dev->interrupt.thres_latent, 0);
/* Set window threshold */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_WIN, dev->interrupt.thres_window);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TAP_WIN, dev->interrupt.thres_window, 0);
/* Set activity threshold */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_ACT, dev->interrupt.thres_act);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_ACT, dev->interrupt.thres_act, 0);
/* Set inactivity threshold */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_INACT, dev->interrupt.thres_inact);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_INACT, dev->interrupt.thres_inact, 0);
/* Set inactivity time */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TIME_INACT, dev->interrupt.time_inact);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TIME_INACT, dev->interrupt.time_inact, 0);
/* Set free-fall threshold */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_FF, dev->interrupt.thres_ff);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_THRESH_FF, dev->interrupt.thres_ff, 0);
/* Set free-fall time */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TIME_FF, dev->interrupt.time_ff);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_TIME_FF, dev->interrupt.time_ff, 0);
/* Set axis control */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_ACT_INACT_CTL, dev->interrupt.act_inact);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_ACT_INACT_CTL, dev->interrupt.act_inact, 0);
/* Enable interrupt */
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_INT_ENABLE, dev->interrupt.enable);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_INT_ENABLE, dev->interrupt.enable, 0);
/* Release the bus */
i2c_release(BUS);
@ -144,9 +135,9 @@ void adxl345_set_measure(const adxl345_t *dev)
DEBUG("[adxl345] set device to measure mode\n");
i2c_acquire(BUS);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, &reg);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, &reg, 0);
reg |= MEASURE_BIT;
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg, 0);
i2c_release(BUS);
}
@ -159,9 +150,9 @@ void adxl345_set_standby(const adxl345_t *dev)
DEBUG("[adxl345] set device to standby mode\n");
i2c_acquire(BUS);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, &reg);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, &reg, 0);
reg &= ~MEASURE_BIT;
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg, 0);
i2c_release(BUS);
}
@ -174,9 +165,9 @@ void adxl345_set_sleep(const adxl345_t *dev)
DEBUG("[adxl345] set device to sleep mode\n");
i2c_acquire(BUS);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, &reg);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, &reg, 0);
reg |= SLEEP_BIT;
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg, 0);
i2c_release(BUS);
}
@ -189,9 +180,9 @@ void adxl345_set_autosleep(const adxl345_t *dev)
DEBUG("[adxl345] set device to autosleep mode\n");
i2c_acquire(BUS);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, &reg);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, &reg, 0);
reg |= AUTOSLEEP_BIT;
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_POWER_CTL, reg, 0);
i2c_release(BUS);
}
@ -204,9 +195,9 @@ void adxl345_set_bandwidth_rate(const adxl345_t *dev, uint8_t bw_rate)
DEBUG("[adxl345] set device rate to %d Hz\n", (int)bw_rate);
i2c_acquire(BUS);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_BW_RATE, &reg);
i2c_read_reg(BUS, ADDR, ACCEL_ADXL345_BW_RATE, &reg, 0);
reg |= bw_rate;
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_BW_RATE, reg);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_BW_RATE, reg, 0);
i2c_release(BUS);
}
@ -222,6 +213,6 @@ void adxl345_set_fifo_mode(const adxl345_t *dev, uint8_t mode,
i2c_acquire(BUS);
reg = ((mode << FIFO_MODE_POS) | (output << FIFO_TRIGGER_POS) | value);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_FIFO_CTL, reg);
i2c_write_reg(BUS, ADDR, ACCEL_ADXL345_FIFO_CTL, reg, 0);
i2c_release(BUS);
}