diff --git a/cpu/esp32/bootloader/sdkconfig.h b/cpu/esp32/bootloader/sdkconfig.h index a627e97f1e..fd1d6a6c43 100644 --- a/cpu/esp32/bootloader/sdkconfig.h +++ b/cpu/esp32/bootloader/sdkconfig.h @@ -33,6 +33,8 @@ #if defined(CPU_FAM_ESP32) #include "sdkconfig_default_esp32.h" +#elif defined(CPU_FAM_ESP32C3) +#include "sdkconfig_default_esp32c3.h" #else #error "ESP32x family implementation missing" #endif diff --git a/cpu/esp32/bootloader/sdkconfig_default_esp32c3.h b/cpu/esp32/bootloader/sdkconfig_default_esp32c3.h new file mode 100644 index 0000000000..bab0fceb7b --- /dev/null +++ b/cpu/esp32/bootloader/sdkconfig_default_esp32c3.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_esp32 + * @{ + * + * @file + * @brief Default SDK configuration for the ESP32C3 SoC bootloader + * + * @author Gunar Schorcht + */ + +#ifndef SDKCONFIG_DEFAULT_ESP32C3_H +#define SDKCONFIG_DEFAULT_ESP32C3_H + +#ifndef DOXYGEN + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 160 +#endif + +#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1 +#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 +#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0 +#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0 +#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1 +#define CONFIG_BOOTLOADER_WDT_ENABLE 1 +#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 + +#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1 +#define CONFIG_ESP_CONSOLE_UART 1 +#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1 +#define CONFIG_ESP_CONSOLE_UART_NUM 0 + +#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM +#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT + +#define CONFIG_EFUSE_MAX_BLK_LEN 192 + +#define CONFIG_ESP32C3_DEBUG_OCDAWARE 1 +#define CONFIG_ESP32C3_REV_MIN 3 + +#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0005 + +#define CONFIG_LOG_DEFAULT_LEVEL 3 +#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1 + +#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 +#define CONFIG_PARTITION_TABLE_MD5 1 + +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 + +#ifdef __cplusplus +} +#endif + +#endif /* DOXYGEN */ +#endif /* SDKCONFIG_DEFAULT_ESP32C3_H */ +/** @} */ diff --git a/cpu/esp32/include/cpu_conf.h b/cpu/esp32/include/cpu_conf.h index 1d28003dcb..9d1335efbc 100644 --- a/cpu/esp32/include/cpu_conf.h +++ b/cpu/esp32/include/cpu_conf.h @@ -63,6 +63,8 @@ /* include ESP32x SoC specific compile time configurations */ #if defined(CPU_FAM_ESP32) #include "cpu_conf_esp32.h" +#elif defined(CPU_FAM_ESP32C3) +#include "cpu_conf_esp32c3.h" #else #error "ESP32x family implementation missing" #endif diff --git a/cpu/esp32/include/cpu_conf_esp32c3.h b/cpu/esp32/include/cpu_conf_esp32c3.h new file mode 100644 index 0000000000..d28307c11b --- /dev/null +++ b/cpu/esp32/include/cpu_conf_esp32c3.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_esp32 + * @ingroup config + * @brief Compile-time configuration macros for ESP32-C3 SoCs + * @{ + * + * @file + * @brief ESP32-C3 specific compile-time configuration + * + * @author Gunar Schorcht + */ + +#ifndef CPU_CONF_ESP32C3_H +#define CPU_CONF_ESP32C3_H + +#ifndef ESP_ISR_STACKSIZE +/** Stack size used in interrupt context */ +#define ESP_ISR_STACKSIZE (THREAD_STACKSIZE_DEFAULT) +#endif /* ESP_ISR_STACKSIZE */ + +/** Number of DRAM sections that can be used as heap. */ +#define NUM_HEAPS (1) + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* CPU_CONF_ESP32C3_H */ +/** @} */ diff --git a/cpu/esp32/include/periph_cpu.h b/cpu/esp32/include/periph_cpu.h index eb6c3e80f5..90cd60ebaa 100644 --- a/cpu/esp32/include/periph_cpu.h +++ b/cpu/esp32/include/periph_cpu.h @@ -153,6 +153,7 @@ typedef enum { * details, see: * * - \ref esp32_adc_channels_esp32 "ESP32" + * - \ref esp32_adc_channels_esp32c3 "ESP32-C3" * * #ADC_GPIOS in the board-specific peripheral configuration defines the * list of GPIOs that can be used as ADC channels on the board, for example: @@ -209,6 +210,7 @@ typedef enum { * For the GPIO that can be used with this function, see: * * - \ref esp32_adc_channels_esp32 "ESP32" + * - \ref esp32_adc_channels_esp32c3 "ESP32-C3" * * @{ */ @@ -735,6 +737,8 @@ typedef struct { */ #if defined(CPU_FAM_ESP32) #include "periph_cpu_esp32.h" +#elif defined(CPU_FAM_ESP32C3) +#include "periph_cpu_esp32c3.h" #else #error "ESP32x family implementation missing" #endif diff --git a/cpu/esp32/include/periph_cpu_esp32c3.h b/cpu/esp32/include/periph_cpu_esp32c3.h new file mode 100644 index 0000000000..e9127ba5fa --- /dev/null +++ b/cpu/esp32/include/periph_cpu_esp32c3.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_esp32 + * @{ + * + * @file + * @brief ESP32-C3 specific peripheral configuration + * + * @author Gunar Schorcht + */ + +#ifndef PERIPH_CPU_ESP32C3_H +#define PERIPH_CPU_ESP32C3_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Predefined GPIO names + * @{ + */ +#define GPIO0 (GPIO_PIN(PORT_GPIO, 0)) +#define GPIO1 (GPIO_PIN(PORT_GPIO, 1)) +#define GPIO2 (GPIO_PIN(PORT_GPIO, 2)) +#define GPIO3 (GPIO_PIN(PORT_GPIO, 3)) +#define GPIO4 (GPIO_PIN(PORT_GPIO, 4)) +#define GPIO5 (GPIO_PIN(PORT_GPIO, 5)) +#define GPIO6 (GPIO_PIN(PORT_GPIO, 6)) +#define GPIO7 (GPIO_PIN(PORT_GPIO, 7)) +#define GPIO8 (GPIO_PIN(PORT_GPIO, 8)) +#define GPIO9 (GPIO_PIN(PORT_GPIO, 9)) +#define GPIO10 (GPIO_PIN(PORT_GPIO, 10)) +#define GPIO11 (GPIO_PIN(PORT_GPIO, 11)) +#define GPIO12 (GPIO_PIN(PORT_GPIO, 12)) +#define GPIO13 (GPIO_PIN(PORT_GPIO, 13)) +#define GPIO14 (GPIO_PIN(PORT_GPIO, 14)) +#define GPIO15 (GPIO_PIN(PORT_GPIO, 15)) +#define GPIO16 (GPIO_PIN(PORT_GPIO, 16)) +#define GPIO17 (GPIO_PIN(PORT_GPIO, 17)) +#define GPIO18 (GPIO_PIN(PORT_GPIO, 18)) +#define GPIO19 (GPIO_PIN(PORT_GPIO, 19)) +#define GPIO20 (GPIO_PIN(PORT_GPIO, 20)) +#define GPIO21 (GPIO_PIN(PORT_GPIO, 21)) +/** @} */ + +/** + * @name ADC configuration + * + * ESP32-C3 integrates two 12-bit ADCs (ADC1 and ADC2) with 6 channels in + * total: + * + * - **ADC1** supports 5 channels: GPIO0, GPIO1, GPIO2, GPIO3 and GPIO4 + * - **ADC2** supports 1 channel: GPIO5 or internal signals such as vdd33 + * + * The maximum number of ADC channels #ADC_NUMOF_MAX is 6. + * + * @note + * - ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are + * therefore not available as ADC channels if the modules `esp_wifi` or + * `esp_now` are used. + * - Vref can be read with function #adc_line_vref_to_gpio at GPIO5. + */ + +/** + * @name I2C configuration + * + * ESP32-C3 has one built-in I2C interfaces. + * + * The following table shows the default configuration of I2C interfaces + * used for ESP32-C3 boards. It can be overridden by + * [application-specific configurations](#esp32_application_specific_configurations). + * + *
+ * + * Device | Signal | Pin | Symbol | Remarks + * :----------|:-------|:-------|:--------------|:---------------- + * I2C_DEV(0) | | | `#I2C0_SPEED` | default is `I2C_SPEED_FAST` + * I2C_DEV(0) | SCL | GPIO4 | `#I2C0_SCL` | - + * I2C_DEV(0) | SDA | GPIO5 | `#I2C0_SDA` | - + * + *

+ */ + +/** + * @name PWM configuration + * + * The ESP32-C3 LEDC module has 1 channel group with 6 channels. Each of + * these channels can be clocked by one of the 4 timers. + */ + +/** + * @name SPI configuration + * + * ESP32-C3 has three SPI controllers where SPI0 and SPI1 share the same bus + * and can only operate in memory mode while SPI2 can be used as general + * purpose SPI: + * + * - controller SPI0 is reserved for external memories like flash and PSRAM + * - controller SPI1 is reserved for external memories like flash and PSRAM + * - controller SPI2 can be used for peripherals (also called FSPI) + * + * Thus, only SPI2 (FSPI) can be used as general purpose SPI in RIOT as + * SPI_DEV(0). + * + * The following table shows the pin configuration used by default, even + * though it **can vary** from board to board. + * + *
+ * + * Device (Alias) | Signal | Pin | Symbol | Remarks + * :-----------------------|:------:|:-------|:-----------:|:--------------------------- + * `SPI_HOST0`/`SPI_HOST1` | SPICS0 | GPIO14 | - | reserved for Flash and PSRAM + * `SPI_HOST0`/`SPI_HOST1` | SPICLK | GPIO15 | - | reserved for Flash and PSRAM + * `SPI_HOST0`/`SPI_HOST1` | SPID | GPIO16 | - | reserved for Flash and PSRAM + * `SPI_HOST0`/`SPI_HOST1` | SPIQ | GPIO17 | - | reserved for Flash and PSRAM + * `SPI_HOST0`/`SPI_HOST1` | SPIHD | GPIO12 | - | reserved for Flash and PSRAM (only in `qio` or `qout` mode) + * `SPI_HOST0`/`SPI_HOST1` | SPIWP | GPIO13 | - | reserved for Flash and PSRAM (only in `qio` or `qout` mode) + * `SPI_HOST2` (`FSPI`) | SCK | GPIO6 |`#SPI0_SCK` | can be used + * `SPI_HOST2` (`FSPI`) | MOSI | GPIO7 |`#SPI0_MOSI` | can be used + * `SPI_HOST2` (`FSPI`) | MISO | GPIO2 |`#SPI0_MISO` | can be used + * `SPI_HOST2` (`FSPI`) | CS0 | GPIO10 |`#SPI0_CS0` | can be used + * + *

+ */ + +/** + * @name Timer configuration depending on which implementation is used + * + * ESP32-C3 has two timer groups with one channel each. + */ + +#ifdef MODULE_ESP_HW_COUNTER +#error "Counter based timers are not supported by ESP32-C3" +#endif + +/** + * @name UART configuration + * + * ESP32-C3 integrates two UART interfaces. The following default pin + * configuration of UART interfaces as used by a most boards can be overridden + * by the application, see section [Application-Specific Configurations] + * (#esp32_application_specific_configurations). + * + *
+ * + * Device |Signal|Pin |Symbol |Remarks + * :-----------|:-----|:-------|:-----------|:---------------- + * UART_DEV(0) | TxD | GPIO21 |`#UART0_TXD`| cannot be changed + * UART_DEV(0) | RxD | GPIO20 |`#UART0_RXD`| cannot be changed + * UART_DEV(1) | TxD | - |`#UART1_TXD`| optional, can be overridden (no direct I/O) + * UART_DEV(1) | RxD | - |`#UART1_RXD`| optional, can be overridden (no direct I/O) + * + *

+ * + */ + +#ifdef MODULE_PERIPH_CAN +#include "can_esp.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CPU_ESP32C3_H */ +/** @} */ diff --git a/cpu/esp32/include/sdkconfig.h b/cpu/esp32/include/sdkconfig.h index 7e1487e234..8782ca317d 100644 --- a/cpu/esp32/include/sdkconfig.h +++ b/cpu/esp32/include/sdkconfig.h @@ -46,6 +46,8 @@ */ #if defined(CPU_FAM_ESP32) #include "sdkconfig_esp32.h" +#elif defined(CPU_FAM_ESP32C3) +#include "sdkconfig_esp32c3.h" #else #error "ESP32x family implementation missing" #endif diff --git a/cpu/esp32/include/sdkconfig_esp32c3.h b/cpu/esp32/include/sdkconfig_esp32c3.h new file mode 100644 index 0000000000..b81ad1260d --- /dev/null +++ b/cpu/esp32/include/sdkconfig_esp32c3.h @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_esp32 + * @{ + * + * @file + * @brief SDK configuration used by the ESP-IDF for ESP32C3 + * + * The SDK configuration can be partially overridden by application-specific + * board configuration. + * + * @author Gunar Schorcht + */ + +#ifndef SDKCONFIG_ESP32C3_H +#define SDKCONFIG_ESP32C3_H + +#ifndef DOXYGEN + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock configuration + * @{ + */ + +/* Mapping of Kconfig defines to the respective enumeration values */ +#if CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_2 +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 2 +#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_5 +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 5 +#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_10 +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 10 +#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_20 +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 20 +#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_40 +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 40 +#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_80 +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 80 +#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_160 +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 160 +#endif + +/** + * @brief Defines the CPU frequency [values = 2, 5, 10, 10, 40, 80, 160] + */ +#ifndef CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 80 +#endif +/** + * @brief Mapping configured ESP32 default clock to CLOCK_CORECLOCK define + */ +#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ) +/** @} */ + +/** + * Default console configuration + * + * STDIO_UART_BAUDRATE is used as CONFIG_CONSOLE_UART_BAUDRATE and + * can be overridden by an application specific configuration. + */ +#define CONFIG_CONSOLE_UART_NUM 0 +#define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM + +#ifndef CONFIG_CONSOLE_UART_BAUDRATE +#define CONFIG_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE +#endif + +/** + * Log output configuration (DO NOT CHANGE) + */ +#ifndef CONFIG_LOG_DEFAULT_LEVEL +#define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL +#endif +#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL + +/** + * RTC clock configuration + */ +#ifdef MODULE_ESP_RTC_TIMER_32K +#define CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS 1 +#endif + +#define CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES (8 * 1024) + +/** + * System specific configuration (DO NOT CHANGE) + */ +#ifdef MODULE_NEWLIB_NANO +#define CONFIG_NEWLIB_NANO_FORMAT 1 +#endif + +#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1 +#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32 +#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2560 + +#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1 +#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1 +#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1 +#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584 +#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE + +#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1 +#define CONFIG_APP_BUILD_BOOTLOADER 1 +#define CONFIG_APP_BUILD_GENERATE_BINARIES 1 +#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1 +#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1 + +#define CONFIG_EFUSE_MAX_BLK_LEN 256 + +#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 +#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv" +#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv" +#define CONFIG_PARTITION_TABLE_SINGLE_APP 1 + +/** + * Bluetooth configuration (DO NOT CHANGE) + */ +#define CONFIG_BT_ENABLED 0 +#define CONFIG_BT_RESERVE_DRAM 0 + +/** + * SPI Flash driver configuration (DO NOT CHANGE) + */ +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 +#define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1 +#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1 +#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1 +#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20 +#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1 +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 +#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1 +#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192 +#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS +#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1 + +/** + * Serial flasher config (defined by CFLAGS, only sanity check here) + */ +#if !defined(CONFIG_FLASHMODE_DOUT) && \ + !defined(CONFIG_FLASHMODE_DIO) && \ + !defined(CONFIG_FLASHMODE_QOUT) && \ + !defined(CONFIG_FLASHMODE_QIO) +#error "Flash mode not configured" +#endif + +/** + * Wi-Fi driver configuration (DO NOT CHANGE) + */ +#ifdef MODULE_ESP_WIFI_ANY +#define CONFIG_ESP32_WIFI_ENABLED 1 +#endif +#if defined(MODULE_ESP_WIFI_AP) || defined(MODULE_ESP_NOW) +#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1 +#endif + +#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER +#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1 +#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1 +#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32 +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1 +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32 +#define CONFIG_ESP32_WIFI_ENABLED 1 +#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1 +#define CONFIG_ESP32_WIFI_IRAM_OPT 1 +#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32 +#if MODULE_ESP_IDF_NVS_ENABLED +#define CONFIG_ESP32_WIFI_NVS_ENABLED 1 +#endif +#define CONFIG_ESP32_WIFI_RX_BA_WIN 6 +#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1 +#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752 +#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10 +#define CONFIG_ESP32_WIFI_TX_BA_WIN 6 +#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1 + +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1 +#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20 + +/** + * PHY configuration + */ +#if MODULE_ESP_IDF_NVS_ENABLED +#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1 +#endif + +#define CONFIG_ESP_PHY_MAX_TX_POWER 20 +#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20 + +#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE +#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER + +#ifdef __cplusplus +} +#endif + +#endif /* DOXYGEN */ +#endif /* SDKCONFIG_ESP32C3_H */ +/** @} */ diff --git a/dist/tools/doccheck/exclude_patterns b/dist/tools/doccheck/exclude_patterns index 9d00920ca1..9b4469ee4d 100644 --- a/dist/tools/doccheck/exclude_patterns +++ b/dist/tools/doccheck/exclude_patterns @@ -14968,6 +14968,7 @@ pkg/nimble/autoadv/include/nimble_autoadv_params\.h:[0-9]+: warning: Member NIMB pkg/nimble/autoadv/include/nimble_autoadv_params\.h:[0-9]+: warning: Member NIMBLE_AUTOADV_FILTER_POLICY \(macro definition\) of file nimble_autoadv_params\.h is not documented\. pkg/nimble/autoadv/include/nimble_autoadv_params\.h:[0-9]+: warning: Member NIMBLE_AUTOADV_PARAMS \(macro definition\) of file nimble_autoadv_params\.h is not documented\. cpu/esp32/include/periph_cpu_esp32\.h:[0-9]+: warning: Member GPIO[0-9]+ \(macro definition\) of file periph_cpu_esp32\.h is not documented. +cpu/esp32/include/periph_cpu_esp32c3\.h:[0-9]+: warning: Member GPIO[0-9]+ \(macro definition\) of file periph_cpu_esp32c3\.h is not documented. boards/waveshare\-nrf52840\-eval\-kit/include/arduino_pinmap\.h:[0-9]+: warning: Member ARDUINO_PIN_[A0-9]+ \(macro definition\) of file arduino_pinmap\.h is not documented. boards/waveshare\-nrf52840\-eval\-kit/include/arduino_pinmap\.h:[0-9]+: warning: Member ARDUINO_[A0-9]+ \(macro definition\) of file arduino_pinmap\.h is not documented. boards/waveshare\-nrf52840\-eval\-kit/include/board\.h:[0-9]+: warning: Member LED0_PIN \(macro definition\) of file board\.h is not documented.