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cpu/nrf5x: unificitaion of GPIO driver

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This commit is contained in:
Hauke Petersen 2016-02-07 12:56:27 +01:00
parent 3745487b95
commit d1808717cb
3 changed files with 41 additions and 156 deletions
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127
cpu/nrf51/periph/gpio.c
View File

@ -1,127 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_nrf51822
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* NOTE: this GPIO driver implementation supports due to hardware limitations
* only one pin configured as external interrupt source at a time!
*
* @author Christian Kühling <kuehling@zedat.fu-berlin.de>
* @author Timo Ziegler <timo.ziegler@fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "sched.h"
#include "thread.h"
#include "periph/gpio.h"
#include "periph_conf.h"
/**
* @brief Place to store the interrupt context
*/
static gpio_isr_ctx_t exti_chan;
int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pullup)
{
/* configure pin direction, input buffer and pull resistor state */
NRF_GPIO->PIN_CNF[pin] = ((dir << GPIO_PIN_CNF_DIR_Pos) |
(dir << GPIO_PIN_CNF_INPUT_Pos) |
(pullup << GPIO_PIN_CNF_PULL_Pos));
return 0;
}
int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
/* disable external interrupt in case one is active */
NRF_GPIOTE->INTENSET &= ~(GPIOTE_INTENSET_IN0_Msk);
/* save callback */
exti_chan.cb = cb;
exti_chan.arg = arg;
/* configure pin as input */
gpio_init(pin, GPIO_DIR_IN, pullup);
/* set interrupt priority and enable global GPIOTE interrupt */
NVIC_EnableIRQ(GPIOTE_IRQn);
/* configure the GPIOTE channel: set even mode, pin and active flank */
NRF_GPIOTE->CONFIG[0] = (GPIOTE_CONFIG_MODE_Event |
(pin << GPIOTE_CONFIG_PSEL_Pos) |
(flank << GPIOTE_CONFIG_POLARITY_Pos));
/* enable external interrupt */
NRF_GPIOTE->INTENSET |= GPIOTE_INTENSET_IN0_Msk;
return 0;
}
/*
* the gpio_init_mux function is not defined as it is not needed for this CPU
*/
void gpio_irq_enable(gpio_t pin)
{
(void) pin;
NRF_GPIOTE->INTENSET |= GPIOTE_INTENSET_IN0_Msk;
}
void gpio_irq_disable(gpio_t dev)
{
(void) dev;
NRF_GPIOTE->INTENCLR |= GPIOTE_INTENSET_IN0_Msk;
}
int gpio_read(gpio_t pin)
{
if (NRF_GPIO->DIR & (1 << pin)) {
return (NRF_GPIO->OUT & (1 << pin)) ? 1 : 0;
}
else {
return (NRF_GPIO->IN & (1 << pin)) ? 1 : 0;
}
}
void gpio_set(gpio_t pin)
{
NRF_GPIO->OUTSET = (1 << pin);
}
void gpio_clear(gpio_t pin)
{
NRF_GPIO->OUTCLR = (1 << pin);
}
void gpio_toggle(gpio_t pin)
{
NRF_GPIO->OUT ^= (1 << pin);
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
NRF_GPIO->OUTSET = (1 << pin);
} else {
NRF_GPIO->OUTCLR = (1 << pin);
}
}
void isr_gpiote(void)
{
if (NRF_GPIOTE->EVENTS_IN[0] == 1)
{
NRF_GPIOTE->EVENTS_IN[0] = 0;
exti_chan.cb(exti_chan.arg);
}
if (sched_context_switch_request) {
thread_yield();
}
}

35
cpu/nrf5x_common/include/periph_cpu.h
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@ -25,6 +25,29 @@
extern "C" {
#endif
/**
* @brief Use base register as defined by the CPU family
*/
#if defined(CPU_FAM_NRF51)
#define GPIO_BASE (NRF_GPIO)
#elif defined(CPU_FAM_NRF52)
#define GPIO_BASE (NRF_P0)
#else
#error "nrf5x_common/periph/gpio: no valid CPU_FAM defined"
#endif
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (8U)
/**
* @brief Override macro for defining GPIO pins
*
* The port definition is used (and zeroed) to suppress compiler warnings
*/
#define GPIO_PIN(x,y) ((x & 0) | y)
/**
* @brief Override GPIO pull register select values
* @{
@ -49,18 +72,6 @@ typedef enum {
} gpio_flank_t;
/** @} */
/**
* @brief Override macro for defining GPIO pins
*
* The port definition is used (and zeroed) to suppress compiler warnings
*/
#define GPIO_PIN(x,y) ((x & 0) | y)
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (8U)
#ifdef __cplusplus
}
#endif

35
cpu/nrf52/periph/gpio.c → cpu/nrf5x_common/periph/gpio.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2015 Jan Wagner <mail@jwagner.eu>
* 2016 Freie Universität Berlin
* 2015-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -8,15 +8,17 @@
*/
/**
* @ingroup cpu_nrf52
* @ingroup cpu_nrf5x_common
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* NOTE: this GPIO driver implementation supports due to hardware limitations
* only one pin configured as external interrupt source at a time!
* @note This GPIO driver implementation supports only one pin to be
* defined as external interrupt.
*
* @author Christian Kühling <kuehling@zedat.fu-berlin.de>
* @author Timo Ziegler <timo.ziegler@fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Jan Wagner <mail@jwagner.eu>
*
@ -27,6 +29,7 @@
#include "sched.h"
#include "thread.h"
#include "periph/gpio.h"
#include "periph_cpu.h"
#include "periph_conf.h"
/**
@ -38,11 +41,9 @@ static gpio_isr_ctx_t exti_chan;
int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pullup)
{
/* configure pin direction, input buffer and pull resistor state */
NRF_P0->PIN_CNF[pin] = ((dir << GPIO_PIN_CNF_DIR_Pos) |
(dir << GPIO_PIN_CNF_INPUT_Pos) |
(pullup << GPIO_PIN_CNF_PULL_Pos));
printf("cfg[%i] 0x%08x\n", (int)pin, (unsigned)NRF_P0->PIN_CNF[pin]);
GPIO_BASE->PIN_CNF[pin] = ((dir << GPIO_PIN_CNF_DIR_Pos) |
(dir << GPIO_PIN_CNF_INPUT_Pos) |
(pullup << GPIO_PIN_CNF_PULL_Pos));
return 0;
}
@ -81,35 +82,35 @@ void gpio_irq_disable(gpio_t pin)
int gpio_read(gpio_t pin)
{
if (NRF_P0->DIR & (1 << pin)) {
return (NRF_P0->OUT & (1 << pin)) ? 1 : 0;
if (GPIO_BASE->DIR & (1 << pin)) {
return (GPIO_BASE->OUT & (1 << pin)) ? 1 : 0;
}
else {
return (NRF_P0->IN & (1 << pin)) ? 1 : 0;
return (GPIO_BASE->IN & (1 << pin)) ? 1 : 0;
}
}
void gpio_set(gpio_t pin)
{
NRF_P0->OUTSET = (1 << pin);
GPIO_BASE->OUTSET = (1 << pin);
}
void gpio_clear(gpio_t pin)
{
NRF_P0->OUTCLR = (1 << pin);
GPIO_BASE->OUTCLR = (1 << pin);
}
void gpio_toggle(gpio_t pin)
{
NRF_P0->OUT ^= (1 << pin);
GPIO_BASE->OUT ^= (1 << pin);
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
NRF_P0->OUTSET = (1 << pin);
GPIO_BASE->OUTSET = (1 << pin);
} else {
NRF_P0->OUTCLR = (1 << pin);
GPIO_BASE->OUTCLR = (1 << pin);
}
}