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cpu/msp430: fix spi clk config for msp430f1xxx

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This commit is contained in:
PeterKietzmann 2016-10-07 17:10:41 +02:00
parent b15115cb10
commit d4ee66cfb7
1 changed files with 13 additions and 10 deletions
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23
cpu/msp430fxyz/periph/spi.c
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@ -52,18 +52,21 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
SPI_DEV->TCTL = (USART_TCTL_SSEL_SMCLK | USART_TCTL_STC);
/* set polarity and phase */
switch (conf) {
case SPI_CONF_FIRST_RISING:
SPI_DEV->TCTL |= (USART_TCTL_CKPH & ~(USART_TCTL_CKPL));
break;
case SPI_CONF_SECOND_RISING:
SPI_DEV->TCTL |= USART_TCTL_CKPH;
SPI_DEV->TCTL |= (~(USART_TCTL_CKPH) & ~(USART_TCTL_CKPL));
break;
case SPI_CONF_FIRST_FALLING:
SPI_DEV->TCTL |= SPI_CONF_FIRST_FALLING;
SPI_DEV->TCTL |= (USART_TCTL_CKPH & USART_TCTL_CKPL);
break;
case SPI_CONF_SECOND_FALLING:
SPI_DEV->TCTL |= (USART_TCTL_CKPH | SPI_CONF_FIRST_FALLING);
SPI_DEV->TCTL |= (~(USART_TCTL_CKPH) & USART_TCTL_CKPL);
break;
default:
/* do nothing */
break;
/* invalid clock setting */
return -2;
}
/* configure clock - we use no modulation for now */
uint32_t br = CLOCK_CMCLK;
@ -122,20 +125,20 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
/* set polarity and phase */
switch (conf) {
case SPI_CONF_FIRST_RISING:
SPI_DEV->CTL0 |= (USCI_SPI_CTL0_CKPH & ~(USCI_SPI_CTL0_CKPL));
SPI_DEV->CTL0 |= USCI_SPI_CTL0_CKPH;
break;
case SPI_CONF_SECOND_RISING:
SPI_DEV->CTL0 |= (~(USCI_SPI_CTL0_CKPH) & ~(USCI_SPI_CTL0_CKPL));
/* nothong to be done here */
break;
case SPI_CONF_FIRST_FALLING:
SPI_DEV->CTL0 |= (USCI_SPI_CTL0_CKPH & USCI_SPI_CTL0_CKPL);
break;
case SPI_CONF_SECOND_FALLING:
SPI_DEV->CTL0 |= (~(USCI_SPI_CTL0_CKPH) & USCI_SPI_CTL0_CKPL);
SPI_DEV->CTL0 |= USCI_SPI_CTL0_CKPL;
break;
default:
/* do nothing */
break;
/* invalid clock setting */
return -2;
}
/* configure clock - we use no modulation for now */
uint32_t br = CLOCK_CMCLK;