mirror of
https://github.com/RIOT-OS/RIOT.git
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implemented UART functions
This commit is contained in:
Thomas Eichinger
parent
0fe0018da7
commit
d70982d5ba
74
redbee-econotag/drivers/gpio.c
Normal file
74
redbee-econotag/drivers/gpio.c
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@ -0,0 +1,74 @@
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/*
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* gpio.c - GPIO driver for redbee
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* Copyright (C) 2013 Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*/
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#include "gpio.h"
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inline void gpio_pad_dir(volatile uint64_t data)
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{
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GPIO->PAD_DIR0 = (data & 0xffffffff);
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GPIO->PAD_DIR1 = (data >> 32);
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}
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inline void gpio_data(volatile uint64_t data)
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{
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GPIO->DATA0 = (data & 0xffffffff);
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GPIO->DATA1 = (data >> 32);
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}
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inline uint64_t gpio_data_get(volatile uint64_t bits) {
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uint64_t rdata = 0;
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rdata = GPIO->DATA0 & (bits & 0xffffffff);
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rdata |= (GPIO->DATA1 & (bits >> 32)) << 32;
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return rdata;
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}
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inline void gpio_pad_pu_en(volatile uint64_t data)
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{
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GPIO->PAD_PU_EN0 = (data & 0xffffffff);
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GPIO->PAD_PU_EN1 = (data >> 32);
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}
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inline void gpio_data_sel(volatile uint64_t data)
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{
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GPIO->DATA_SEL0 = (data & 0xffffffff);
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GPIO->DATA_SEL1 = (data >> 32);
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}
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inline void gpio_pad_pu_sel(volatile uint64_t data)
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{
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GPIO->PAD_PU_SEL0 = (data & 0xffffffff);
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GPIO->PAD_PU_SEL1 = (data >> 32);
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}
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inline void gpio_data_set(volatile uint64_t data)
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{
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GPIO->DATA_SET0 = (data & 0xffffffff);
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GPIO->DATA_SET1 = (data >> 32);
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}
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inline void gpio_data_reset(volatile uint64_t data)
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{
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GPIO->DATA_RESET0 = (data & 0xffffffff);
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GPIO->DATA_RESET1 = (data >> 32);
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}
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inline void gpio_pad_dir_set(volatile uint64_t data)
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{
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GPIO->PAD_DIR_SET0 = (data & 0xffffffff);
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GPIO->PAD_DIR_SET1 = (data >> 32);
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}
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inline void gpio_pad_dir_reset(volatile uint64_t data)
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{
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GPIO->PAD_DIR_RESET0 = (data & 0xffffffff);
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GPIO->PAD_DIR_RESET1 = (data >> 32);
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}
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157
redbee-econotag/drivers/include/gpio.h
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157
redbee-econotag/drivers/include/gpio.h
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@ -0,0 +1,157 @@
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/*
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* gpio.h - GPIO driver for redbee
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* Copyright (C) 2013 Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*/
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#ifndef GPIO_H
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#define GPIO_H
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/* Structure-based GPIO access
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Example usage:
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GPIO->FUNC_SEL0 |= 0x00008000; // set a whole register
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GPIO->FUNC_SEL_08 = 2; // set just one pin
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#define MY_PIN GPIO_08
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GPIO->FUNC_SEL.MY_PIN = 2; // same, to allow #define for pin names
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GPIO->DATA.MY_PIN = 1;
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gpio_set(GPIO_08); // efficiently set or clear a single output bit
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gpio_reset(GPIO_08);
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*/
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// GPIO to Function Alias macros:
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#define ADC0 GPIO_30
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#define ADC1 GPIO_31
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#define ADC2 GPIO_32
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#define ADC3 GPIO_33
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#define ADC4 GPIO_34
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#define ADC5 GPIO_35
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#define ADC6 GPIO_36
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#define ADC7 GPIO_37
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#define TDO GPIO_49
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#define TDI GPIO_48
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#define TCK GPIO_47
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#define TMS GPIO_46
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#define U2RTS GPIO_21
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#define U2CTS GPIO_20
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#define U2RX GPIO_19
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#define U2TX GPIO_18
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#define U1RTS GPIO_17
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#define U1CTS GPIO_16
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#define U1RX GPIO_15
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#define U1TX GPIO_14
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#define SDA GPIO_13
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#define SCL GPIO_12
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#define TMR3 GPIO_11
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#define TMR2 GPIO_10
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#define TMR1 GPIO_09
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#define TMR0 GPIO_08
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#define SCK GPIO_07
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#define MOSI GPIO_06
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#define MISO GPIO_05
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#define SS GPIO_04
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#define BTCK GPIO_03
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#define FSYN GPIO_02
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#define SSIRX GPIO_01
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#define SSITX GPIO_00
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#define KBI7 GPIO_29
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#define KBI6 GPIO_28
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#define KBI5 GPIO_27
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#define KBI4 GPIO_26
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#define KBI3 GPIO_25
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#define KBI2 GPIO_24
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#define KBI1 GPIO_23
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#define KBI0 GPIO_22
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#define TXON GPIO_44
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#define RXON GPIO_45
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#define ANT1 GPIO_42
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#define ANT2 GPIO_43
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#define VREF2H GPIO_38
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#define VREF2L GPIO_39
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#define VREF1H GPIO_40
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#define VREF1L GPIO_41
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#define MDO0 GPIO_51
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#define MDO1 GPIO_52
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#define MDO2 GPIO_53
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#define MDO3 GPIO_54
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#define MDO4 GPIO_55
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#define MDO5 GPIO_56
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#define MDO6 GPIO_57
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#define MDO7 GPIO_58
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#define MSEO0 GPIO_59
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#define MSEO1 GPIO_60
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#define RDY GPIO_61
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#define EVTO GPIO_62
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#define MCKO GPIO_50
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#define EVTI GPIO_63
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#define _V(x,n,i) uint32_t x##_##i : n;
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#define _REP(x,n) \
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_V(x,n,00) _V(x,n,01) _V(x,n,02) _V(x,n,03) _V(x,n,04) _V(x,n,05) _V(x,n,06) _V(x,n,07) \
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_V(x,n,08) _V(x,n,09) _V(x,n,10) _V(x,n,11) _V(x,n,12) _V(x,n,13) _V(x,n,14) _V(x,n,15) \
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_V(x,n,16) _V(x,n,17) _V(x,n,18) _V(x,n,19) _V(x,n,20) _V(x,n,21) _V(x,n,22) _V(x,n,23) \
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_V(x,n,24) _V(x,n,25) _V(x,n,26) _V(x,n,27) _V(x,n,28) _V(x,n,29) _V(x,n,30) _V(x,n,31) \
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_V(x,n,32) _V(x,n,33) _V(x,n,34) _V(x,n,35) _V(x,n,36) _V(x,n,37) _V(x,n,38) _V(x,n,39) \
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_V(x,n,40) _V(x,n,41) _V(x,n,42) _V(x,n,43) _V(x,n,44) _V(x,n,45) _V(x,n,46) _V(x,n,47) \
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_V(x,n,48) _V(x,n,49) _V(x,n,50) _V(x,n,51) _V(x,n,52) _V(x,n,53) _V(x,n,54) _V(x,n,55) \
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_V(x,n,56) _V(x,n,57) _V(x,n,58) _V(x,n,59) _V(x,n,60) _V(x,n,61) _V(x,n,62) _V(x,n,63)
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struct GPIO_struct {
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#define _IO(x) \
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union { struct { uint32_t x##0; uint32_t x##1; }; \
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struct { _REP(x, 1) }; \
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struct GPIO_##x { _REP(GPIO, 1) } x; };
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#define _IO_2bit(x) \
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union { struct { uint32_t x##0; uint32_t x##1; uint32_t x##2; uint32_t x##3; }; \
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struct { _REP(x, 2) }; \
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struct GPIO_##x { _REP(GPIO, 2) } x; };
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_IO(PAD_DIR);
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_IO(DATA);
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_IO(PAD_PU_EN);
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_IO_2bit(FUNC_SEL);
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_IO(DATA_SEL);
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_IO(PAD_PU_SEL);
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_IO(PAD_HYST_EN);
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_IO(PAD_KEEP);
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_IO(DATA_SET);
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_IO(DATA_RESET);
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_IO(PAD_DIR_SET);
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_IO(PAD_DIR_RESET);
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};
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#undef _IO
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#undef _IO_2bit
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/* Build an enum lookup to map GPIO_08 -> 8 */
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#undef _V
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#define _V(x,n,i) __NUM_GPIO_GPIO_##i,
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enum { _REP(0,0) };
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/* Macros to set or reset a data pin in the fastest possible way */
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#define gpio_set(gpio_xx) __gpio_set(gpio_xx)
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#define __gpio_set(gpio_xx) \
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((__NUM_GPIO_##gpio_xx < 32) \
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? (GPIO->DATA_SET0 = (1 << (__NUM_GPIO_##gpio_xx - 0))) \
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: (GPIO->DATA_SET1 = (1 << (__NUM_GPIO_##gpio_xx - 32))))
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#define gpio_reset(gpio_xx) __gpio_reset(gpio_xx)
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#define __gpio_reset(gpio_xx) \
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((__NUM_GPIO_##gpio_xx < 32) \
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? (GPIO->DATA_RESET0 = (1 << (__NUM_GPIO_##gpio_xx - 0))) \
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: (GPIO->DATA_RESET1 = (1 << (__NUM_GPIO_##gpio_xx - 32))))
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#undef _REP
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#undef _V
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static volatile struct GPIO_struct * const GPIO = (void *) (0x80000000);
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#endif
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139
redbee-econotag/drivers/include/uart.h
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139
redbee-econotag/drivers/include/uart.h
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@ -0,0 +1,139 @@
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/*
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* uart.h - UART driver for redbee
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* Copyright (C) 2013 Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*/
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#ifndef UART_H
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#define UART_H
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/*-----------------------------------------------------------------*/
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/* UART */
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#define UART1_BASE (0x80005000)
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#define UART2_BASE (0x8000B000)
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struct UART_struct {
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union {
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uint32_t CON;
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struct UART_CON {
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uint32_t :16;
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uint32_t TST:1;
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uint32_t MRXR:1;
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uint32_t MTXR:1;
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uint32_t FCE:1;
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uint32_t FCP:1;
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uint32_t XTIM:1;
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uint32_t :2;
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uint32_t TXOENB:1;
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uint32_t CONTX:1;
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uint32_t SB:1;
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uint32_t ST2:1;
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uint32_t EP:1;
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uint32_t PEN:1;
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uint32_t RXE:1;
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uint32_t TXE:1;
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} CONbits;
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};
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union {
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uint32_t STAT;
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struct UART_STAT {
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uint32_t :24;
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uint32_t TXRDY:1;
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uint32_t RXRDY:1;
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uint32_t RUE:1;
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uint32_t ROE:1;
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uint32_t TOE:1;
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uint32_t FE:1;
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uint32_t PE:1;
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uint32_t SE:1;
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} USTATbits;
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};
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union {
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uint32_t DATA;
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struct UART_DATA {
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uint32_t :24;
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uint32_t DATA:8;
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} DATAbits;
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};
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union {
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uint32_t RXCON;
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struct UART_URXCON {
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uint32_t :26;
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uint32_t LVL:6;
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} RXCONbits;
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};
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union {
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uint32_t TXCON;
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struct UART_TXCON {
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uint32_t :26;
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uint32_t LVL:6;
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} TXCONbits;
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};
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union {
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uint32_t CTS;
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struct UART_CTS {
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uint32_t :27;
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uint32_t LVL:5;
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} CTSbits;
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};
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union {
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uint32_t BR;
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struct UART_BR {
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uint32_t INC:16;
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uint32_t MOD:16;
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} BRbits;
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};
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};
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static volatile struct UART_struct * const UART1 = (void *) (UART1_BASE);
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static volatile struct UART_struct * const UART2 = (void *) (UART2_BASE);
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void uart_init(volatile struct UART_struct * uart, uint32_t baud);
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void uart_set_baudrate(volatile struct UART_struct * uart, uint32_t baud);
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void uart_flow_ctl(volatile struct UART_struct * uart, uint8_t on);
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/* The mc1322x has a 32 byte hardware FIFO for transmitted characters.
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* Currently it is always filled from a larger RAM buffer. It would be
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* possible to eliminate that overhead by filling directly from a chain
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* of data buffer pointers, but printf's would be not so easy.
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*/
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#define UART1_TX_BUFFERSIZE 1024
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extern volatile uint32_t u1_tx_head, u1_tx_tail;
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void uart1_putc(char c);
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/* The mc1322x has a 32 byte hardware FIFO for received characters.
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* If a larger rx buffersize is specified the FIFO will be extended into RAM.
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* RAM transfers will occur on interrupt when the FIFO is nearly full.
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* If a smaller buffersize is specified hardware flow control will be
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* initiated at that FIFO level.
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* Set to 32 for no flow control or RAM buffer.
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*/
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#define UART1_RX_BUFFERSIZE 128
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#if UART1_RX_BUFFERSIZE > 32
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extern volatile uint32_t u1_rx_head, u1_rx_tail;
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#define uart1_can_get() ((u1_rx_head!=u1_rx_tail) || (*UART1_URXCON > 0))
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#else
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#define uart1_can_get() (*UART1_URXCON > 0)
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#endif
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uint8_t uart1_getc(void);
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#define UART2_TX_BUFFERSIZE 1024
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extern volatile uint32_t u2_tx_head, u2_tx_tail;
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void uart2_putc(char c);
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#define UART2_RX_BUFFERSIZE 128
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#if UART2_RX_BUFFERSIZE > 32
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extern volatile uint32_t u2_rx_head, u2_rx_tail;
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#define uart2_can_get() ((u2_rx_head!=u2_rx_tail) || (*UART2_URXCON > 0))
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#else
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#define uart2_can_get() (*UART2_URXCON > 0)
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#endif
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uint8_t uart2_getc(void);
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#endif
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171
redbee-econotag/drivers/redbee_uart.c
Normal file
171
redbee-econotag/drivers/redbee_uart.c
Normal file
@ -0,0 +1,171 @@
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/*
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* redbee_uart.c - UART driver for redbee
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* Copyright (C) 2013 Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*/
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#include "mc1322x.h"
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#include "uart.h"
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#include "gpio.h"
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#include "io.h"
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#define MOD_ 9999
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#define CLK_ 24000000
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#define DIV_ 16 /* uart->CON.XTIM = 0 is 16x oversample (datasheet is incorrect) */
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void uart_set_baudrate ( volatile struct UART_struct* uart, uint32_t baudrate ) {
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uint64_t inc = 0;
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/* calculate inc following equation 13-1 from datasheet */
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/* multiply by another 10 to get a fixed point*/
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inc = ((uint64_t) baudrate * DIV_ * MOD_ * 10 / CLK_) - 10;
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/* add 5 and div by 10 to get a rounding */
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inc = (inc + 5) / 10;
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/* disable UARTx to set baudrate */
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uart->CONbits.TXE = 0;
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uart->CONbits.RXE = 0;
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/* set baudrate */
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uart->BRbits.INC = inc;
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uart->BRbits.MOD = MOD_;
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/* reenable UARTx again */
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/* uart->CON.XTIM = 0 is 16x oversample (datasheet is incorrect) */
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uart->CONbits.XTIM = 0;
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uart->CONbits.TXE = 1;
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uart->CONbits.RXE = 1;
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}
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void uart_flow_ctl ( volatile struct UART_struct* uart, uint8_t on ) {
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if (on) {
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/* enable flow control */
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if (uart == UART1) {
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/* CTS and RTS directions */
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GPIO->PAD_DIR_SET.U1CTS = 1;
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GPIO->PAD_DIR_RESET.U1RTS = 1;
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/* function select to uart */
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GPIO->FUNC_SEL.U1CTS = 1;
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GPIO->FUNC_SEL.U1RTS = 1;
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}
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else {
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/* UART2 */
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/* CTS and RTS directions */
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GPIO->PAD_DIR_SET.U2CTS = 1;
|
||||
GPIO->PAD_DIR_RESET.U2RTS = 1;
|
||||
/* function select to uart */
|
||||
GPIO->FUNC_SEL.U2CTS = 1;
|
||||
GPIO->FUNC_SEL.U2RTS = 1;
|
||||
}
|
||||
/* enable flow control */
|
||||
uart->CONbits.FCE = 1;
|
||||
}
|
||||
else {
|
||||
/* disable flow control */
|
||||
uart->CONbits.FCE = 0;
|
||||
if (uart == UART1) {
|
||||
/* CTS and RTS directions */
|
||||
GPIO->PAD_DIR_RESET.U1CTS = 1;
|
||||
GPIO->PAD_DIR_RESET.U1RTS = 1;
|
||||
/* function select to GPIO */
|
||||
GPIO->FUNC_SEL.U1CTS = 3;
|
||||
GPIO->FUNC_SEL.U1RTS = 3;
|
||||
}
|
||||
else {
|
||||
/* CTS and RTS directions */
|
||||
GPIO->PAD_DIR_RESET.U2CTS = 1;
|
||||
GPIO->PAD_DIR_RESET.U2RTS = 1;
|
||||
/* function select to GPIO */
|
||||
GPIO->FUNC_SEL.U2CTS = 3;
|
||||
GPIO->FUNC_SEL.U2RTS = 3;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void uart_init ( volatile struct UART_struct* uart, uint32_t baudrate ) {
|
||||
/* enable the uart so we can set the gpio mode */
|
||||
/* has to be enabled before setting the function with GPIO->FUNC_SEL */
|
||||
uart->CONbits.TXE = 1;
|
||||
uart->CONbits.RXE = 1;
|
||||
|
||||
/* interrupt when this or more bytes are free in the tx buffer */
|
||||
uart->TXCON = 16;
|
||||
|
||||
if (uart == UART1) {
|
||||
/* TX and RX direction */
|
||||
GPIO->PAD_DIR_SET.U1TX = 1;
|
||||
GPIO->PAD_DIR_RESET.U1RX = 1;
|
||||
|
||||
/* set function selection to UART */
|
||||
GPIO->FUNC_SEL.U1TX = 1;
|
||||
GPIO->FUNC_SEL.U1RX = 1;
|
||||
|
||||
UART1->CONbits.TXE = 1; /*< enable transmit */
|
||||
UART1->CONbits.RXE = 1; /*< enable receive */
|
||||
#if UART1_RX_BUFFERSIZE > 32
|
||||
UART1->RXCONbits.LVL = 30; /*< interrupt when fifo is nearly full */
|
||||
u1_rx_head = 0;
|
||||
u1_rx_tail = 0;
|
||||
#elif UART1_RX_BUFFERSIZE < 32
|
||||
UART1->CONbits.FCE = 1; /*< enable flowcontrol */
|
||||
UART1->CONbits.MRXR = 1; /*< disable Rx interrupt */
|
||||
UART1->CTSbits.LVL = UART1_RX_BUFFERSIZE; /*< drop cts when tx buffer at trigger level */
|
||||
GPIO->FUNC_SEL1.U1CTS = 1; /*< set GPIO 16 to UART1 CTS */
|
||||
GPIO->FUNC_SEL1.U1RTS = 1; /*< set GPIO 17 to UART1 RTS */
|
||||
#else
|
||||
UART1->CONbits.MRXR = 1; /*< disable rx interrupt */
|
||||
#endif
|
||||
|
||||
u1_tx_head = 0;
|
||||
u1_tx_tail = 0;
|
||||
|
||||
enable_irq(UART1);
|
||||
}
|
||||
else {
|
||||
/* UART2 */
|
||||
/* TX and RX direction */
|
||||
GPIO->PAD_DIR_SET.U2TX = 1;
|
||||
GPIO->PAD_DIR_RESET.U2RX = 1;
|
||||
|
||||
/* set function selection to UART */
|
||||
GPIO->FUNC_SEL.U2TX = 1;
|
||||
GPIO->FUNC_SEL.U2RX = 1;
|
||||
|
||||
UART2->CONbits.TXE = 1; /*< enable transmit */
|
||||
UART2->CONbits.RXE = 1; /*< enable receive */
|
||||
#if UART2_RX_BUFFERSIZE > 32
|
||||
UART2->RXCONbits.LVL = 30; /*< interrupt when fifo is nearly full */
|
||||
u2_rx_head = 0;
|
||||
u2_rx_tail = 0;
|
||||
#elif UART2_RX_BUFFERSIZE < 32
|
||||
UART2->CONbits.FCE = 1; /*< enable flowcontrol */
|
||||
UART2->CONbits.MRXR = 1; /*< disable Rx interrupt */
|
||||
UART2->CTSbits.LVL = UART2_RX_BUFFERSIZE; /*< drop cts when tx buffer at trigger level */
|
||||
GPIO->FUNC_SEL1.U1CTS = 1; /*< set GPIO 16 to UART2 CTS */
|
||||
GPIO->FUNC_SEL1.U1RTS = 1; /*< set GPIO 17 to UART2 RTS */
|
||||
#else
|
||||
UART2->CONbits.MRXR = 1; /*< disable rx interrupt */
|
||||
#endif
|
||||
|
||||
u2_tx_head = 0;
|
||||
u2_tx_tail = 0;
|
||||
|
||||
enable_irq(UART2);
|
||||
}
|
||||
|
||||
uart_set_baudrate( uart, baudrate );
|
||||
}
|
||||
|
||||
int fw_puts(char *astring,int length)
|
||||
{
|
||||
int i = 0;
|
||||
for (; i<length; i++) {
|
||||
uart1_putc( astring[i] );
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
@ -1,6 +1,7 @@
|
||||
/*
|
||||
* redbee_uart1.c - UART1 driver for redbee
|
||||
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
|
||||
* 2013 Thomas Eichinger <thomas.eichinger@fu-berlin.de>
|
||||
*
|
||||
* This source code is licensed under the GNU General Public License,
|
||||
* Version 3. See the file LICENSE for more details.
|
||||
@ -9,35 +10,145 @@
|
||||
*/
|
||||
|
||||
#include "mc1322x.h"
|
||||
#include "uart.h"
|
||||
|
||||
static volatile unsigned int running = 0;
|
||||
static volatile unsigned int fifo = 0;
|
||||
volatile uint8_t u1_tx_buf[UART1_TX_BUFFERSIZE];
|
||||
volatile uint32_t u1_tx_head, u1_tx_tail;
|
||||
|
||||
static inline int uart0_puts(char *astring, int length)
|
||||
{
|
||||
int i;
|
||||
for (i=0;i<length;i++) {
|
||||
/* TODO: Fix me */
|
||||
while(UART1->TXCON != 0);
|
||||
UART1->DATA = astring[i];
|
||||
#if UART1_RX_BUFFERSIZE > 32
|
||||
volatile uint8_t u1_rx_buf[UART1_RX_BUFFERSIZE];
|
||||
volatile uint32_t u1_rx_head, u1_rx_tail;
|
||||
#endif
|
||||
|
||||
void uart1_isr ( void ) {
|
||||
#if UART1_RX_BUFFERSIZE > 32
|
||||
/* receive interrupt */
|
||||
if ( UART1->USTATbits.RXRDY == 1) {
|
||||
/* copy fifo into SW buffer */
|
||||
while (UART1->RXCON != 0) {
|
||||
uint32_t u1_rx_tail_next;
|
||||
u1_rx_tail_next = u1_rx_tail + 1;
|
||||
if ( u1_rx_tail_next >= sizeof(u1_rx_buf) ) {
|
||||
u1_rx_tail_next = 0;
|
||||
}
|
||||
if ( u1_rx_head != u1_rx_tail_next ) {
|
||||
u1_rx_buf[u1_rx_tail] = UART1->DATA;
|
||||
u1_rx_tail = u1_rx_tail_next;
|
||||
}
|
||||
/* buffer full, flush fifo */
|
||||
else {
|
||||
while ( UART1->RXCON != 0 ) {
|
||||
UART1->DATA;
|
||||
}
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
while ( UART1->TXCON != 0 ) {
|
||||
if ( u1_tx_head == u1_tx_tail ) {
|
||||
#if UART1_RX_BUFFERSIZE > 32
|
||||
UART1->CONbits.MTXR = 1;
|
||||
#else
|
||||
disable_irq(UART1);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
UART1->DATA = u1_tx_buf[u1_tx_tail++];
|
||||
if ( u1_tx_tail >= sizeof(u1_tx_buf) ) {
|
||||
u1_tx_tail = 0;
|
||||
}
|
||||
}
|
||||
return length;
|
||||
}
|
||||
|
||||
int fw_puts(char *astring, int length)
|
||||
{
|
||||
return uart0_puts(astring, length);
|
||||
}
|
||||
|
||||
void stdio_flush(void)
|
||||
{
|
||||
/* disable TX interrupt */
|
||||
void uart1_putc ( uint8_t c ) {
|
||||
/* disable UART1_IRQ since it modifies u1_tx_(head|tail) */
|
||||
#if UART1_RX_BUFFERSIZE > 32
|
||||
UART1->CONbits.MTXR = 1;
|
||||
while(running) {
|
||||
while(UART1->TXCON != 0);
|
||||
fifo=0;
|
||||
push_queue(); // dequeue to fifo
|
||||
#else
|
||||
disable_irq(UART1);
|
||||
#endif
|
||||
if ( (u1_tx_head == u1_tx_tail) && (UART1->TXCON != 0) ) {
|
||||
UART1->DATA = c;
|
||||
}
|
||||
/* enable TX interrupt */
|
||||
else {
|
||||
u1_tx_buf[u1_tx_head++] = c;
|
||||
if ( u1_tx_head >= sizeof(u1_tx_buf) ) {
|
||||
u1_tx_head = 0;
|
||||
}
|
||||
if ( u1_tx_head == u1_tx_tail ) {
|
||||
uint32_t u1_tx_tail_save = u1_tx_tail;
|
||||
/* back up head to show buffer not empty and enable tx interrupt */
|
||||
u1_tx_head--;
|
||||
#if UART1_RX_BUFFERSIZE > 32
|
||||
UART1->CONbits.MTXR = 0;
|
||||
#else
|
||||
enable_irq(UART1);
|
||||
#endif
|
||||
/* tail will change after one char goes out */
|
||||
while ( u1_tx_tail_save == u1_tx_tail ) {
|
||||
/* wait */
|
||||
}
|
||||
/* restor head */
|
||||
u1_tx_head++;
|
||||
return;
|
||||
}
|
||||
}
|
||||
#if UART1_RX_BUFFERSIZE > 32
|
||||
UART1->CONbits.MTXR = 0;
|
||||
#else
|
||||
enable_irq(UART1);
|
||||
#endif
|
||||
}
|
||||
|
||||
uint8_t uart1_getc ( void ) {
|
||||
#if UART1_RX_BUFFERSIZE > 32
|
||||
/* pull from ram buffer */
|
||||
uint8_t c = 0;
|
||||
if ( u1_rx_head != u1_rx_tail ) {
|
||||
c = u1_rx_buf[u1_rx_head++];
|
||||
if ( u1_rx_head >= sizeof(u1_rx_buf) ) {
|
||||
u1_rx_head = 0;
|
||||
}
|
||||
return c;
|
||||
}
|
||||
#endif
|
||||
/* pull from hw fifo */
|
||||
while ( uart1_can_get() == 0 ) {
|
||||
/* wait */
|
||||
}
|
||||
return UART1->DATA;
|
||||
}
|
||||
|
||||
// static volatile unsigned int running = 0;
|
||||
// static volatile unsigned int fifo = 0;
|
||||
//
|
||||
// static inline int uart0_puts(char *astring, int length)
|
||||
// {
|
||||
// int i;
|
||||
// for (i=0;i<length;i++) {
|
||||
// /* TODO: Fix me */
|
||||
// while(UART1->TXCON != 0);
|
||||
// UART1->DATA = astring[i];
|
||||
// }
|
||||
// return length;
|
||||
// }
|
||||
//
|
||||
// int fw_puts(char *astring, int length)
|
||||
// {
|
||||
// return uart0_puts(astring, length);
|
||||
// }
|
||||
//
|
||||
// void stdio_flush(void)
|
||||
// {
|
||||
// /* disable TX interrupt */
|
||||
// UART1->CONbits.MTXR = 1;
|
||||
// while(running) {
|
||||
// while(UART1->TXCON != 0);
|
||||
// fifo=0;
|
||||
// push_queue(); // dequeue to fifo
|
||||
// }
|
||||
// /* enable TX interrupt */
|
||||
// UART1->CONbits.MTXR = 0;
|
||||
// }
|
||||
|
||||
121
redbee-econotag/drivers/redbee_uart2.c
Normal file
121
redbee-econotag/drivers/redbee_uart2.c
Normal file
@ -0,0 +1,121 @@
|
||||
/*
|
||||
* redbee_uart2.c - UART2 driver for redbee
|
||||
* Copyright (C) 2013 Thomas Eichinger <thomas.eichinger@fu-berlin.de>
|
||||
*
|
||||
* This source code is licensed under the GNU General Public License,
|
||||
* Version 3. See the file LICENSE for more details.
|
||||
*
|
||||
* This file is part of RIOT.
|
||||
*/
|
||||
|
||||
#include "mc1322x.h"
|
||||
#include "uart.h"
|
||||
|
||||
volatile uint8_t u2_tx_buf[UART2_TX_BUFFERSIZE];
|
||||
volatile uint32_t u2_tx_head, u2_tx_tail;
|
||||
|
||||
#if UART2_RX_BUFFERSIZE > 32
|
||||
volatile uint8_t u2_rx_buf[UART2_RX_BUFFERSIZE];
|
||||
volatile uint32_t u2_rx_head, u2_rx_tail;
|
||||
#endif
|
||||
|
||||
void uart2_isr ( void ) {
|
||||
#if UART2_RX_BUFFERSIZE > 32
|
||||
/* receive interrupt */
|
||||
if ( UART2->USTATbits.RXRDY == 1) {
|
||||
/* copy fifo into SW buffer */
|
||||
while (UART2->RXCON != 0) {
|
||||
uint32_t u2_rx_tail_next;
|
||||
u2_rx_tail_next = u2_rx_tail + 1;
|
||||
if ( u2_rx_tail_next >= sizeof(u2_rx_buf) ) {
|
||||
u2_rx_tail_next = 0;
|
||||
}
|
||||
if ( u2_rx_head != u2_rx_tail_next ) {
|
||||
u2_rx_buf[u2_rx_tail] = UART2->DATA;
|
||||
u2_rx_tail = u2_rx_tail_next;
|
||||
}
|
||||
/* buffer full, flush fifo */
|
||||
else {
|
||||
while ( UART2->RXCON != 0 ) {
|
||||
UART2->DATA;
|
||||
}
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
while ( UART2->TXCON != 0 ) {
|
||||
if ( u2_tx_head == u2_tx_tail ) {
|
||||
#if UART2_RX_BUFFERSIZE > 32
|
||||
UART2->CONbits.MTXR = 1;
|
||||
#else
|
||||
disable_irq(UART2);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
UART2->DATA = u2_tx_buf[u2_tx_tail++];
|
||||
if ( u2_tx_tail >= sizeof(u2_tx_buf) ) {
|
||||
u2_tx_tail = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void uart2_putc ( uint8_t c ) {
|
||||
/* disable UART2_IRQ since it modifies u2_tx_(head|tail) */
|
||||
#if UART2_RX_BUFFERSIZE > 32
|
||||
UART2->CONbits.MTXR = 1;
|
||||
#else
|
||||
disable_irq(UART2);
|
||||
#endif
|
||||
if ( (u2_tx_head == u2_tx_tail) && (UART2->TXCON != 0) ) {
|
||||
UART2->DATA = c;
|
||||
}
|
||||
else {
|
||||
u2_tx_buf[u2_tx_head++] = c;
|
||||
if ( u2_tx_head >= sizeof(u2_tx_buf) ) {
|
||||
u2_tx_head = 0;
|
||||
}
|
||||
if ( u2_tx_head == u2_tx_tail ) {
|
||||
uint32_t u2_tx_tail_save = u2_tx_tail;
|
||||
/* back up head to show buffer not empty and enable tx interrupt */
|
||||
u2_tx_head--;
|
||||
#if UART2_RX_BUFFERSIZE > 32
|
||||
UART2->CONbits.MTXR = 0;
|
||||
#else
|
||||
enable_irq(UART2);
|
||||
#endif
|
||||
/* tail will change after one char goes out */
|
||||
while ( u2_tx_tail_save == u2_tx_tail ) {
|
||||
/* wait */
|
||||
}
|
||||
/* restor head */
|
||||
u2_tx_head++;
|
||||
return;
|
||||
}
|
||||
}
|
||||
#if UART2_RX_BUFFERSIZE > 32
|
||||
UART2->CONbits.MTXR = 0;
|
||||
#else
|
||||
enable_irq(UART2);
|
||||
#endif
|
||||
}
|
||||
|
||||
uint8_t uart2_getc ( void ) {
|
||||
#if UART2_RX_BUFFERSIZE > 32
|
||||
/* pull from ram buffer */
|
||||
uint8_t c = 0;
|
||||
if ( u2_rx_head != u2_rx_tail ) {
|
||||
c = u2_rx_buf[u2_rx_head++];
|
||||
if ( u2_rx_head >= sizeof(u2_rx_buf) ) {
|
||||
u2_rx_head = 0;
|
||||
}
|
||||
return c;
|
||||
}
|
||||
#endif
|
||||
/* pull from hw fifo */
|
||||
while ( uart2_can_get() == 0 ) {
|
||||
/* wait */
|
||||
}
|
||||
return UART2->DATA;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user