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cortexm_common: Remove read in ICSR register operations

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All bits in the ICSR register in the cortexm system control block are
either read-only or don't have an effect when writing a zero. A
read-modify-write cycle is thus not required when writing bit flags in
the register. This commit removes the reads in the read-modify-store
patterns for this register.
This commit is contained in:
Koen Zandberg 2020-06-23 11:53:53 +02:00
parent ae95e33308
commit d7c1510b0f
No known key found for this signature in database
GPG Key ID: 0895A893E6D2985B
1 changed files with 3 additions and 3 deletions
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6
cpu/cortexm_common/thread_arch.c
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@ -280,7 +280,7 @@ void thread_yield_higher(void)
{ {
/* trigger the PENDSV interrupt to run scheduler and schedule new thread if /* trigger the PENDSV interrupt to run scheduler and schedule new thread if
* applicable */ * applicable */
SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
} }
void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) { void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
@ -432,7 +432,7 @@ static void __attribute__((used)) _svc_dispatch(unsigned int *svc_args)
switch (svc_number) { switch (svc_number) {
case 1: /* SVC number used by cpu_switch_context_exit */ case 1: /* SVC number used by cpu_switch_context_exit */
SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
break; break;
default: default:
DEBUG("svc: unhandled SVC #%u\n", svc_number); DEBUG("svc: unhandled SVC #%u\n", svc_number);
@ -443,6 +443,6 @@ static void __attribute__((used)) _svc_dispatch(unsigned int *svc_args)
#else /* MODULE_CORTEXM_SVC */ #else /* MODULE_CORTEXM_SVC */
void __attribute__((used)) isr_svc(void) void __attribute__((used)) isr_svc(void)
{ {
SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
} }
#endif /* MODULE_CORTEXM_SVC */ #endif /* MODULE_CORTEXM_SVC */