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Merge pull request #15000 from aabadie/pr/boards/stm32l0l1_clock_kconfig_only

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boards/stm32l0l1: model clock configuration in kconfig
This commit is contained in:
Alexandre Abadie 2020-11-03 17:20:00 +01:00 committed by GitHub
commit daa7ed54cd
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12 changed files with 143 additions and 5 deletions
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5
boards/b-l072z-lrwan1/Kconfig
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@ -28,3 +28,8 @@ config BOARD_B_L072Z_LRWAN1
# The 0.10.0 openocd version in Ubuntu Bionic doesn't work. The change was
# introduced after Jun 8, 2017 - v0.10.0-1-20170607-2132-dev.
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

5
boards/i-nucleo-lrwan1/Kconfig
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@ -22,3 +22,8 @@ config BOARD_I_NUCLEO_LRWAN1
select HAS_PERIPH_SPI_GPIO_MODE
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

5
boards/im880b/Kconfig
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@ -20,3 +20,8 @@ config BOARD_IM880B
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

2
boards/limifrog-v1/Kconfig
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@ -18,3 +18,5 @@ config BOARD_LIMIFROG_V1
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
source "$(RIOTBOARD)/common/stm32/Kconfig"

5
boards/lobaro-lorabox/Kconfig
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@ -20,3 +20,8 @@ config BOARD_LOBARO_LORABOX
select HAS_PERIPH_SPI_GPIO_MODE
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

5
boards/lsn50/Kconfig
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@ -28,3 +28,8 @@ config BOARD_LSN50
# The 0.10.0 openocd version in Ubuntu Bionic doesn't work. The change was
# introduced after Jun 8, 2017 - v0.10.0-1-20170607-2132-dev.
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

3
boards/nucleo-l031k6/Kconfig
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@ -24,4 +24,7 @@ config BOARD_NUCLEO_L031K6
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo32/Kconfig"

3
boards/nucleo-l053r8/Kconfig
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@ -22,4 +22,7 @@ config BOARD_NUCLEO_L053R8
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

3
boards/nucleo-l073rz/Kconfig
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@ -32,4 +32,7 @@ config BOARD_NUCLEO_L073RZ
# introduced after Jun 8, 2017 - v0.10.0-1-20170607-2132-dev.
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

2
boards/nz32-sc151/Kconfig
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@ -23,3 +23,5 @@ config BOARD_NZ32_SC151
select HAS_PERIPH_SPI_GPIO_MODE
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
source "$(RIOTBOARD)/common/stm32/Kconfig"

2
boards/stm32l0538-disco/Kconfig
View File

@ -18,3 +18,5 @@ config BOARD_STM32L0538_DISCO
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
source "$(RIOTBOARD)/common/stm32/Kconfig"

108
cpu/stm32/kconfigs/Kconfig.clk
View File

@ -6,7 +6,7 @@
#
menu "STM32 clock configuration"
depends on CPU_FAM_G0 || CPU_FAM_G4
depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1
choice
bool "Clock source selection"
@ -15,6 +15,10 @@ default USE_CLOCK_PLL
config USE_CLOCK_PLL
bool "PLL"
config USE_CLOCK_MSI
bool "Use direct multi-speed frequency internal oscillator (MSI)"
depends on CPU_FAM_L0 || CPU_FAM_L1
config USE_CLOCK_HSE
bool "Direct High frequency external oscillator (HSE)"
depends on BOARD_HAS_HSE
@ -24,6 +28,7 @@ config USE_CLOCK_HSI
endchoice
if CPU_FAM_G0 || CPU_FAM_G4
config CLOCK_PLL_M
int "M: PLLIN division factor" if USE_CLOCK_PLL
default 1 if CPU_FAM_G0
@ -45,7 +50,7 @@ config CLOCK_PLL_R
default 6 if BOARD_HAS_HSE
default 5
range 2 8
endif
endif # CPU_FAM_G0
if CPU_FAM_G4
choice
@ -72,7 +77,7 @@ config CLOCK_PLL_R
default 4 if PLL_R_DIV_4
default 6 if PLL_R_DIV_6
default 8 if PLL_R_DIV_8
endif
endif # CPU_FAM_G4
if CPU_FAM_G0
choice
@ -115,7 +120,99 @@ config CLOCK_HSISYS_DIV
default 32 if CLOCK_HSISYS_DIV_32
default 64 if CLOCK_HSISYS_DIV_64
default 128 if CLOCK_HSISYS_DIV_128
endif
endif # CPU_FAM_G0
endif # CPU_FAM_G0 || CPU_FAM_G4
if CPU_FAM_L0 || CPU_FAM_L1
config CLOCK_PLL_DIV
int "Main PLL division factor" if USE_CLOCK_PLL
default 2
range 2 4
choice
bool "Main PLL multiply factor" if USE_CLOCK_PLL
default PLL_MUL_4
config PLL_MUL_3
bool "Multiply by 3"
config PLL_MUL_4
bool "Multiply by 4"
config PLL_MUL_6
bool "Multiply by 6"
config PLL_MUL_8
bool "Multiply by 8"
config PLL_MUL_12
bool "Multiply by 12"
config PLL_MUL_16
bool "Multiply by 16"
config PLL_MUL_24
bool "Multiply by 24"
config PLL_MUL_32
bool "Multiply by 32"
config PLL_MUL_48
bool "Multiply by 48"
endchoice
config CLOCK_PLL_MUL
int
default 3 if PLL_MUL_3
default 4 if PLL_MUL_4
default 6 if PLL_MUL_6
default 8 if PLL_MUL_8
default 12 if PLL_MUL_12
default 16 if PLL_MUL_16
default 24 if PLL_MUL_24
default 32 if PLL_MUL_32
default 48 if PLL_MUL_48
choice
bool "Desired MSI clock frequency" if USE_CLOCK_MSI
default CLOCK_MSI_4MHZ
config CLOCK_MSI_65KHZ
bool "65.536kHz"
config CLOCK_MSI_130KHZ
bool "131.072kHz"
config CLOCK_MSI_260KHZ
bool "262.144kHz"
config CLOCK_MSI_520KHZ
bool "524.288kHz"
config CLOCK_MSI_1MHZ
bool "1.048MHz"
config CLOCK_MSI_2MHZ
bool "2.097MHz"
config CLOCK_MSI_4MHZ
bool "4.194MHz"
endchoice
config CLOCK_MSI
int
default 65536 if CLOCK_MSI_65KHZ
default 131072 if CLOCK_MSI_130KHZ
default 262144 if CLOCK_MSI_260KHZ
default 524288 if CLOCK_MSI_520KHZ
default 1048000 if CLOCK_MSI_1MHZ
default 2097000 if CLOCK_MSI_2MHZ
default 4194000 if CLOCK_MSI_4MHZ
endif # CPU_FAM_L0 || CPU_FAM_L1
choice
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
@ -147,7 +244,8 @@ config CLOCK_APB1_DIV
default 16 if CLOCK_APB1_DIV_16
choice
bool "APB2 prescaler (division factor of HCLK to produce PCLK2)" if CPU_FAM_G4
bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
depends on CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1
default CLOCK_APB2_DIV_1
config CLOCK_APB2_DIV_1