diff --git a/cpu/esp32/include/cpu_conf.h b/cpu/esp32/include/cpu_conf.h index b9f2a35788..6268a01a4f 100644 --- a/cpu/esp32/include/cpu_conf.h +++ b/cpu/esp32/include/cpu_conf.h @@ -65,6 +65,8 @@ #include "cpu_conf_esp32.h" #elif defined(CPU_FAM_ESP32C3) #include "cpu_conf_esp32c3.h" +#elif defined(CPU_FAM_ESP32S2) +#include "cpu_conf_esp32s2.h" #elif defined(CPU_FAM_ESP32S3) #include "cpu_conf_esp32s3.h" #else diff --git a/cpu/esp32/include/cpu_conf_esp32s2.h b/cpu/esp32/include/cpu_conf_esp32s2.h new file mode 100644 index 0000000000..57e8614ad8 --- /dev/null +++ b/cpu/esp32/include/cpu_conf_esp32s2.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_esp32 + * @ingroup config + * @brief Compile-time configuration macros for ESP32-S2 SoCs + * @{ + * + * @file + * @brief ESP32-S2 specific compile-time configuration + * + * @author Gunar Schorcht + */ + +#ifndef CPU_CONF_ESP32S2_H +#define CPU_CONF_ESP32S2_H + +#ifndef ESP_ISR_STACKSIZE +/** Stack size used in interrupt context */ +#define ESP_ISR_STACKSIZE (THREAD_STACKSIZE_DEFAULT) +#endif /* ESP_ISR_STACKSIZE */ + +/** Number of DRAM sections that can be used as heap. */ +#define NUM_HEAPS (1) + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* CPU_CONF_ESP32S2_H */ +/** @} */ diff --git a/cpu/esp32/include/periph_cpu.h b/cpu/esp32/include/periph_cpu.h index 66acd048b0..bb6edecd0c 100644 --- a/cpu/esp32/include/periph_cpu.h +++ b/cpu/esp32/include/periph_cpu.h @@ -561,7 +561,7 @@ typedef struct { * That is, if SPI_DEV(1) is used by defining the `SPI1_*` symbols, * SPI_DEV(0) must also be used by defining the `SPI0_*` symbols. * - The order in which the available interfaces `SPI2_HOST` (alias `HSPI` or - * `FSP`) and `SPI3_HOST` (alias `HSPI`) are assigned doesn't matter. + * `FSPI`) and `SPI3_HOST` (alias `VPSI` or `HSPI`) are assigned doesn't matter. * - The GPIOs listed in the configuration are only initialized as SPI * signals when the `periph_spi` module is used. Otherwise they are not * allocated and can be used for other purposes. @@ -599,9 +599,15 @@ typedef spi_host_device_t spi_ctrl_t; * sheets. These alias names have been declared obsolete in ESP-IDF. For * source code compatibility reasons these alias names are defined here. */ +#if defined(CPU_FAM_ESP32) #define HSPI SPI2_HOST /**< Alias name for SPI2_HOST as used in former ESP-IDF versions */ -#define FSPI SPI2_HOST /**< Alias name for SPI2_HOST as used in former ESP-IDF versions */ #define VSPI SPI3_HOST /**< Alias name for SPI3_HOST as used in former ESP-IDF versions */ +#elif defined(CPU_FAM_ESP32S2) +#define FSPI SPI2_HOST /**< Alias name for SPI2_HOST as used in former ESP-IDF versions */ +#define HSPI SPI3_HOST /**< Alias name for SPI3_HOST as used in former ESP-IDF versions */ +#else +#define FSPI SPI2_HOST /**< Alias name for SPI2_HOST as used in former ESP-IDF versions */ +#endif /** * @brief SPI configuration structure type @@ -741,6 +747,8 @@ typedef struct { #include "periph_cpu_esp32.h" #elif defined(CPU_FAM_ESP32C3) #include "periph_cpu_esp32c3.h" +#elif defined(CPU_FAM_ESP32S2) +#include "periph_cpu_esp32s2.h" #elif defined(CPU_FAM_ESP32S3) #include "periph_cpu_esp32s3.h" #else diff --git a/cpu/esp32/include/periph_cpu_esp32s2.h b/cpu/esp32/include/periph_cpu_esp32s2.h new file mode 100644 index 0000000000..74ffd6ed00 --- /dev/null +++ b/cpu/esp32/include/periph_cpu_esp32s2.h @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_esp32 + * @{ + * + * @file + * @brief ESP32-S2 specific peripheral configuration + * + * @author Gunar Schorcht + */ + +#ifndef PERIPH_CPU_ESP32S2_H +#define PERIPH_CPU_ESP32S2_H + +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Mapping configured ESP32-S2 default clock to CLOCK_CORECLOCK define */ +#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ) + +/** + * @name Predefined GPIO names + * @{ + */ +#define GPIO0 (GPIO_PIN(PORT_GPIO, 0)) +#define GPIO1 (GPIO_PIN(PORT_GPIO, 1)) +#define GPIO2 (GPIO_PIN(PORT_GPIO, 2)) +#define GPIO3 (GPIO_PIN(PORT_GPIO, 3)) +#define GPIO4 (GPIO_PIN(PORT_GPIO, 4)) +#define GPIO5 (GPIO_PIN(PORT_GPIO, 5)) +#define GPIO6 (GPIO_PIN(PORT_GPIO, 6)) +#define GPIO7 (GPIO_PIN(PORT_GPIO, 7)) +#define GPIO8 (GPIO_PIN(PORT_GPIO, 8)) +#define GPIO9 (GPIO_PIN(PORT_GPIO, 9)) +#define GPIO10 (GPIO_PIN(PORT_GPIO, 10)) +#define GPIO11 (GPIO_PIN(PORT_GPIO, 11)) +#define GPIO12 (GPIO_PIN(PORT_GPIO, 12)) +#define GPIO13 (GPIO_PIN(PORT_GPIO, 13)) +#define GPIO14 (GPIO_PIN(PORT_GPIO, 14)) +#define GPIO15 (GPIO_PIN(PORT_GPIO, 15)) +#define GPIO16 (GPIO_PIN(PORT_GPIO, 16)) +#define GPIO17 (GPIO_PIN(PORT_GPIO, 17)) +#define GPIO18 (GPIO_PIN(PORT_GPIO, 18)) +#define GPIO19 (GPIO_PIN(PORT_GPIO, 19)) +#define GPIO20 (GPIO_PIN(PORT_GPIO, 20)) +#define GPIO21 (GPIO_PIN(PORT_GPIO, 21)) +/* GPIOs 22 ...25 are not available */ +#define GPIO26 (GPIO_PIN(PORT_GPIO, 26)) +#define GPIO27 (GPIO_PIN(PORT_GPIO, 27)) +#define GPIO28 (GPIO_PIN(PORT_GPIO, 28)) +#define GPIO29 (GPIO_PIN(PORT_GPIO, 29)) +#define GPIO30 (GPIO_PIN(PORT_GPIO, 30)) +#define GPIO31 (GPIO_PIN(PORT_GPIO, 31)) +#define GPIO32 (GPIO_PIN(PORT_GPIO, 32)) +#define GPIO33 (GPIO_PIN(PORT_GPIO, 33)) +#define GPIO34 (GPIO_PIN(PORT_GPIO, 34)) +#define GPIO35 (GPIO_PIN(PORT_GPIO, 35)) +#define GPIO36 (GPIO_PIN(PORT_GPIO, 36)) +#define GPIO37 (GPIO_PIN(PORT_GPIO, 37)) +#define GPIO38 (GPIO_PIN(PORT_GPIO, 38)) +#define GPIO39 (GPIO_PIN(PORT_GPIO, 39)) +#define GPIO40 (GPIO_PIN(PORT_GPIO, 40)) +#define GPIO41 (GPIO_PIN(PORT_GPIO, 41)) +#define GPIO42 (GPIO_PIN(PORT_GPIO, 42)) +#define GPIO43 (GPIO_PIN(PORT_GPIO, 43)) +#define GPIO44 (GPIO_PIN(PORT_GPIO, 44)) +#define GPIO45 (GPIO_PIN(PORT_GPIO, 45)) +#define GPIO46 (GPIO_PIN(PORT_GPIO, 46)) +/** @} */ + +/** + * @name ADC configuration + * + * ESP32-S2 integrates two 13-bit ADCs (ADC1 and ADC2) with 20 channels in + * total: + * + * - **ADC1** supports 10 channels: GPIO1 ... GPIO10 + * - **ADC2** supports 10 channels: GPIO11 ... GPIO20 + * + * @note + * - ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are + * therefore not available as ADC channels if the modules `esp_wifi` or + * `esp_now` are used. + * - Vref can be read with function #adc_line_vref_to_gpio at an ADC2 channel, + * that is at GPIO11 ... GPIO20. + * - GPIO3 is a strapping pin und shouldn't be used as ADC channel + */ + +/** + * @name I2C configuration + * + * ESP32-S2 has two built-in I2C interfaces. + * + * The following table shows the default configuration of I2C interfaces + * used for ESP32-S2 boards. It can be overridden by + * [application-specific configurations](#esp32_application_specific_configurations). + * + *
+ * + * Device | Signal | Pin | Symbol | Remarks + * :----------|:-------|:-------|:--------------|:---------------- + * I2C_DEV(0) | | | `#I2C0_SPEED` | default is `I2C_SPEED_FAST` + * I2C_DEV(0) | SCL | GPIO9 | `#I2C0_SCL` | - + * I2C_DEV(0) | SDA | GPIO8 | `#I2C0_SDA` | - + * + *

+ */ + +/** + * @name PWM configuration + * + * The ESP32-S2 LEDC module has 1 channel group with 8 channels. Each of + * these channels can be clocked by one of the 4 timers. + */ + +/** + * @name SPI configuration + * + * ESP32-S2 has four SPI controllers where SPI0 and SPI1 share the same bus + * and can only operate in memory mode while SPI2 and SPI3 can be used as general + * purpose SPI: + * + * - controller SPI0 is reserved for external memories like Flash and PSRAM + * - controller SPI1 is reserved for external memories like Flash and PSRAM + * - controller SPI2 can be used for peripherals (also called FSPI) + * - controller SPI3 can be used for peripherals + * + * Thus, SPI2 (`FSPI`) and SPI3 can be used as general purpose SPI in + * RIOT as SPI_DEV(0) and SPI_DEV(1) by defining the symbols `SPI0_*` + * and `SPI1_*`. + * + * The following table shows the pin configuration used by default, even + * though it **can vary** from board to board. + * + *
+ * + * Device (Alias) | Signal | Pin | Symbol | Remarks + * :-----------------------|:------:|:-------|:-----------:|:--------------------------- + * `SPI_HOST0`/`SPI_HOST1` | SPICS0 | GPIO29 | - | reserved for Flash and PSRAM + * `SPI_HOST0`/`SPI_HOST1` | SPICS1 | GPIO26 | - | reserved for Flash and PSRAM + * `SPI_HOST0`/`SPI_HOST1` | SPICLK | GPIO30 | - | reserved for Flash and PSRAM + * `SPI_HOST0`/`SPI_HOST1` | SPID | GPIO32 | - | reserved for Flash and PSRAM + * `SPI_HOST0`/`SPI_HOST1` | SPIQ | GPIO31 | - | reserved for Flash and PSRAM + * `SPI_HOST0`/`SPI_HOST1` | SPIHD | GPIO27 | - | reserved for Flash and PSRAM (only in `qio` or `qout` mode) + * `SPI_HOST0`/`SPI_HOST1` | SPIWP | GPIO28 | - | reserved for Flash and PSRAM (only in `qio` or `qout` mode) + * `SPI_HOST0`/`SPI_HOST1` | SPIIO4 | GPIO33 | - | reserved for Flash and PSRAM (only in octal mode) + * `SPI_HOST0`/`SPI_HOST1` | SPIIO5 | GPIO34 | - | reserved for Flash and PSRAM (only in octal mode) + * `SPI_HOST0`/`SPI_HOST1` | SPIIO6 | GPIO35 | - | reserved for Flash and PSRAM (only in octal mode) + * `SPI_HOST0`/`SPI_HOST1` | SPIIO7 | GPIO36 | - | reserved for Flash and PSRAM (only in octal mode) + * `SPI_HOST0`/`SPI_HOST1` | SPIDQA | GPIO37 | - | reserved for Flash and PSRAM (only in octal mode) + * `SPI_HOST2` (`FSPI`) | SCK | GPIO36 |`#SPI0_SCK` | can be used + * `SPI_HOST2` (`FSPI`) | MOSI | GPIO35 |`#SPI0_MOSI` | can be used + * `SPI_HOST2` (`FSPI`) | MISO | GPIO37 |`#SPI0_MISO` | can be used + * `SPI_HOST2` (`FSPI`) | CS0 | GPIO38 |`#SPI0_CS0` | can be used + * `SPI_HOST3` (`HSPI`) | SCK | - |`#SPI1_SCK` | can be used + * `SPI_HOST3` (`HSPI`) | MOSI | - |`#SPI1_MOSI` | can be used + * `SPI_HOST3` (`HSPI`) | MISO | - |`#SPI1_MISO` | can be used + * `SPI_HOST3` (`HSPI`) | CS0 | - |`#SPI1_CS0` | can be used + * + *

+ */ + +/** + * @name Timer configuration depending on which implementation is used + * + * Timers are MCU built-in feature and not board-specific. They are therefore + * configured here. + * + * ESP32-S2 has two timer groups with two timers each, resulting in a total of + * four timers. Since one timer is used as system timer, up to three timers + * with one channel each can be used in RIOT as timer devices + * TIMER_DEV(0) ... TIMER_DEV(2). + * + * Additionally ESP32-S2 has three CCOMPARE registers which can be used + * alternatively as timer devices TIMER_DEV(0) ... TIMER_DEV(2) can be used + * in RIOT if the module `esp_hw_counter` is enabled. + */ + +#ifdef MODULE_ESP_HW_COUNTER +/** Hardware ccount/ccompare registers are used for timer implementation */ +#define TIMER_NUMOF (2) +#define TIMER_CHANNEL_NUMOF (1) +#endif + +/** + * @name UART configuration + * + * ESP32-S2 integrates two UART interfaces. The following default pin + * configuration of UART interfaces as used by a most boards can be overridden + * by the application, see section [Application-Specific Configurations] + * (#esp32_application_specific_configurations). + * + *
+ * + * Device |Signal|Pin |Symbol |Remarks + * :-----------|:-----|:-------|:-----------|:---------------- + * UART_DEV(0) | TxD | GPIO43 |`#UART0_TXD`| cannot be changed + * UART_DEV(0) | RxD | GPIO44 |`#UART0_RXD`| cannot be changed + * UART_DEV(1) | TxD | GPIO17 |`#UART1_TXD`| optional, can be overridden + * UART_DEV(1) | RxD | GPIO18 |`#UART1_RXD`| optional, can be overridden + * UART_DEV(2) | TxD | - |`UART2_TXD` | optional, can be overridden (no direct I/O) + * UART_DEV(2) | RxD | - |`UART2_RXD` | optional, can be overridden (no direct I/O) + * + *

+ * + */ + +#ifdef MODULE_PERIPH_CAN +#include "can_esp.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CPU_ESP32S2_H */ +/** @} */ diff --git a/cpu/esp32/include/sdkconfig.h b/cpu/esp32/include/sdkconfig.h index fe62dc58f2..49ce822592 100644 --- a/cpu/esp32/include/sdkconfig.h +++ b/cpu/esp32/include/sdkconfig.h @@ -83,6 +83,7 @@ #define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1 #define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32 #define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2560 +#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1 #define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1 #define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584 @@ -139,6 +140,9 @@ #define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1 #define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1 #define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_TH_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP 1 /** * Ethernet driver configuration (DO NOT CHANGE) @@ -211,6 +215,8 @@ #include "sdkconfig_esp32.h" #elif defined(CPU_FAM_ESP32C3) #include "sdkconfig_esp32c3.h" +#elif defined(CPU_FAM_ESP32S2) +#include "sdkconfig_esp32s2.h" #elif defined(CPU_FAM_ESP32S3) #include "sdkconfig_esp32s3.h" #else diff --git a/cpu/esp32/include/sdkconfig_esp32s2.h b/cpu/esp32/include/sdkconfig_esp32s2.h new file mode 100644 index 0000000000..5969ce2e37 --- /dev/null +++ b/cpu/esp32/include/sdkconfig_esp32s2.h @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_esp32 + * @{ + * + * @file + * @brief SDK configuration used by the ESP-IDF for ESP32-S2 SoC variant (family) + * + * The SDK configuration can be partially overridden by application-specific + * board configuration. + * + * @author Gunar Schorcht + */ + +#ifndef SDKCONFIG_ESP32S2_H +#define SDKCONFIG_ESP32S2_H + +#ifndef DOXYGEN + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name ESP32-S2 specific clock configuration + * @{ + */ + +/* Mapping of Kconfig defines to the respective enumeration values */ +#if CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_2 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 2 +#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_5 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 5 +#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_10 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 10 +#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_20 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 20 +#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_40 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 40 +#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_80 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 80 +#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_160 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 160 +#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_240 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 240 +#endif + +/** + * @brief Defines the CPU frequency [values = 2, 5, 10, 10, 40, 80, 160, 240] + */ +#ifndef CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 80 +#endif +/** @} */ + +/** + * ESP32-S2 specific RTC clock configuration + */ +#define CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES (8 * 1024) + +/** + * ESP32-S2 specific EFUSE configuration + */ +#define CONFIG_EFUSE_MAX_BLK_LEN 256 + +/** + * ESP32-S2 specific MAC configuration + */ +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1 +#define CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES 2 + +/** + * ESP32-S2 specific serial flasher config (DO NOT CHANGE) + */ +#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ "80m" + +/** + * ESP32-S2 specific system configuration (DO NOT CHANGE) + */ +#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1 +#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1 + +#define CONFIG_ESP32S2_DEBUG_OCDAWARE 1 + +#define CONFIG_ESP32S2_BROWNOUT_DET 1 +#define CONFIG_ESP32S2_BROWNOUT_DET_LVL 7 + +#define CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM 0x0 +#define CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM 0 + +/** + * ESP32-S2 specific sleep configuration (DO NOT CHANGE) + */ +#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1 + +/** + * ESP32-S2 specific PHY configuration + */ +#define CONFIG_USB_OTG_SUPPORTED 0 +#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256 +#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1 + +/** + * ESP32-S2 specific SPI RAM configuration + */ +#ifdef MODULE_ESP_SPI_RAM +#define CONFIG_ESP32S2_SPIRAM_SUPPORT 1 +#ifdef MODULE_ESP_SPI_OCT +#define CONFIG_SPIRAM_MODE_OCT 1 +#else +#define CONFIG_SPIRAM_MODE_QUAD 1 +#endif +#define CONFIG_DEFAULT_PSRAM_CLK_IO 30 +#define CONFIG_DEFAULT_PSRAM_CS_IO 26 +#define CONFIG_SPIRAM_SUPPORT CONFIG_ESP32S2_SPIRAM_SUPPORT +#endif + +/** + * ESP32-S2 specific Cache config + */ +#define CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB 1 +#define CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B 1 +#define CONFIG_ESP32S2_DATA_CACHE_8KB 1 +#define CONFIG_ESP32S2_DATA_CACHE_LINE_32B 1 + +/** + * ESP32-S2 specific system configuration + */ +#define CONFIG_ESP_SYSTEM_MEMPROT_DEPCHECK 1 +#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 0 /* default enabled */ +#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK 0 /* default enabled */ +#define CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 +#define CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE 4 + +#ifdef __cplusplus +} +#endif + +#endif /* DOXYGEN */ +#endif /* SDKCONFIG_ESP32S2_H */ +/** @} */ diff --git a/dist/tools/doccheck/exclude_patterns b/dist/tools/doccheck/exclude_patterns index 10f95f9612..0e1c01f823 100644 --- a/dist/tools/doccheck/exclude_patterns +++ b/dist/tools/doccheck/exclude_patterns @@ -13133,6 +13133,7 @@ boards/common/esp32c3/include/board_common.h:[0-9]+: warning: Member SPIFFS_[_A- cpu/esp32/include/periph_cpu_esp32s3\.h:[0-9]+: warning: Member GPIO[0-9]+ \(macro definition\) of file periph_cpu_esp32s3\.h is not documented. boards/common/esp32s3/include/board_common.h:[0-9]+: warning: Member LED[0-9]_[A-Z]+ \(macro definition\) of file board_common\.h is not documented. boards/common/esp32s3/include/board_common.h:[0-9]+: warning: Member SPIFFS_[_A-Z]+ \(macro definition\) of file board_common\.h is not documented. +cpu/esp32/include/periph_cpu_esp32s2\.h:[0-9]+: warning: Member GPIO[0-9]+ \(macro definition\) of file periph_cpu_esp32s2\.h is not documented. boards/waveshare\-nrf52840\-eval\-kit/include/arduino_pinmap\.h:[0-9]+: warning: Member ARDUINO_PIN_[A0-9]+ \(macro definition\) of file arduino_pinmap\.h is not documented. boards/waveshare\-nrf52840\-eval\-kit/include/arduino_pinmap\.h:[0-9]+: warning: Member ARDUINO_[A0-9]+ \(macro definition\) of file arduino_pinmap\.h is not documented. boards/waveshare\-nrf52840\-eval\-kit/include/board\.h:[0-9]+: warning: Member LED[A-Z0-9_]+ \(macro definition\) of file board\.h is not documented.