From dd0593a3c87ca794b23ea549447357a481d2ad72 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Sun, 8 Jan 2023 10:38:36 +0100 Subject: [PATCH] cpu/gd32v: fix clock setting Setting the `RCU_CTL` register just to the IRC8M bit also removes the IRC8M calibration and trim adjust value in this register. Therefore IRC8M calibration and trim adjust value have to be preserved and the IRC8M has to be set. --- boards/seeedstudio-gd32/include/periph_conf.h | 2 +- cpu/gd32v/clock.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/boards/seeedstudio-gd32/include/periph_conf.h b/boards/seeedstudio-gd32/include/periph_conf.h index 72342297e2..7e81b68ebb 100644 --- a/boards/seeedstudio-gd32/include/periph_conf.h +++ b/boards/seeedstudio-gd32/include/periph_conf.h @@ -32,7 +32,7 @@ extern "C" { #endif #define CLOCK_HXTAL MHZ(8) /**< HXTAL frequency */ -#define CLOCK_CORECLOCK MHZ(104) /**< CPU clock frequency in Hz */ +#define CLOCK_CORECLOCK MHZ(108) /**< CPU clock frequency in Hz */ /** * @name Timer configuration diff --git a/cpu/gd32v/clock.c b/cpu/gd32v/clock.c index d9146d0353..ca0d5d0a7e 100644 --- a/cpu/gd32v/clock.c +++ b/cpu/gd32v/clock.c @@ -119,7 +119,8 @@ void gd32vf103_clock_init(void) (RCU_CFG0_SCS_IRC8 << RCU_CFG0_SCSS_Pos)) {} /* disable all active clocks except IRC8 -> resets the clk configuration */ - RCU->CTL = (RCU_CTL_IRC8MEN_Msk); + RCU->CTL &= (RCU_CTL_IRC8MCALIB_Msk | RCU_CTL_IRC8MADJ_Msk); + RCU->CTL |= RCU_CTL_IRC8MEN_Msk; if (IS_ACTIVE(CONFIG_BOARD_HAS_HXTAL)) { cpu_reg_enable_bits(&RCU->CTL, RCU_CTL_HXTALEN_Msk);