diff --git a/cpu/k60/Makefile b/cpu/k60/Makefile new file mode 100644 index 0000000000..ae17a35174 --- /dev/null +++ b/cpu/k60/Makefile @@ -0,0 +1,7 @@ +# define the module that is build +MODULE = cpu + +# add a list of subdirectories, that should also be build +DIRS = periph $(CORTEX_M4_COMMON) devio $(KINETIS_COMMON) + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/k60/Makefile.include b/cpu/k60/Makefile.include new file mode 100644 index 0000000000..ceee8cb5dc --- /dev/null +++ b/cpu/k60/Makefile.include @@ -0,0 +1,42 @@ +# this CPU implementation is using the explicit core/CPU interface +export CFLAGS += -DCOREIF_NG=1 + +# export the peripheral drivers to be linked into the final binary +export USEMODULE += periph + +# Posix device I/O interface +export USEMODULE += devio + +# tell the build system that the CPU depends on the Cortex-M common files +export USEMODULE += cortex-m4_common + +# tell the build system that the CPU depends on the Kinetis common files +export USEMODULE += kinetis_common + +# define path to cortex-m common module, which is needed for this CPU +export CORTEX_M4_COMMON = $(RIOTCPU)/cortex-m4_common/ + +# define path to kinetis module, which is needed for this CPU +export KINETIS_COMMON = $(RIOTCPU)/kinetis_common/ + +# CPU depends on the cortex-m common module, so include it +include $(CORTEX_M4_COMMON)Makefile.include + +# CPU depends on the kinetis module, so include it +include $(KINETIS_COMMON)Makefile.include + +# define the linker script to use for this CPU +export LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ldscripts +export LINKERSCRIPT = $(CPU_MODEL).ld + +#export the CPU model +MODEL = $(shell echo $(CPU_MODEL)|tr 'a-z' 'A-Z') +export CFLAGS += -DCPU_MODEL_$(MODEL) + +# include CPU specific includes +export INCLUDES += -I$(RIOTCPU)/$(CPU)/include + +# add the CPU specific system calls implementations for the linker +export UNDEF += $(BINDIR)cpu/syscalls.o +export UNDEF += $(BINDIR)cpu/ssp.o +export UNDEF += $(BINDIR)cpu/interrupt_vector.o diff --git a/cpu/k60/cpu.c b/cpu/k60/cpu.c new file mode 100644 index 0000000000..d48b1d348f --- /dev/null +++ b/cpu/k60/cpu.c @@ -0,0 +1,248 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +#include +#include "cpu.h" +#include "board.h" + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Implementation of K60 CPU initialization. + * + * @author Joakim Gebart + */ + +extern void *_vector_rom[]; + +/** @brief Current core clock frequency */ +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; +/** @brief Current system clock frequency */ +uint32_t SystemSysClock = DEFAULT_SYSTEM_CLOCK; +/** @brief Current bus clock frequency */ +uint32_t SystemBusClock = DEFAULT_SYSTEM_CLOCK; +/** @brief Current FlexBus clock frequency */ +uint32_t SystemFlexBusClock = DEFAULT_SYSTEM_CLOCK; +/** @brief Current flash clock frequency */ +uint32_t SystemFlashClock = DEFAULT_SYSTEM_CLOCK; +/** @brief Number of full PIT ticks in one microsecond. */ +uint32_t PIT_ticks_per_usec = (DEFAULT_SYSTEM_CLOCK / 1000000ul); + +/** + * @brief Check the running CPU identification to find if we are running on the + * wrong hardware. + */ +static void check_running_cpu_revision(void); + +/** + * @brief Initialize the CPU, set IRQ priorities + */ +void cpu_init(void) +{ + /* Check that we are running on the CPU that this code was built for */ + check_running_cpu_revision(); + + /* configure the vector table location to internal flash */ + SCB->VTOR = (uint32_t)_vector_rom; + + /* set pendSV interrupt to lowest possible priority */ + NVIC_SetPriority(PendSV_IRQn, 0xff); + +} + +static void check_running_cpu_revision(void) +{ + /* Check that the running CPU revision matches the compiled revision */ + if (SCB->CPUID != K60_EXPECTED_CPUID) { + uint32_t CPUID = SCB->CPUID; /* This is only to ease debugging, type + * "print /x CPUID" in gdb */ + uint32_t SILICON_REVISION = (SCB->CPUID & SCB_CPUID_REVISION_Msk) + 1; + (void)CPUID; /* prevents compiler warnings about an unused variable. */ + (void)SILICON_REVISION; + + /* Running on the wrong CPU, the clock initialization is different + * between silicon revision 1.x and 2.x (LSB of CPUID) */ + /* If you unexpectedly end up on this line when debugging: + * Rebuild the code using the correct value for K60_CPU_REV */ + __ASM volatile ("bkpt #99\n"); + + while (1); + } +} + +void SystemCoreClockUpdate(void) +{ + /* Variable to store output clock frequency of the MCG module */ + uint32_t MCGOUT_clock; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { + /* External reference clock is selected */ +#if K60_CPU_REV == 1 + /* rev.1 silicon */ + if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) { + /* System oscillator drives MCG clock */ + MCGOUT_clock = CPU_XTAL_CLK_HZ; + } + else { + /* RTC 32 kHz oscillator drives MCG clock */ + MCGOUT_clock = CPU_XTAL32k_CLK_HZ; + } + +#else /* K60_CPU_REV */ + + /* rev.2 silicon */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + /* System oscillator drives MCG clock */ + MCGOUT_clock = CPU_XTAL_CLK_HZ; + } + else { + /* RTC 32 kHz oscillator drives MCG clock */ + MCGOUT_clock = CPU_XTAL32k_CLK_HZ; + } + +#endif /* K60_CPU_REV */ + uint8_t divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + /* Calculate the divided FLL reference clock */ + MCGOUT_clock /= divider; + + if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { + /* If high range is enabled, additional 32 divider is active */ + MCGOUT_clock /= 32u; + } + } + else { + /* The slow internal reference clock is selected */ + MCGOUT_clock = CPU_INT_SLOW_CLK_HZ; + } + + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case (0x0u): + MCGOUT_clock *= 640u; + break; + + case (MCG_C4_DRST_DRS(0b01)): /* 0x20u */ + MCGOUT_clock *= 1280u; + break; + + case (MCG_C4_DRST_DRS(0b10)): /* 0x40u */ + MCGOUT_clock *= 1920u; + break; + + case (MCG_C4_DRST_DRS(0b11)): /* 0x60u */ + MCGOUT_clock *= 2560u; + break; + + case (MCG_C4_DMX32_MASK): /* 0x80u */ + MCGOUT_clock *= 732u; + break; + + case (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0b01)): /* 0xA0u */ + MCGOUT_clock *= 1464u; + break; + + case (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0b10)): /* 0xC0u */ + MCGOUT_clock *= 2197u; + break; + + case (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0b11)): /* 0xE0u */ + MCGOUT_clock *= 2929u; + break; + + default: + break; + } + } + else { + /* PLL is selected */ + /* Calculate the PLL reference clock */ + uint8_t divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); + MCGOUT_clock = (uint32_t)(CPU_XTAL_CLK_HZ / divider); + /* Calculate the MCG output clock */ + divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); + MCGOUT_clock *= divider; + } + } + else if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0b01)) { /* 0x40u */ + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { + /* Slow internal reference clock selected */ + MCGOUT_clock = CPU_INT_SLOW_CLK_HZ; + } + else { + /* Fast internal reference clock selected */ +#if K60_CPU_REV == 1 + /* rev.1 silicon */ + MCGOUT_clock = CPU_INT_FAST_CLK_HZ; +#else /* K60_CPU_REV */ + /* rev.2 silicon */ + MCGOUT_clock = CPU_INT_FAST_CLK_HZ / + (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); +#endif /* K60_CPU_REV */ + } + } + else if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0b10)) { /* 0x80u */ + /* External reference clock is selected */ +#if K60_CPU_REV == 1 + /* rev.1 silicon */ + if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) { + /* System oscillator drives MCG clock */ + MCGOUT_clock = CPU_XTAL_CLK_HZ; + } + else { + /* RTC 32 kHz oscillator drives MCG clock */ + MCGOUT_clock = CPU_XTAL32k_CLK_HZ; + } + +#else /* K60_CPU_REV */ + + /* rev.2 silicon */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + /* System oscillator drives MCG clock */ + MCGOUT_clock = CPU_XTAL_CLK_HZ; + } + else { + /* RTC 32 kHz oscillator drives MCG clock */ + MCGOUT_clock = CPU_XTAL32k_CLK_HZ; + } + +#endif /* K60_CPU_REV */ + } + else { + /* Reserved value */ + return; + } + + /* Core clock and system clock use the same divider setting */ + SystemCoreClock = SystemSysClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) + >> SIM_CLKDIV1_OUTDIV1_SHIFT))); + SystemBusClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> + SIM_CLKDIV1_OUTDIV2_SHIFT))); + SystemFlexBusClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> + SIM_CLKDIV1_OUTDIV3_SHIFT))); + SystemFlashClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> + SIM_CLKDIV1_OUTDIV4_SHIFT))); + + /* Module helper variables */ + if (SystemBusClock >= 1000000) { + /* PIT module clock_delay_usec scale factor */ + PIT_ticks_per_usec = (SystemBusClock + 500000) / 1000000; /* Rounded to nearest integer */ + } + else { + /* less than 1 MHz clock frequency on the PIT module, round up. */ + PIT_ticks_per_usec = 1; + } +} + +/** @} */ diff --git a/cpu/k60/devio/Makefile b/cpu/k60/devio/Makefile new file mode 100644 index 0000000000..b99e0bff11 --- /dev/null +++ b/cpu/k60/devio/Makefile @@ -0,0 +1,3 @@ +MODULE = devio + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/k60/devio/devio-null.c b/cpu/k60/devio/devio-null.c new file mode 100644 index 0000000000..8b53985ea1 --- /dev/null +++ b/cpu/k60/devio/devio-null.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Device I/O helpers for a no-op device, implementations. + * + * @author Joakim Gebart + * + * @} + */ + +#include +#include +#include +#include "devio-null.h" + +int devnull_open_r(struct _reent *r, const char *path, int flags, int mode) +{ + return 0; +} + +int devnull_close_r(struct _reent *r, int fd) +{ + return 0; +} + +long devnull_write_r(struct _reent *r, int fd, const char *ptr, int len) +{ + /* Aaand... it's gone!*/ + return len; +} + +long devnull_read_r(struct _reent *r, int fd, char *ptr, int len) +{ + /* Read null bytes */ + memset(ptr, '\0', len); + return len; +} + +long devnull_lseek_r(struct _reent *r, int fd, int ptr, int dir) +{ + r->_errno = ENOSYS; + return -1; +} + +long devnull_fstat_r(struct _reent *r, int fd, char *ptr, int len) +{ + r->_errno = ENOSYS; + return -1; +} diff --git a/cpu/k60/devio/devio-uart.c b/cpu/k60/devio/devio-uart.c new file mode 100644 index 0000000000..ff44d07840 --- /dev/null +++ b/cpu/k60/devio/devio-uart.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Device I/O helpers for UARTs on K60, implementation. + * + * @author Joakim Gebart + * + * @} + */ + +#include +#include "devio-uart.h" +#include "periph/uart.h" +#include "cpu.h" + +static inline long uart_write_r(uart_t uart_num, struct _reent *r, int fd, const char *ptr, + int len) +{ + int i = 0; + + while (i < len) { + uart_write_blocking(uart_num, ptr[i]); + ++i; + } + + return i; +} + +static long uart_read_r(uart_t uart_num, struct _reent *r, int fd, char *ptr, int len) +{ + /* not yet implemented */ + return 0; +} + +#if UART_0_EN +long uart0_write_r(struct _reent *r, int fd, const char *ptr, int len) +{ + return uart_write_r(UART_0, r, fd, ptr, len); +} +#endif + +#if UART_1_EN +long uart1_write_r(struct _reent *r, int fd, const char *ptr, int len) +{ + return uart_write_r(UART_1, r, fd, ptr, len); +} +#endif + +#if UART_2_EN +long uart2_write_r(struct _reent *r, int fd, const char *ptr, int len) +{ + return uart_write_r(UART_2, r, fd, ptr, len); +} +#endif + +#if UART_3_EN +long uart3_write_r(struct _reent *r, int fd, const char *ptr, int len) +{ + return uart_write_r(UART_3, r, fd, ptr, len); +} +#endif + +#if UART_4_EN +long uart4_write_r(struct _reent *r, int fd, const char *ptr, int len) +{ + return uart_write_r(UART_4, r, fd, ptr, len); +} +#endif + +#if UART_0_EN +long uart0_read_r(struct _reent *r, int fd, char *ptr, int len) +{ + return uart_read_r(UART_0, r, fd, ptr, len); +} +#endif diff --git a/cpu/k60/include/MK60-comp.h b/cpu/k60/include/MK60-comp.h new file mode 100644 index 0000000000..ccd6d52011 --- /dev/null +++ b/cpu/k60/include/MK60-comp.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Compatibility definitions between MK60D10.h and MK60DZ10.h + * + * @author Joakim Gebart + */ + +#ifndef MK60_COMP_H_ +#define MK60_COMP_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if K60_CPU_REV == 1 + +/* Some compatibility defines to minimize the ifdefs needed for the register + * name changes */ + +#define SIM_SCGC6_SPI0_MASK SIM_SCGC6_DSPI0_MASK +#define SIM_SCGC6_SPI0_SHIFT SIM_SCGC6_DSPI0_SHIFT + +#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK +#define MCG_C5_PRDIV0_MASK MCG_C5_PRDIV_MASK +#define MCG_C6_VDIV0_MASK MCG_C6_VDIV_MASK + +#define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 } + +#define LPTMR0_IRQn LPTimer_IRQn + +/* Rev 2.x made the OSC32KSEL field into a bitfield (is a single bit in 1.x) */ +#define SIM_SOPT1_OSC32KSEL(a) (SIM_SOPT1_OSC32KSEL_MASK) + +#endif /* K60_CPU_REV == 1 */ + + +/* Compatibility defines for compatibility with differing module names between + * MK60 and MKW22 headers */ +#define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK +#define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT + +#ifndef OSC0 +/* Compatibility definition */ +#define OSC0 OSC +#endif +#ifndef MCG_C2_RANGE0 +/* Rev 2 parts renamed the parameter RANGE -> RANGE0 */ +#define MCG_C2_RANGE0 MCG_C2_RANGE +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* MK60_COMP_H_ */ +/** @} */ diff --git a/cpu/k60/include/MK60D10.h b/cpu/k60/include/MK60D10.h new file mode 100644 index 0000000000..38e263ede1 --- /dev/null +++ b/cpu/k60/include/MK60D10.h @@ -0,0 +1,14597 @@ +/* +** ################################################################### +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** GNU C Compiler - CodeSourcery Sourcery G++ +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K60P144M100SF2V2RM Rev. 2, Jun 2012 +** Version: rev. 1.8, 2014-10-14 +** Build: b141015 +** +** Abstract: +** CMSIS Peripheral Access Layer for MK60D10 +** +** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2012-01-03) +** Initial version +** - rev. 1.1 (2012-04-13) +** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR. +** Added new #define symbols _BASE_PTRS. +** - rev. 1.2 (2012-07-09) +** UART0 - Fixed register definition - CEA709.1-B (LON) registers added. +** - rev. 1.3 (2012-10-29) +** Registers updated according to the new reference manual revision - Rev. 2, Jun 2012 +** - rev. 1.4 (2013-04-05) +** Changed start of doxygen comment. +** - rev. 1.5 (2013-06-24) +** NV_FOPT register - NMI_DIS bit added. +** SPI - PCSIS bit group in MCR register updated. +** - rev. 1.6 (2014-07-23) +** Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. +** Predefined SystemInit() implementation updated: +** - External clock sources available on TWR board used. +** - Added 1 ms waiting loop after entering FLL engaged MCG mode. +** - rev. 1.7 (2014-08-28) +** Update of startup files - possibility to override DefaultISR added. +** - rev. 1.8 (2014-10-14) +** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0 +** +** ################################################################### +*/ + +/*! + * @file MK60D10.h + * @version 1.8 + * @date 2014-10-14 + * @brief CMSIS Peripheral Access Layer for MK60D10 + * + * CMSIS Peripheral Access Layer for MK60D10 + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(MK60D10_H_) /* Check if memory map has not been already included */ +#define MK60D10_H_ +#define MCU_MK60D10 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error MK60D10 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0008u + +/** + * @brief Macro to calculate address of an aliased word in the peripheral + * bitband area for a peripheral register and bit (bit band region 0x40000000 to + * 0x400FFFFF). + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Address of the aliased word in the peripheral bitband area. + */ +#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 32bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 16bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 8bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 120 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ + DMA4_IRQn = 4, /**< DMA channel 4 transfer complete */ + DMA5_IRQn = 5, /**< DMA channel 5 transfer complete */ + DMA6_IRQn = 6, /**< DMA channel 6 transfer complete */ + DMA7_IRQn = 7, /**< DMA channel 7 transfer complete */ + DMA8_IRQn = 8, /**< DMA channel 8 transfer complete */ + DMA9_IRQn = 9, /**< DMA channel 9 transfer complete */ + DMA10_IRQn = 10, /**< DMA channel 10 transfer complete */ + DMA11_IRQn = 11, /**< DMA channel 11 transfer complete */ + DMA12_IRQn = 12, /**< DMA channel 12 transfer complete */ + DMA13_IRQn = 13, /**< DMA channel 13 transfer complete */ + DMA14_IRQn = 14, /**< DMA channel 14 transfer complete */ + DMA15_IRQn = 15, /**< DMA channel 15 transfer complete */ + DMA_Error_IRQn = 16, /**< DMA channel 0 - 15 error */ + MCM_IRQn = 17, /**< MCM normal interrupt */ + FTFL_IRQn = 18, /**< FTFL command complete */ + Read_Collision_IRQn = 19, /**< FTFL read collision */ + LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */ + LLW_IRQn = 21, /**< Low leakage wakeup */ + WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */ + RNG_IRQn = 23, /**< Randon number generator */ + I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */ + I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */ + SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */ + SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */ + SPI2_IRQn = 28, /**< Serial peripheral Interface 1 */ + CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 ORed message buffers */ + CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off */ + CAN0_Error_IRQn = 31, /**< CAN0 error */ + CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning */ + CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning */ + CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up */ + I2S0_Tx_IRQn = 35, /**< Integrated interchip sound 0 transmit interrupt */ + I2S0_Rx_IRQn = 36, /**< Integrated interchip sound 0 receive interrupt */ + CAN1_ORed_Message_buffer_IRQn = 37, /**< CAN1 OR'd message buffers interrupt */ + CAN1_Bus_Off_IRQn = 38, /**< CAN1 bus off interrupt */ + CAN1_Error_IRQn = 39, /**< CAN1 error interrupt */ + CAN1_Tx_Warning_IRQn = 40, /**< CAN1 Tx warning interrupt */ + CAN1_Rx_Warning_IRQn = 41, /**< CAN1 Rx warning interrupt */ + CAN1_Wake_Up_IRQn = 42, /**< CAN1 wake up interrupt */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + UART0_LON_IRQn = 44, /**< UART0 LON */ + UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */ + UART0_ERR_IRQn = 46, /**< UART0 error interrupt */ + UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */ + UART1_ERR_IRQn = 48, /**< UART1 error interrupt */ + UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */ + UART2_ERR_IRQn = 50, /**< UART2 error interrupt */ + UART3_RX_TX_IRQn = 51, /**< UART3 receive/transmit interrupt */ + UART3_ERR_IRQn = 52, /**< UART3 error interrupt */ + UART4_RX_TX_IRQn = 53, /**< UART4 receive/transmit interrupt */ + UART4_ERR_IRQn = 54, /**< UART4 error interrupt */ + UART5_RX_TX_IRQn = 55, /**< UART5 receive/transmit interrupt */ + UART5_ERR_IRQn = 56, /**< UART5 error interrupt */ + ADC0_IRQn = 57, /**< Analog-to-digital converter 0 */ + ADC1_IRQn = 58, /**< Analog-to-digital converter 1 */ + CMP0_IRQn = 59, /**< Comparator 0 */ + CMP1_IRQn = 60, /**< Comparator 1 */ + CMP2_IRQn = 61, /**< Comparator 2 */ + FTM0_IRQn = 62, /**< FlexTimer module 0 fault, overflow and channels interrupt */ + FTM1_IRQn = 63, /**< FlexTimer module 1 fault, overflow and channels interrupt */ + FTM2_IRQn = 64, /**< FlexTimer module 2 fault, overflow and channels interrupt */ + CMT_IRQn = 65, /**< Carrier modulator transmitter */ + RTC_IRQn = 66, /**< Real time clock */ + RTC_Seconds_IRQn = 67, /**< Real time clock seconds */ + PIT0_IRQn = 68, /**< Periodic interrupt timer channel 0 */ + PIT1_IRQn = 69, /**< Periodic interrupt timer channel 1 */ + PIT2_IRQn = 70, /**< Periodic interrupt timer channel 2 */ + PIT3_IRQn = 71, /**< Periodic interrupt timer channel 3 */ + PDB0_IRQn = 72, /**< Programmable delay block */ + USB0_IRQn = 73, /**< USB OTG interrupt */ + USBDCD_IRQn = 74, /**< USB charger detect */ + ENET_1588_Timer_IRQn = 75, /**< Ethernet MAC IEEE 1588 timer */ + ENET_Transmit_IRQn = 76, /**< Ethernet MAC transmit */ + ENET_Receive_IRQn = 77, /**< Ethernet MAC receive */ + ENET_Error_IRQn = 78, /**< Ethernet MAC error and miscelaneous */ + Reserved95_IRQn = 79, /**< Reserved interrupt */ + SDHC_IRQn = 80, /**< Secured digital host controller */ + DAC0_IRQn = 81, /**< Digital-to-analog converter 0 */ + DAC1_IRQn = 82, /**< Digital-to-analog converter 1 */ + TSI0_IRQn = 83, /**< TSI0 Interrupt */ + MCG_IRQn = 84, /**< Multipurpose clock generator */ + LPTMR0_IRQn = 85, /**< Low power timer interrupt */ + Reserved102_IRQn = 86, /**< Reserved interrupt */ + PORTA_IRQn = 87, /**< Port A interrupt */ + PORTB_IRQn = 88, /**< Port B interrupt */ + PORTC_IRQn = 89, /**< Port C interrupt */ + PORTD_IRQn = 90, /**< Port D interrupt */ + PORTE_IRQn = 91, /**< Port E interrupt */ + Reserved108_IRQn = 92, /**< Reserved interrupt */ + Reserved109_IRQn = 93, /**< Reserved interrupt */ + SWI_IRQn = 94, /**< Software interrupt */ + Reserved111_IRQn = 95, /**< Reserved interrupt */ + Reserved112_IRQn = 96, /**< Reserved interrupt */ + Reserved113_IRQn = 97, /**< Reserved interrupt */ + Reserved114_IRQn = 98, /**< Reserved interrupt */ + Reserved115_IRQn = 99, /**< Reserved interrupt */ + Reserved116_IRQn = 100, /**< Reserved interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MK60D10.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ + __IO uint32_t PGA; /**< ADC PGA Register, offset: 0x50 */ + __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ +} ADC_Type, *ADC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ADC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros + * @{ + */ + + +/* ADC - Register accessors */ +#define ADC_SC1_REG(base,index) ((base)->SC1[index]) +#define ADC_CFG1_REG(base) ((base)->CFG1) +#define ADC_CFG2_REG(base) ((base)->CFG2) +#define ADC_R_REG(base,index) ((base)->R[index]) +#define ADC_CV1_REG(base) ((base)->CV1) +#define ADC_CV2_REG(base) ((base)->CV2) +#define ADC_SC2_REG(base) ((base)->SC2) +#define ADC_SC3_REG(base) ((base)->SC3) +#define ADC_OFS_REG(base) ((base)->OFS) +#define ADC_PG_REG(base) ((base)->PG) +#define ADC_MG_REG(base) ((base)->MG) +#define ADC_CLPD_REG(base) ((base)->CLPD) +#define ADC_CLPS_REG(base) ((base)->CLPS) +#define ADC_CLP4_REG(base) ((base)->CLP4) +#define ADC_CLP3_REG(base) ((base)->CLP3) +#define ADC_CLP2_REG(base) ((base)->CLP2) +#define ADC_CLP1_REG(base) ((base)->CLP1) +#define ADC_CLP0_REG(base) ((base)->CLP0) +#define ADC_PGA_REG(base) ((base)->PGA) +#define ADC_CLMD_REG(base) ((base)->CLMD) +#define ADC_CLMS_REG(base) ((base)->CLMS) +#define ADC_CLM4_REG(base) ((base)->CLM4) +#define ADC_CLM3_REG(base) ((base)->CLM3) +#define ADC_CLM2_REG(base) ((base)->CLM2) +#define ADC_CLM1_REG(base) ((base)->CLM1) +#define ADC_CLM0_REG(base) ((base)->CLM0) + +/*! + * @} + */ /* end of group ADC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0 +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<MPRA) +#define AIPS_PACRA_REG(base) ((base)->PACRA) +#define AIPS_PACRB_REG(base) ((base)->PACRB) +#define AIPS_PACRC_REG(base) ((base)->PACRC) +#define AIPS_PACRD_REG(base) ((base)->PACRD) +#define AIPS_PACRE_REG(base) ((base)->PACRE) +#define AIPS_PACRF_REG(base) ((base)->PACRF) +#define AIPS_PACRG_REG(base) ((base)->PACRG) +#define AIPS_PACRH_REG(base) ((base)->PACRH) +#define AIPS_PACRI_REG(base) ((base)->PACRI) +#define AIPS_PACRJ_REG(base) ((base)->PACRJ) +#define AIPS_PACRK_REG(base) ((base)->PACRK) +#define AIPS_PACRL_REG(base) ((base)->PACRL) +#define AIPS_PACRM_REG(base) ((base)->PACRM) +#define AIPS_PACRN_REG(base) ((base)->PACRN) +#define AIPS_PACRO_REG(base) ((base)->PACRO) +#define AIPS_PACRP_REG(base) ((base)->PACRP) + +/*! + * @} + */ /* end of group AIPS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- AIPS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPS_Register_Masks AIPS Register Masks + * @{ + */ + +/* MPRA Bit Fields */ +#define AIPS_MPRA_MPL5_MASK 0x100u +#define AIPS_MPRA_MPL5_SHIFT 8 +#define AIPS_MPRA_MTW5_MASK 0x200u +#define AIPS_MPRA_MTW5_SHIFT 9 +#define AIPS_MPRA_MTR5_MASK 0x400u +#define AIPS_MPRA_MTR5_SHIFT 10 +#define AIPS_MPRA_MPL4_MASK 0x1000u +#define AIPS_MPRA_MPL4_SHIFT 12 +#define AIPS_MPRA_MTW4_MASK 0x2000u +#define AIPS_MPRA_MTW4_SHIFT 13 +#define AIPS_MPRA_MTR4_MASK 0x4000u +#define AIPS_MPRA_MTR4_SHIFT 14 +#define AIPS_MPRA_MPL3_MASK 0x10000u +#define AIPS_MPRA_MPL3_SHIFT 16 +#define AIPS_MPRA_MTW3_MASK 0x20000u +#define AIPS_MPRA_MTW3_SHIFT 17 +#define AIPS_MPRA_MTR3_MASK 0x40000u +#define AIPS_MPRA_MTR3_SHIFT 18 +#define AIPS_MPRA_MPL2_MASK 0x100000u +#define AIPS_MPRA_MPL2_SHIFT 20 +#define AIPS_MPRA_MTW2_MASK 0x200000u +#define AIPS_MPRA_MTW2_SHIFT 21 +#define AIPS_MPRA_MTR2_MASK 0x400000u +#define AIPS_MPRA_MTR2_SHIFT 22 +#define AIPS_MPRA_MPL1_MASK 0x1000000u +#define AIPS_MPRA_MPL1_SHIFT 24 +#define AIPS_MPRA_MTW1_MASK 0x2000000u +#define AIPS_MPRA_MTW1_SHIFT 25 +#define AIPS_MPRA_MTR1_MASK 0x4000000u +#define AIPS_MPRA_MTR1_SHIFT 26 +#define AIPS_MPRA_MPL0_MASK 0x10000000u +#define AIPS_MPRA_MPL0_SHIFT 28 +#define AIPS_MPRA_MTW0_MASK 0x20000000u +#define AIPS_MPRA_MTW0_SHIFT 29 +#define AIPS_MPRA_MTR0_MASK 0x40000000u +#define AIPS_MPRA_MTR0_SHIFT 30 +/* PACRA Bit Fields */ +#define AIPS_PACRA_TP7_MASK 0x1u +#define AIPS_PACRA_TP7_SHIFT 0 +#define AIPS_PACRA_WP7_MASK 0x2u +#define AIPS_PACRA_WP7_SHIFT 1 +#define AIPS_PACRA_SP7_MASK 0x4u +#define AIPS_PACRA_SP7_SHIFT 2 +#define AIPS_PACRA_TP6_MASK 0x10u +#define AIPS_PACRA_TP6_SHIFT 4 +#define AIPS_PACRA_WP6_MASK 0x20u +#define AIPS_PACRA_WP6_SHIFT 5 +#define AIPS_PACRA_SP6_MASK 0x40u +#define AIPS_PACRA_SP6_SHIFT 6 +#define AIPS_PACRA_TP5_MASK 0x100u +#define AIPS_PACRA_TP5_SHIFT 8 +#define AIPS_PACRA_WP5_MASK 0x200u +#define AIPS_PACRA_WP5_SHIFT 9 +#define AIPS_PACRA_SP5_MASK 0x400u +#define AIPS_PACRA_SP5_SHIFT 10 +#define AIPS_PACRA_TP4_MASK 0x1000u +#define AIPS_PACRA_TP4_SHIFT 12 +#define AIPS_PACRA_WP4_MASK 0x2000u +#define AIPS_PACRA_WP4_SHIFT 13 +#define AIPS_PACRA_SP4_MASK 0x4000u +#define AIPS_PACRA_SP4_SHIFT 14 +#define AIPS_PACRA_TP3_MASK 0x10000u +#define AIPS_PACRA_TP3_SHIFT 16 +#define AIPS_PACRA_WP3_MASK 0x20000u +#define AIPS_PACRA_WP3_SHIFT 17 +#define AIPS_PACRA_SP3_MASK 0x40000u +#define AIPS_PACRA_SP3_SHIFT 18 +#define AIPS_PACRA_TP2_MASK 0x100000u +#define AIPS_PACRA_TP2_SHIFT 20 +#define AIPS_PACRA_WP2_MASK 0x200000u +#define AIPS_PACRA_WP2_SHIFT 21 +#define AIPS_PACRA_SP2_MASK 0x400000u +#define AIPS_PACRA_SP2_SHIFT 22 +#define AIPS_PACRA_TP1_MASK 0x1000000u +#define AIPS_PACRA_TP1_SHIFT 24 +#define AIPS_PACRA_WP1_MASK 0x2000000u +#define AIPS_PACRA_WP1_SHIFT 25 +#define AIPS_PACRA_SP1_MASK 0x4000000u +#define AIPS_PACRA_SP1_SHIFT 26 +#define AIPS_PACRA_TP0_MASK 0x10000000u +#define AIPS_PACRA_TP0_SHIFT 28 +#define AIPS_PACRA_WP0_MASK 0x20000000u +#define AIPS_PACRA_WP0_SHIFT 29 +#define AIPS_PACRA_SP0_MASK 0x40000000u +#define AIPS_PACRA_SP0_SHIFT 30 +/* PACRB Bit Fields */ +#define AIPS_PACRB_TP7_MASK 0x1u +#define AIPS_PACRB_TP7_SHIFT 0 +#define AIPS_PACRB_WP7_MASK 0x2u +#define AIPS_PACRB_WP7_SHIFT 1 +#define AIPS_PACRB_SP7_MASK 0x4u +#define AIPS_PACRB_SP7_SHIFT 2 +#define AIPS_PACRB_TP6_MASK 0x10u +#define AIPS_PACRB_TP6_SHIFT 4 +#define AIPS_PACRB_WP6_MASK 0x20u +#define AIPS_PACRB_WP6_SHIFT 5 +#define AIPS_PACRB_SP6_MASK 0x40u +#define AIPS_PACRB_SP6_SHIFT 6 +#define AIPS_PACRB_TP5_MASK 0x100u +#define AIPS_PACRB_TP5_SHIFT 8 +#define AIPS_PACRB_WP5_MASK 0x200u +#define AIPS_PACRB_WP5_SHIFT 9 +#define AIPS_PACRB_SP5_MASK 0x400u +#define AIPS_PACRB_SP5_SHIFT 10 +#define AIPS_PACRB_TP4_MASK 0x1000u +#define AIPS_PACRB_TP4_SHIFT 12 +#define AIPS_PACRB_WP4_MASK 0x2000u +#define AIPS_PACRB_WP4_SHIFT 13 +#define AIPS_PACRB_SP4_MASK 0x4000u +#define AIPS_PACRB_SP4_SHIFT 14 +#define AIPS_PACRB_TP3_MASK 0x10000u +#define AIPS_PACRB_TP3_SHIFT 16 +#define AIPS_PACRB_WP3_MASK 0x20000u +#define AIPS_PACRB_WP3_SHIFT 17 +#define AIPS_PACRB_SP3_MASK 0x40000u +#define AIPS_PACRB_SP3_SHIFT 18 +#define AIPS_PACRB_TP2_MASK 0x100000u +#define AIPS_PACRB_TP2_SHIFT 20 +#define AIPS_PACRB_WP2_MASK 0x200000u +#define AIPS_PACRB_WP2_SHIFT 21 +#define AIPS_PACRB_SP2_MASK 0x400000u +#define AIPS_PACRB_SP2_SHIFT 22 +#define AIPS_PACRB_TP1_MASK 0x1000000u +#define AIPS_PACRB_TP1_SHIFT 24 +#define AIPS_PACRB_WP1_MASK 0x2000000u +#define AIPS_PACRB_WP1_SHIFT 25 +#define AIPS_PACRB_SP1_MASK 0x4000000u +#define AIPS_PACRB_SP1_SHIFT 26 +#define AIPS_PACRB_TP0_MASK 0x10000000u +#define AIPS_PACRB_TP0_SHIFT 28 +#define AIPS_PACRB_WP0_MASK 0x20000000u +#define AIPS_PACRB_WP0_SHIFT 29 +#define AIPS_PACRB_SP0_MASK 0x40000000u +#define AIPS_PACRB_SP0_SHIFT 30 +/* PACRC Bit Fields */ +#define AIPS_PACRC_TP7_MASK 0x1u +#define AIPS_PACRC_TP7_SHIFT 0 +#define AIPS_PACRC_WP7_MASK 0x2u +#define AIPS_PACRC_WP7_SHIFT 1 +#define AIPS_PACRC_SP7_MASK 0x4u +#define AIPS_PACRC_SP7_SHIFT 2 +#define AIPS_PACRC_TP6_MASK 0x10u +#define AIPS_PACRC_TP6_SHIFT 4 +#define AIPS_PACRC_WP6_MASK 0x20u +#define AIPS_PACRC_WP6_SHIFT 5 +#define AIPS_PACRC_SP6_MASK 0x40u +#define AIPS_PACRC_SP6_SHIFT 6 +#define AIPS_PACRC_TP5_MASK 0x100u +#define AIPS_PACRC_TP5_SHIFT 8 +#define AIPS_PACRC_WP5_MASK 0x200u +#define AIPS_PACRC_WP5_SHIFT 9 +#define AIPS_PACRC_SP5_MASK 0x400u +#define AIPS_PACRC_SP5_SHIFT 10 +#define AIPS_PACRC_TP4_MASK 0x1000u +#define AIPS_PACRC_TP4_SHIFT 12 +#define AIPS_PACRC_WP4_MASK 0x2000u +#define AIPS_PACRC_WP4_SHIFT 13 +#define AIPS_PACRC_SP4_MASK 0x4000u +#define AIPS_PACRC_SP4_SHIFT 14 +#define AIPS_PACRC_TP3_MASK 0x10000u +#define AIPS_PACRC_TP3_SHIFT 16 +#define AIPS_PACRC_WP3_MASK 0x20000u +#define AIPS_PACRC_WP3_SHIFT 17 +#define AIPS_PACRC_SP3_MASK 0x40000u +#define AIPS_PACRC_SP3_SHIFT 18 +#define AIPS_PACRC_TP2_MASK 0x100000u +#define AIPS_PACRC_TP2_SHIFT 20 +#define AIPS_PACRC_WP2_MASK 0x200000u +#define AIPS_PACRC_WP2_SHIFT 21 +#define AIPS_PACRC_SP2_MASK 0x400000u +#define AIPS_PACRC_SP2_SHIFT 22 +#define AIPS_PACRC_TP1_MASK 0x1000000u +#define AIPS_PACRC_TP1_SHIFT 24 +#define AIPS_PACRC_WP1_MASK 0x2000000u +#define AIPS_PACRC_WP1_SHIFT 25 +#define AIPS_PACRC_SP1_MASK 0x4000000u +#define AIPS_PACRC_SP1_SHIFT 26 +#define AIPS_PACRC_TP0_MASK 0x10000000u +#define AIPS_PACRC_TP0_SHIFT 28 +#define AIPS_PACRC_WP0_MASK 0x20000000u +#define AIPS_PACRC_WP0_SHIFT 29 +#define AIPS_PACRC_SP0_MASK 0x40000000u +#define AIPS_PACRC_SP0_SHIFT 30 +/* PACRD Bit Fields */ +#define AIPS_PACRD_TP7_MASK 0x1u +#define AIPS_PACRD_TP7_SHIFT 0 +#define AIPS_PACRD_WP7_MASK 0x2u +#define AIPS_PACRD_WP7_SHIFT 1 +#define AIPS_PACRD_SP7_MASK 0x4u +#define AIPS_PACRD_SP7_SHIFT 2 +#define AIPS_PACRD_TP6_MASK 0x10u +#define AIPS_PACRD_TP6_SHIFT 4 +#define AIPS_PACRD_WP6_MASK 0x20u +#define AIPS_PACRD_WP6_SHIFT 5 +#define AIPS_PACRD_SP6_MASK 0x40u +#define AIPS_PACRD_SP6_SHIFT 6 +#define AIPS_PACRD_TP5_MASK 0x100u +#define AIPS_PACRD_TP5_SHIFT 8 +#define AIPS_PACRD_WP5_MASK 0x200u +#define AIPS_PACRD_WP5_SHIFT 9 +#define AIPS_PACRD_SP5_MASK 0x400u +#define AIPS_PACRD_SP5_SHIFT 10 +#define AIPS_PACRD_TP4_MASK 0x1000u +#define AIPS_PACRD_TP4_SHIFT 12 +#define AIPS_PACRD_WP4_MASK 0x2000u +#define AIPS_PACRD_WP4_SHIFT 13 +#define AIPS_PACRD_SP4_MASK 0x4000u +#define AIPS_PACRD_SP4_SHIFT 14 +#define AIPS_PACRD_TP3_MASK 0x10000u +#define AIPS_PACRD_TP3_SHIFT 16 +#define AIPS_PACRD_WP3_MASK 0x20000u +#define AIPS_PACRD_WP3_SHIFT 17 +#define AIPS_PACRD_SP3_MASK 0x40000u +#define AIPS_PACRD_SP3_SHIFT 18 +#define AIPS_PACRD_TP2_MASK 0x100000u +#define AIPS_PACRD_TP2_SHIFT 20 +#define AIPS_PACRD_WP2_MASK 0x200000u +#define AIPS_PACRD_WP2_SHIFT 21 +#define AIPS_PACRD_SP2_MASK 0x400000u +#define AIPS_PACRD_SP2_SHIFT 22 +#define AIPS_PACRD_TP1_MASK 0x1000000u +#define AIPS_PACRD_TP1_SHIFT 24 +#define AIPS_PACRD_WP1_MASK 0x2000000u +#define AIPS_PACRD_WP1_SHIFT 25 +#define AIPS_PACRD_SP1_MASK 0x4000000u +#define AIPS_PACRD_SP1_SHIFT 26 +#define AIPS_PACRD_TP0_MASK 0x10000000u +#define AIPS_PACRD_TP0_SHIFT 28 +#define AIPS_PACRD_WP0_MASK 0x20000000u +#define AIPS_PACRD_WP0_SHIFT 29 +#define AIPS_PACRD_SP0_MASK 0x40000000u +#define AIPS_PACRD_SP0_SHIFT 30 +/* PACRE Bit Fields */ +#define AIPS_PACRE_TP7_MASK 0x1u +#define AIPS_PACRE_TP7_SHIFT 0 +#define AIPS_PACRE_WP7_MASK 0x2u +#define AIPS_PACRE_WP7_SHIFT 1 +#define AIPS_PACRE_SP7_MASK 0x4u +#define AIPS_PACRE_SP7_SHIFT 2 +#define AIPS_PACRE_TP6_MASK 0x10u +#define AIPS_PACRE_TP6_SHIFT 4 +#define AIPS_PACRE_WP6_MASK 0x20u +#define AIPS_PACRE_WP6_SHIFT 5 +#define AIPS_PACRE_SP6_MASK 0x40u +#define AIPS_PACRE_SP6_SHIFT 6 +#define AIPS_PACRE_TP5_MASK 0x100u +#define AIPS_PACRE_TP5_SHIFT 8 +#define AIPS_PACRE_WP5_MASK 0x200u +#define AIPS_PACRE_WP5_SHIFT 9 +#define AIPS_PACRE_SP5_MASK 0x400u +#define AIPS_PACRE_SP5_SHIFT 10 +#define AIPS_PACRE_TP4_MASK 0x1000u +#define AIPS_PACRE_TP4_SHIFT 12 +#define AIPS_PACRE_WP4_MASK 0x2000u +#define AIPS_PACRE_WP4_SHIFT 13 +#define AIPS_PACRE_SP4_MASK 0x4000u +#define AIPS_PACRE_SP4_SHIFT 14 +#define AIPS_PACRE_TP3_MASK 0x10000u +#define AIPS_PACRE_TP3_SHIFT 16 +#define AIPS_PACRE_WP3_MASK 0x20000u +#define AIPS_PACRE_WP3_SHIFT 17 +#define AIPS_PACRE_SP3_MASK 0x40000u +#define AIPS_PACRE_SP3_SHIFT 18 +#define AIPS_PACRE_TP2_MASK 0x100000u +#define AIPS_PACRE_TP2_SHIFT 20 +#define AIPS_PACRE_WP2_MASK 0x200000u +#define AIPS_PACRE_WP2_SHIFT 21 +#define AIPS_PACRE_SP2_MASK 0x400000u +#define AIPS_PACRE_SP2_SHIFT 22 +#define AIPS_PACRE_TP1_MASK 0x1000000u +#define AIPS_PACRE_TP1_SHIFT 24 +#define AIPS_PACRE_WP1_MASK 0x2000000u +#define AIPS_PACRE_WP1_SHIFT 25 +#define AIPS_PACRE_SP1_MASK 0x4000000u +#define AIPS_PACRE_SP1_SHIFT 26 +#define AIPS_PACRE_TP0_MASK 0x10000000u +#define AIPS_PACRE_TP0_SHIFT 28 +#define AIPS_PACRE_WP0_MASK 0x20000000u +#define AIPS_PACRE_WP0_SHIFT 29 +#define AIPS_PACRE_SP0_MASK 0x40000000u +#define AIPS_PACRE_SP0_SHIFT 30 +/* PACRF Bit Fields */ +#define AIPS_PACRF_TP7_MASK 0x1u +#define AIPS_PACRF_TP7_SHIFT 0 +#define AIPS_PACRF_WP7_MASK 0x2u +#define AIPS_PACRF_WP7_SHIFT 1 +#define AIPS_PACRF_SP7_MASK 0x4u +#define AIPS_PACRF_SP7_SHIFT 2 +#define AIPS_PACRF_TP6_MASK 0x10u +#define AIPS_PACRF_TP6_SHIFT 4 +#define AIPS_PACRF_WP6_MASK 0x20u +#define AIPS_PACRF_WP6_SHIFT 5 +#define AIPS_PACRF_SP6_MASK 0x40u +#define AIPS_PACRF_SP6_SHIFT 6 +#define AIPS_PACRF_TP5_MASK 0x100u +#define AIPS_PACRF_TP5_SHIFT 8 +#define AIPS_PACRF_WP5_MASK 0x200u +#define AIPS_PACRF_WP5_SHIFT 9 +#define AIPS_PACRF_SP5_MASK 0x400u +#define AIPS_PACRF_SP5_SHIFT 10 +#define AIPS_PACRF_TP4_MASK 0x1000u +#define AIPS_PACRF_TP4_SHIFT 12 +#define AIPS_PACRF_WP4_MASK 0x2000u +#define AIPS_PACRF_WP4_SHIFT 13 +#define AIPS_PACRF_SP4_MASK 0x4000u +#define AIPS_PACRF_SP4_SHIFT 14 +#define AIPS_PACRF_TP3_MASK 0x10000u +#define AIPS_PACRF_TP3_SHIFT 16 +#define AIPS_PACRF_WP3_MASK 0x20000u +#define AIPS_PACRF_WP3_SHIFT 17 +#define AIPS_PACRF_SP3_MASK 0x40000u +#define AIPS_PACRF_SP3_SHIFT 18 +#define AIPS_PACRF_TP2_MASK 0x100000u +#define AIPS_PACRF_TP2_SHIFT 20 +#define AIPS_PACRF_WP2_MASK 0x200000u +#define AIPS_PACRF_WP2_SHIFT 21 +#define AIPS_PACRF_SP2_MASK 0x400000u +#define AIPS_PACRF_SP2_SHIFT 22 +#define AIPS_PACRF_TP1_MASK 0x1000000u +#define AIPS_PACRF_TP1_SHIFT 24 +#define AIPS_PACRF_WP1_MASK 0x2000000u +#define AIPS_PACRF_WP1_SHIFT 25 +#define AIPS_PACRF_SP1_MASK 0x4000000u +#define AIPS_PACRF_SP1_SHIFT 26 +#define AIPS_PACRF_TP0_MASK 0x10000000u +#define AIPS_PACRF_TP0_SHIFT 28 +#define AIPS_PACRF_WP0_MASK 0x20000000u +#define AIPS_PACRF_WP0_SHIFT 29 +#define AIPS_PACRF_SP0_MASK 0x40000000u +#define AIPS_PACRF_SP0_SHIFT 30 +/* PACRG Bit Fields */ +#define AIPS_PACRG_TP7_MASK 0x1u +#define AIPS_PACRG_TP7_SHIFT 0 +#define AIPS_PACRG_WP7_MASK 0x2u +#define AIPS_PACRG_WP7_SHIFT 1 +#define AIPS_PACRG_SP7_MASK 0x4u +#define AIPS_PACRG_SP7_SHIFT 2 +#define AIPS_PACRG_TP6_MASK 0x10u +#define AIPS_PACRG_TP6_SHIFT 4 +#define AIPS_PACRG_WP6_MASK 0x20u +#define AIPS_PACRG_WP6_SHIFT 5 +#define AIPS_PACRG_SP6_MASK 0x40u +#define AIPS_PACRG_SP6_SHIFT 6 +#define AIPS_PACRG_TP5_MASK 0x100u +#define AIPS_PACRG_TP5_SHIFT 8 +#define AIPS_PACRG_WP5_MASK 0x200u +#define AIPS_PACRG_WP5_SHIFT 9 +#define AIPS_PACRG_SP5_MASK 0x400u +#define AIPS_PACRG_SP5_SHIFT 10 +#define AIPS_PACRG_TP4_MASK 0x1000u +#define AIPS_PACRG_TP4_SHIFT 12 +#define AIPS_PACRG_WP4_MASK 0x2000u +#define AIPS_PACRG_WP4_SHIFT 13 +#define AIPS_PACRG_SP4_MASK 0x4000u +#define AIPS_PACRG_SP4_SHIFT 14 +#define AIPS_PACRG_TP3_MASK 0x10000u +#define AIPS_PACRG_TP3_SHIFT 16 +#define AIPS_PACRG_WP3_MASK 0x20000u +#define AIPS_PACRG_WP3_SHIFT 17 +#define AIPS_PACRG_SP3_MASK 0x40000u +#define AIPS_PACRG_SP3_SHIFT 18 +#define AIPS_PACRG_TP2_MASK 0x100000u +#define AIPS_PACRG_TP2_SHIFT 20 +#define AIPS_PACRG_WP2_MASK 0x200000u +#define AIPS_PACRG_WP2_SHIFT 21 +#define AIPS_PACRG_SP2_MASK 0x400000u +#define AIPS_PACRG_SP2_SHIFT 22 +#define AIPS_PACRG_TP1_MASK 0x1000000u +#define AIPS_PACRG_TP1_SHIFT 24 +#define AIPS_PACRG_WP1_MASK 0x2000000u +#define AIPS_PACRG_WP1_SHIFT 25 +#define AIPS_PACRG_SP1_MASK 0x4000000u +#define AIPS_PACRG_SP1_SHIFT 26 +#define AIPS_PACRG_TP0_MASK 0x10000000u +#define AIPS_PACRG_TP0_SHIFT 28 +#define AIPS_PACRG_WP0_MASK 0x20000000u +#define AIPS_PACRG_WP0_SHIFT 29 +#define AIPS_PACRG_SP0_MASK 0x40000000u +#define AIPS_PACRG_SP0_SHIFT 30 +/* PACRH Bit Fields */ +#define AIPS_PACRH_TP7_MASK 0x1u +#define AIPS_PACRH_TP7_SHIFT 0 +#define AIPS_PACRH_WP7_MASK 0x2u +#define AIPS_PACRH_WP7_SHIFT 1 +#define AIPS_PACRH_SP7_MASK 0x4u +#define AIPS_PACRH_SP7_SHIFT 2 +#define AIPS_PACRH_TP6_MASK 0x10u +#define AIPS_PACRH_TP6_SHIFT 4 +#define AIPS_PACRH_WP6_MASK 0x20u +#define AIPS_PACRH_WP6_SHIFT 5 +#define AIPS_PACRH_SP6_MASK 0x40u +#define AIPS_PACRH_SP6_SHIFT 6 +#define AIPS_PACRH_TP5_MASK 0x100u +#define AIPS_PACRH_TP5_SHIFT 8 +#define AIPS_PACRH_WP5_MASK 0x200u +#define AIPS_PACRH_WP5_SHIFT 9 +#define AIPS_PACRH_SP5_MASK 0x400u +#define AIPS_PACRH_SP5_SHIFT 10 +#define AIPS_PACRH_TP4_MASK 0x1000u +#define AIPS_PACRH_TP4_SHIFT 12 +#define AIPS_PACRH_WP4_MASK 0x2000u +#define AIPS_PACRH_WP4_SHIFT 13 +#define AIPS_PACRH_SP4_MASK 0x4000u +#define AIPS_PACRH_SP4_SHIFT 14 +#define AIPS_PACRH_TP3_MASK 0x10000u +#define AIPS_PACRH_TP3_SHIFT 16 +#define AIPS_PACRH_WP3_MASK 0x20000u +#define AIPS_PACRH_WP3_SHIFT 17 +#define AIPS_PACRH_SP3_MASK 0x40000u +#define AIPS_PACRH_SP3_SHIFT 18 +#define AIPS_PACRH_TP2_MASK 0x100000u +#define AIPS_PACRH_TP2_SHIFT 20 +#define AIPS_PACRH_WP2_MASK 0x200000u +#define AIPS_PACRH_WP2_SHIFT 21 +#define AIPS_PACRH_SP2_MASK 0x400000u +#define AIPS_PACRH_SP2_SHIFT 22 +#define AIPS_PACRH_TP1_MASK 0x1000000u +#define AIPS_PACRH_TP1_SHIFT 24 +#define AIPS_PACRH_WP1_MASK 0x2000000u +#define AIPS_PACRH_WP1_SHIFT 25 +#define AIPS_PACRH_SP1_MASK 0x4000000u +#define AIPS_PACRH_SP1_SHIFT 26 +#define AIPS_PACRH_TP0_MASK 0x10000000u +#define AIPS_PACRH_TP0_SHIFT 28 +#define AIPS_PACRH_WP0_MASK 0x20000000u +#define AIPS_PACRH_WP0_SHIFT 29 +#define AIPS_PACRH_SP0_MASK 0x40000000u +#define AIPS_PACRH_SP0_SHIFT 30 +/* PACRI Bit Fields */ +#define AIPS_PACRI_TP7_MASK 0x1u +#define AIPS_PACRI_TP7_SHIFT 0 +#define AIPS_PACRI_WP7_MASK 0x2u +#define AIPS_PACRI_WP7_SHIFT 1 +#define AIPS_PACRI_SP7_MASK 0x4u +#define AIPS_PACRI_SP7_SHIFT 2 +#define AIPS_PACRI_TP6_MASK 0x10u +#define AIPS_PACRI_TP6_SHIFT 4 +#define AIPS_PACRI_WP6_MASK 0x20u +#define AIPS_PACRI_WP6_SHIFT 5 +#define AIPS_PACRI_SP6_MASK 0x40u +#define AIPS_PACRI_SP6_SHIFT 6 +#define AIPS_PACRI_TP5_MASK 0x100u +#define AIPS_PACRI_TP5_SHIFT 8 +#define AIPS_PACRI_WP5_MASK 0x200u +#define AIPS_PACRI_WP5_SHIFT 9 +#define AIPS_PACRI_SP5_MASK 0x400u +#define AIPS_PACRI_SP5_SHIFT 10 +#define AIPS_PACRI_TP4_MASK 0x1000u +#define AIPS_PACRI_TP4_SHIFT 12 +#define AIPS_PACRI_WP4_MASK 0x2000u +#define AIPS_PACRI_WP4_SHIFT 13 +#define AIPS_PACRI_SP4_MASK 0x4000u +#define AIPS_PACRI_SP4_SHIFT 14 +#define AIPS_PACRI_TP3_MASK 0x10000u +#define AIPS_PACRI_TP3_SHIFT 16 +#define AIPS_PACRI_WP3_MASK 0x20000u +#define AIPS_PACRI_WP3_SHIFT 17 +#define AIPS_PACRI_SP3_MASK 0x40000u +#define AIPS_PACRI_SP3_SHIFT 18 +#define AIPS_PACRI_TP2_MASK 0x100000u +#define AIPS_PACRI_TP2_SHIFT 20 +#define AIPS_PACRI_WP2_MASK 0x200000u +#define AIPS_PACRI_WP2_SHIFT 21 +#define AIPS_PACRI_SP2_MASK 0x400000u +#define AIPS_PACRI_SP2_SHIFT 22 +#define AIPS_PACRI_TP1_MASK 0x1000000u +#define AIPS_PACRI_TP1_SHIFT 24 +#define AIPS_PACRI_WP1_MASK 0x2000000u +#define AIPS_PACRI_WP1_SHIFT 25 +#define AIPS_PACRI_SP1_MASK 0x4000000u +#define AIPS_PACRI_SP1_SHIFT 26 +#define AIPS_PACRI_TP0_MASK 0x10000000u +#define AIPS_PACRI_TP0_SHIFT 28 +#define AIPS_PACRI_WP0_MASK 0x20000000u +#define AIPS_PACRI_WP0_SHIFT 29 +#define AIPS_PACRI_SP0_MASK 0x40000000u +#define AIPS_PACRI_SP0_SHIFT 30 +/* PACRJ Bit Fields */ +#define AIPS_PACRJ_TP7_MASK 0x1u +#define AIPS_PACRJ_TP7_SHIFT 0 +#define AIPS_PACRJ_WP7_MASK 0x2u +#define AIPS_PACRJ_WP7_SHIFT 1 +#define AIPS_PACRJ_SP7_MASK 0x4u +#define AIPS_PACRJ_SP7_SHIFT 2 +#define AIPS_PACRJ_TP6_MASK 0x10u +#define AIPS_PACRJ_TP6_SHIFT 4 +#define AIPS_PACRJ_WP6_MASK 0x20u +#define AIPS_PACRJ_WP6_SHIFT 5 +#define AIPS_PACRJ_SP6_MASK 0x40u +#define AIPS_PACRJ_SP6_SHIFT 6 +#define AIPS_PACRJ_TP5_MASK 0x100u +#define AIPS_PACRJ_TP5_SHIFT 8 +#define AIPS_PACRJ_WP5_MASK 0x200u +#define AIPS_PACRJ_WP5_SHIFT 9 +#define AIPS_PACRJ_SP5_MASK 0x400u +#define AIPS_PACRJ_SP5_SHIFT 10 +#define AIPS_PACRJ_TP4_MASK 0x1000u +#define AIPS_PACRJ_TP4_SHIFT 12 +#define AIPS_PACRJ_WP4_MASK 0x2000u +#define AIPS_PACRJ_WP4_SHIFT 13 +#define AIPS_PACRJ_SP4_MASK 0x4000u +#define AIPS_PACRJ_SP4_SHIFT 14 +#define AIPS_PACRJ_TP3_MASK 0x10000u +#define AIPS_PACRJ_TP3_SHIFT 16 +#define AIPS_PACRJ_WP3_MASK 0x20000u +#define AIPS_PACRJ_WP3_SHIFT 17 +#define AIPS_PACRJ_SP3_MASK 0x40000u +#define AIPS_PACRJ_SP3_SHIFT 18 +#define AIPS_PACRJ_TP2_MASK 0x100000u +#define AIPS_PACRJ_TP2_SHIFT 20 +#define AIPS_PACRJ_WP2_MASK 0x200000u +#define AIPS_PACRJ_WP2_SHIFT 21 +#define AIPS_PACRJ_SP2_MASK 0x400000u +#define AIPS_PACRJ_SP2_SHIFT 22 +#define AIPS_PACRJ_TP1_MASK 0x1000000u +#define AIPS_PACRJ_TP1_SHIFT 24 +#define AIPS_PACRJ_WP1_MASK 0x2000000u +#define AIPS_PACRJ_WP1_SHIFT 25 +#define AIPS_PACRJ_SP1_MASK 0x4000000u +#define AIPS_PACRJ_SP1_SHIFT 26 +#define AIPS_PACRJ_TP0_MASK 0x10000000u +#define AIPS_PACRJ_TP0_SHIFT 28 +#define AIPS_PACRJ_WP0_MASK 0x20000000u +#define AIPS_PACRJ_WP0_SHIFT 29 +#define AIPS_PACRJ_SP0_MASK 0x40000000u +#define AIPS_PACRJ_SP0_SHIFT 30 +/* PACRK Bit Fields */ +#define AIPS_PACRK_TP7_MASK 0x1u +#define AIPS_PACRK_TP7_SHIFT 0 +#define AIPS_PACRK_WP7_MASK 0x2u +#define AIPS_PACRK_WP7_SHIFT 1 +#define AIPS_PACRK_SP7_MASK 0x4u +#define AIPS_PACRK_SP7_SHIFT 2 +#define AIPS_PACRK_TP6_MASK 0x10u +#define AIPS_PACRK_TP6_SHIFT 4 +#define AIPS_PACRK_WP6_MASK 0x20u +#define AIPS_PACRK_WP6_SHIFT 5 +#define AIPS_PACRK_SP6_MASK 0x40u +#define AIPS_PACRK_SP6_SHIFT 6 +#define AIPS_PACRK_TP5_MASK 0x100u +#define AIPS_PACRK_TP5_SHIFT 8 +#define AIPS_PACRK_WP5_MASK 0x200u +#define AIPS_PACRK_WP5_SHIFT 9 +#define AIPS_PACRK_SP5_MASK 0x400u +#define AIPS_PACRK_SP5_SHIFT 10 +#define AIPS_PACRK_TP4_MASK 0x1000u +#define AIPS_PACRK_TP4_SHIFT 12 +#define AIPS_PACRK_WP4_MASK 0x2000u +#define AIPS_PACRK_WP4_SHIFT 13 +#define AIPS_PACRK_SP4_MASK 0x4000u +#define AIPS_PACRK_SP4_SHIFT 14 +#define AIPS_PACRK_TP3_MASK 0x10000u +#define AIPS_PACRK_TP3_SHIFT 16 +#define AIPS_PACRK_WP3_MASK 0x20000u +#define AIPS_PACRK_WP3_SHIFT 17 +#define AIPS_PACRK_SP3_MASK 0x40000u +#define AIPS_PACRK_SP3_SHIFT 18 +#define AIPS_PACRK_TP2_MASK 0x100000u +#define AIPS_PACRK_TP2_SHIFT 20 +#define AIPS_PACRK_WP2_MASK 0x200000u +#define AIPS_PACRK_WP2_SHIFT 21 +#define AIPS_PACRK_SP2_MASK 0x400000u +#define AIPS_PACRK_SP2_SHIFT 22 +#define AIPS_PACRK_TP1_MASK 0x1000000u +#define AIPS_PACRK_TP1_SHIFT 24 +#define AIPS_PACRK_WP1_MASK 0x2000000u +#define AIPS_PACRK_WP1_SHIFT 25 +#define AIPS_PACRK_SP1_MASK 0x4000000u +#define AIPS_PACRK_SP1_SHIFT 26 +#define AIPS_PACRK_TP0_MASK 0x10000000u +#define AIPS_PACRK_TP0_SHIFT 28 +#define AIPS_PACRK_WP0_MASK 0x20000000u +#define AIPS_PACRK_WP0_SHIFT 29 +#define AIPS_PACRK_SP0_MASK 0x40000000u +#define AIPS_PACRK_SP0_SHIFT 30 +/* PACRL Bit Fields */ +#define AIPS_PACRL_TP7_MASK 0x1u +#define AIPS_PACRL_TP7_SHIFT 0 +#define AIPS_PACRL_WP7_MASK 0x2u +#define AIPS_PACRL_WP7_SHIFT 1 +#define AIPS_PACRL_SP7_MASK 0x4u +#define AIPS_PACRL_SP7_SHIFT 2 +#define AIPS_PACRL_TP6_MASK 0x10u +#define AIPS_PACRL_TP6_SHIFT 4 +#define AIPS_PACRL_WP6_MASK 0x20u +#define AIPS_PACRL_WP6_SHIFT 5 +#define AIPS_PACRL_SP6_MASK 0x40u +#define AIPS_PACRL_SP6_SHIFT 6 +#define AIPS_PACRL_TP5_MASK 0x100u +#define AIPS_PACRL_TP5_SHIFT 8 +#define AIPS_PACRL_WP5_MASK 0x200u +#define AIPS_PACRL_WP5_SHIFT 9 +#define AIPS_PACRL_SP5_MASK 0x400u +#define AIPS_PACRL_SP5_SHIFT 10 +#define AIPS_PACRL_TP4_MASK 0x1000u +#define AIPS_PACRL_TP4_SHIFT 12 +#define AIPS_PACRL_WP4_MASK 0x2000u +#define AIPS_PACRL_WP4_SHIFT 13 +#define AIPS_PACRL_SP4_MASK 0x4000u +#define AIPS_PACRL_SP4_SHIFT 14 +#define AIPS_PACRL_TP3_MASK 0x10000u +#define AIPS_PACRL_TP3_SHIFT 16 +#define AIPS_PACRL_WP3_MASK 0x20000u +#define AIPS_PACRL_WP3_SHIFT 17 +#define AIPS_PACRL_SP3_MASK 0x40000u +#define AIPS_PACRL_SP3_SHIFT 18 +#define AIPS_PACRL_TP2_MASK 0x100000u +#define AIPS_PACRL_TP2_SHIFT 20 +#define AIPS_PACRL_WP2_MASK 0x200000u +#define AIPS_PACRL_WP2_SHIFT 21 +#define AIPS_PACRL_SP2_MASK 0x400000u +#define AIPS_PACRL_SP2_SHIFT 22 +#define AIPS_PACRL_TP1_MASK 0x1000000u +#define AIPS_PACRL_TP1_SHIFT 24 +#define AIPS_PACRL_WP1_MASK 0x2000000u +#define AIPS_PACRL_WP1_SHIFT 25 +#define AIPS_PACRL_SP1_MASK 0x4000000u +#define AIPS_PACRL_SP1_SHIFT 26 +#define AIPS_PACRL_TP0_MASK 0x10000000u +#define AIPS_PACRL_TP0_SHIFT 28 +#define AIPS_PACRL_WP0_MASK 0x20000000u +#define AIPS_PACRL_WP0_SHIFT 29 +#define AIPS_PACRL_SP0_MASK 0x40000000u +#define AIPS_PACRL_SP0_SHIFT 30 +/* PACRM Bit Fields */ +#define AIPS_PACRM_TP7_MASK 0x1u +#define AIPS_PACRM_TP7_SHIFT 0 +#define AIPS_PACRM_WP7_MASK 0x2u +#define AIPS_PACRM_WP7_SHIFT 1 +#define AIPS_PACRM_SP7_MASK 0x4u +#define AIPS_PACRM_SP7_SHIFT 2 +#define AIPS_PACRM_TP6_MASK 0x10u +#define AIPS_PACRM_TP6_SHIFT 4 +#define AIPS_PACRM_WP6_MASK 0x20u +#define AIPS_PACRM_WP6_SHIFT 5 +#define AIPS_PACRM_SP6_MASK 0x40u +#define AIPS_PACRM_SP6_SHIFT 6 +#define AIPS_PACRM_TP5_MASK 0x100u +#define AIPS_PACRM_TP5_SHIFT 8 +#define AIPS_PACRM_WP5_MASK 0x200u +#define AIPS_PACRM_WP5_SHIFT 9 +#define AIPS_PACRM_SP5_MASK 0x400u +#define AIPS_PACRM_SP5_SHIFT 10 +#define AIPS_PACRM_TP4_MASK 0x1000u +#define AIPS_PACRM_TP4_SHIFT 12 +#define AIPS_PACRM_WP4_MASK 0x2000u +#define AIPS_PACRM_WP4_SHIFT 13 +#define AIPS_PACRM_SP4_MASK 0x4000u +#define AIPS_PACRM_SP4_SHIFT 14 +#define AIPS_PACRM_TP3_MASK 0x10000u +#define AIPS_PACRM_TP3_SHIFT 16 +#define AIPS_PACRM_WP3_MASK 0x20000u +#define AIPS_PACRM_WP3_SHIFT 17 +#define AIPS_PACRM_SP3_MASK 0x40000u +#define AIPS_PACRM_SP3_SHIFT 18 +#define AIPS_PACRM_TP2_MASK 0x100000u +#define AIPS_PACRM_TP2_SHIFT 20 +#define AIPS_PACRM_WP2_MASK 0x200000u +#define AIPS_PACRM_WP2_SHIFT 21 +#define AIPS_PACRM_SP2_MASK 0x400000u +#define AIPS_PACRM_SP2_SHIFT 22 +#define AIPS_PACRM_TP1_MASK 0x1000000u +#define AIPS_PACRM_TP1_SHIFT 24 +#define AIPS_PACRM_WP1_MASK 0x2000000u +#define AIPS_PACRM_WP1_SHIFT 25 +#define AIPS_PACRM_SP1_MASK 0x4000000u +#define AIPS_PACRM_SP1_SHIFT 26 +#define AIPS_PACRM_TP0_MASK 0x10000000u +#define AIPS_PACRM_TP0_SHIFT 28 +#define AIPS_PACRM_WP0_MASK 0x20000000u +#define AIPS_PACRM_WP0_SHIFT 29 +#define AIPS_PACRM_SP0_MASK 0x40000000u +#define AIPS_PACRM_SP0_SHIFT 30 +/* PACRN Bit Fields */ +#define AIPS_PACRN_TP7_MASK 0x1u +#define AIPS_PACRN_TP7_SHIFT 0 +#define AIPS_PACRN_WP7_MASK 0x2u +#define AIPS_PACRN_WP7_SHIFT 1 +#define AIPS_PACRN_SP7_MASK 0x4u +#define AIPS_PACRN_SP7_SHIFT 2 +#define AIPS_PACRN_TP6_MASK 0x10u +#define AIPS_PACRN_TP6_SHIFT 4 +#define AIPS_PACRN_WP6_MASK 0x20u +#define AIPS_PACRN_WP6_SHIFT 5 +#define AIPS_PACRN_SP6_MASK 0x40u +#define AIPS_PACRN_SP6_SHIFT 6 +#define AIPS_PACRN_TP5_MASK 0x100u +#define AIPS_PACRN_TP5_SHIFT 8 +#define AIPS_PACRN_WP5_MASK 0x200u +#define AIPS_PACRN_WP5_SHIFT 9 +#define AIPS_PACRN_SP5_MASK 0x400u +#define AIPS_PACRN_SP5_SHIFT 10 +#define AIPS_PACRN_TP4_MASK 0x1000u +#define AIPS_PACRN_TP4_SHIFT 12 +#define AIPS_PACRN_WP4_MASK 0x2000u +#define AIPS_PACRN_WP4_SHIFT 13 +#define AIPS_PACRN_SP4_MASK 0x4000u +#define AIPS_PACRN_SP4_SHIFT 14 +#define AIPS_PACRN_TP3_MASK 0x10000u +#define AIPS_PACRN_TP3_SHIFT 16 +#define AIPS_PACRN_WP3_MASK 0x20000u +#define AIPS_PACRN_WP3_SHIFT 17 +#define AIPS_PACRN_SP3_MASK 0x40000u +#define AIPS_PACRN_SP3_SHIFT 18 +#define AIPS_PACRN_TP2_MASK 0x100000u +#define AIPS_PACRN_TP2_SHIFT 20 +#define AIPS_PACRN_WP2_MASK 0x200000u +#define AIPS_PACRN_WP2_SHIFT 21 +#define AIPS_PACRN_SP2_MASK 0x400000u +#define AIPS_PACRN_SP2_SHIFT 22 +#define AIPS_PACRN_TP1_MASK 0x1000000u +#define AIPS_PACRN_TP1_SHIFT 24 +#define AIPS_PACRN_WP1_MASK 0x2000000u +#define AIPS_PACRN_WP1_SHIFT 25 +#define AIPS_PACRN_SP1_MASK 0x4000000u +#define AIPS_PACRN_SP1_SHIFT 26 +#define AIPS_PACRN_TP0_MASK 0x10000000u +#define AIPS_PACRN_TP0_SHIFT 28 +#define AIPS_PACRN_WP0_MASK 0x20000000u +#define AIPS_PACRN_WP0_SHIFT 29 +#define AIPS_PACRN_SP0_MASK 0x40000000u +#define AIPS_PACRN_SP0_SHIFT 30 +/* PACRO Bit Fields */ +#define AIPS_PACRO_TP7_MASK 0x1u +#define AIPS_PACRO_TP7_SHIFT 0 +#define AIPS_PACRO_WP7_MASK 0x2u +#define AIPS_PACRO_WP7_SHIFT 1 +#define AIPS_PACRO_SP7_MASK 0x4u +#define AIPS_PACRO_SP7_SHIFT 2 +#define AIPS_PACRO_TP6_MASK 0x10u +#define AIPS_PACRO_TP6_SHIFT 4 +#define AIPS_PACRO_WP6_MASK 0x20u +#define AIPS_PACRO_WP6_SHIFT 5 +#define AIPS_PACRO_SP6_MASK 0x40u +#define AIPS_PACRO_SP6_SHIFT 6 +#define AIPS_PACRO_TP5_MASK 0x100u +#define AIPS_PACRO_TP5_SHIFT 8 +#define AIPS_PACRO_WP5_MASK 0x200u +#define AIPS_PACRO_WP5_SHIFT 9 +#define AIPS_PACRO_SP5_MASK 0x400u +#define AIPS_PACRO_SP5_SHIFT 10 +#define AIPS_PACRO_TP4_MASK 0x1000u +#define AIPS_PACRO_TP4_SHIFT 12 +#define AIPS_PACRO_WP4_MASK 0x2000u +#define AIPS_PACRO_WP4_SHIFT 13 +#define AIPS_PACRO_SP4_MASK 0x4000u +#define AIPS_PACRO_SP4_SHIFT 14 +#define AIPS_PACRO_TP3_MASK 0x10000u +#define AIPS_PACRO_TP3_SHIFT 16 +#define AIPS_PACRO_WP3_MASK 0x20000u +#define AIPS_PACRO_WP3_SHIFT 17 +#define AIPS_PACRO_SP3_MASK 0x40000u +#define AIPS_PACRO_SP3_SHIFT 18 +#define AIPS_PACRO_TP2_MASK 0x100000u +#define AIPS_PACRO_TP2_SHIFT 20 +#define AIPS_PACRO_WP2_MASK 0x200000u +#define AIPS_PACRO_WP2_SHIFT 21 +#define AIPS_PACRO_SP2_MASK 0x400000u +#define AIPS_PACRO_SP2_SHIFT 22 +#define AIPS_PACRO_TP1_MASK 0x1000000u +#define AIPS_PACRO_TP1_SHIFT 24 +#define AIPS_PACRO_WP1_MASK 0x2000000u +#define AIPS_PACRO_WP1_SHIFT 25 +#define AIPS_PACRO_SP1_MASK 0x4000000u +#define AIPS_PACRO_SP1_SHIFT 26 +#define AIPS_PACRO_TP0_MASK 0x10000000u +#define AIPS_PACRO_TP0_SHIFT 28 +#define AIPS_PACRO_WP0_MASK 0x20000000u +#define AIPS_PACRO_WP0_SHIFT 29 +#define AIPS_PACRO_SP0_MASK 0x40000000u +#define AIPS_PACRO_SP0_SHIFT 30 +/* PACRP Bit Fields */ +#define AIPS_PACRP_TP7_MASK 0x1u +#define AIPS_PACRP_TP7_SHIFT 0 +#define AIPS_PACRP_WP7_MASK 0x2u +#define AIPS_PACRP_WP7_SHIFT 1 +#define AIPS_PACRP_SP7_MASK 0x4u +#define AIPS_PACRP_SP7_SHIFT 2 +#define AIPS_PACRP_TP6_MASK 0x10u +#define AIPS_PACRP_TP6_SHIFT 4 +#define AIPS_PACRP_WP6_MASK 0x20u +#define AIPS_PACRP_WP6_SHIFT 5 +#define AIPS_PACRP_SP6_MASK 0x40u +#define AIPS_PACRP_SP6_SHIFT 6 +#define AIPS_PACRP_TP5_MASK 0x100u +#define AIPS_PACRP_TP5_SHIFT 8 +#define AIPS_PACRP_WP5_MASK 0x200u +#define AIPS_PACRP_WP5_SHIFT 9 +#define AIPS_PACRP_SP5_MASK 0x400u +#define AIPS_PACRP_SP5_SHIFT 10 +#define AIPS_PACRP_TP4_MASK 0x1000u +#define AIPS_PACRP_TP4_SHIFT 12 +#define AIPS_PACRP_WP4_MASK 0x2000u +#define AIPS_PACRP_WP4_SHIFT 13 +#define AIPS_PACRP_SP4_MASK 0x4000u +#define AIPS_PACRP_SP4_SHIFT 14 +#define AIPS_PACRP_TP3_MASK 0x10000u +#define AIPS_PACRP_TP3_SHIFT 16 +#define AIPS_PACRP_WP3_MASK 0x20000u +#define AIPS_PACRP_WP3_SHIFT 17 +#define AIPS_PACRP_SP3_MASK 0x40000u +#define AIPS_PACRP_SP3_SHIFT 18 +#define AIPS_PACRP_TP2_MASK 0x100000u +#define AIPS_PACRP_TP2_SHIFT 20 +#define AIPS_PACRP_WP2_MASK 0x200000u +#define AIPS_PACRP_WP2_SHIFT 21 +#define AIPS_PACRP_SP2_MASK 0x400000u +#define AIPS_PACRP_SP2_SHIFT 22 +#define AIPS_PACRP_TP1_MASK 0x1000000u +#define AIPS_PACRP_TP1_SHIFT 24 +#define AIPS_PACRP_WP1_MASK 0x2000000u +#define AIPS_PACRP_WP1_SHIFT 25 +#define AIPS_PACRP_SP1_MASK 0x4000000u +#define AIPS_PACRP_SP1_SHIFT 26 +#define AIPS_PACRP_TP0_MASK 0x10000000u +#define AIPS_PACRP_TP0_SHIFT 28 +#define AIPS_PACRP_WP0_MASK 0x20000000u +#define AIPS_PACRP_WP0_SHIFT 29 +#define AIPS_PACRP_SP0_MASK 0x40000000u +#define AIPS_PACRP_SP0_SHIFT 30 + +/*! + * @} + */ /* end of group AIPS_Register_Masks */ + + +/* AIPS - Peripheral instance base addresses */ +/** Peripheral AIPS0 base address */ +#define AIPS0_BASE (0x40000000u) +/** Peripheral AIPS0 base pointer */ +#define AIPS0 ((AIPS_Type *)AIPS0_BASE) +#define AIPS0_BASE_PTR (AIPS0) +/** Peripheral AIPS1 base address */ +#define AIPS1_BASE (0x40080000u) +/** Peripheral AIPS1 base pointer */ +#define AIPS1 ((AIPS_Type *)AIPS1_BASE) +#define AIPS1_BASE_PTR (AIPS1) +/** Array initializer of AIPS peripheral base addresses */ +#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } +/** Array initializer of AIPS peripheral base pointers */ +#define AIPS_BASE_PTRS { AIPS0, AIPS1 } + +/* ---------------------------------------------------------------------------- + -- AIPS - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros + * @{ + */ + + +/* AIPS - Register instance definitions */ +/* AIPS0 */ +#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0) +#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0) +#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0) +#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0) +#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0) +#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0) +#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0) +#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0) +#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0) +#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0) +#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0) +#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0) +#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0) +#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0) +#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0) +#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0) +#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0) +/* AIPS1 */ +#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1) +#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1) +#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1) +#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1) +#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1) +#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1) +#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1) +#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1) +#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1) +#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1) +#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1) +#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1) +#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1) +#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1) +#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1) +#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1) +#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1) + +/*! + * @} + */ /* end of group AIPS_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group AIPS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AXBS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer + * @{ + */ + +/** AXBS - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x100 */ + __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ + uint8_t RESERVED_1[236]; + } SLAVE[5]; + uint8_t RESERVED_0[768]; + __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ + uint8_t RESERVED_1[252]; + __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ + uint8_t RESERVED_2[252]; + __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ + uint8_t RESERVED_3[252]; + __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ + uint8_t RESERVED_4[252]; + __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ + uint8_t RESERVED_5[252]; + __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ +} AXBS_Type, *AXBS_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- AXBS - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros + * @{ + */ + + +/* AXBS - Register accessors */ +#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) +#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) +#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) +#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) +#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) +#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3) +#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) +#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) + +/*! + * @} + */ /* end of group AXBS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- AXBS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Register_Masks AXBS Register Masks + * @{ + */ + +/* PRS Bit Fields */ +#define AXBS_PRS_M0_MASK 0x7u +#define AXBS_PRS_M0_SHIFT 0 +#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define CAN_CTRL1_REG(base) ((base)->CTRL1) +#define CAN_TIMER_REG(base) ((base)->TIMER) +#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) +#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) +#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) +#define CAN_ECR_REG(base) ((base)->ECR) +#define CAN_ESR1_REG(base) ((base)->ESR1) +#define CAN_IMASK1_REG(base) ((base)->IMASK1) +#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) +#define CAN_CTRL2_REG(base) ((base)->CTRL2) +#define CAN_ESR2_REG(base) ((base)->ESR2) +#define CAN_CRCR_REG(base) ((base)->CRCR) +#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) +#define CAN_RXFIR_REG(base) ((base)->RXFIR) +#define CAN_CS_REG(base,index) ((base)->MB[index].CS) +#define CAN_ID_REG(base,index) ((base)->MB[index].ID) +#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) +#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) +#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) + +/*! + * @} + */ /* end of group CAN_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define CAN_MCR_MAXMB_MASK 0x7Fu +#define CAN_MCR_MAXMB_SHIFT 0 +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<DIRECT[index]) +#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR) +#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA) +#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index]) +#define CAU_STR_CASR_REG(base) ((base)->STR_CASR) +#define CAU_STR_CAA_REG(base) ((base)->STR_CAA) +#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index]) +#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR) +#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA) +#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index]) +#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR) +#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA) +#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index]) +#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR) +#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA) +#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index]) +#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR) +#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA) +#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index]) +#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR) +#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA) +#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index]) +#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR) +#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA) +#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index]) + +/*! + * @} + */ /* end of group CAU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CAU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAU_Register_Masks CAU Register Masks + * @{ + */ + +/* DIRECT Bit Fields */ +#define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu +#define CAU_DIRECT_CAU_DIRECT0_SHIFT 0 +#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<CR0) +#define CMP_CR1_REG(base) ((base)->CR1) +#define CMP_FPR_REG(base) ((base)->FPR) +#define CMP_SCR_REG(base) ((base)->SCR) +#define CMP_DACCR_REG(base) ((base)->DACCR) +#define CMP_MUXCR_REG(base) ((base)->MUXCR) + +/*! + * @} + */ /* end of group CMP_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/* CR0 Bit Fields */ +#define CMP_CR0_HYSTCTR_MASK 0x3u +#define CMP_CR0_HYSTCTR_SHIFT 0 +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<CGH1) +#define CMT_CGL1_REG(base) ((base)->CGL1) +#define CMT_CGH2_REG(base) ((base)->CGH2) +#define CMT_CGL2_REG(base) ((base)->CGL2) +#define CMT_OC_REG(base) ((base)->OC) +#define CMT_MSC_REG(base) ((base)->MSC) +#define CMT_CMD1_REG(base) ((base)->CMD1) +#define CMT_CMD2_REG(base) ((base)->CMD2) +#define CMT_CMD3_REG(base) ((base)->CMD3) +#define CMT_CMD4_REG(base) ((base)->CMD4) +#define CMT_PPS_REG(base) ((base)->PPS) +#define CMT_DMA_REG(base) ((base)->DMA) + +/*! + * @} + */ /* end of group CMT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CMT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMT_Register_Masks CMT Register Masks + * @{ + */ + +/* CGH1 Bit Fields */ +#define CMT_CGH1_PH_MASK 0xFFu +#define CMT_CGH1_PH_SHIFT 0 +#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.CRCL) +#define CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH) +#define CRC_CRC_REG(base) ((base)->CRC) +#define CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL) +#define CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU) +#define CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL) +#define CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU) +#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) +#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) +#define CRC_GPOLY_REG(base) ((base)->GPOLY) +#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) +#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) +#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) +#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) +#define CRC_CTRL_REG(base) ((base)->CTRL) +#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) + +/*! + * @} + */ /* end of group CRC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/* CRCL Bit Fields */ +#define CRC_CRCL_CRCL_MASK 0xFFFFu +#define CRC_CRCL_CRCL_SHIFT 0 +#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) +#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) +#define DAC_SR_REG(base) ((base)->SR) +#define DAC_C0_REG(base) ((base)->C0) +#define DAC_C1_REG(base) ((base)->C1) +#define DAC_C2_REG(base) ((base)->C2) + +/*! + * @} + */ /* end of group DAC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DAC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Register_Masks DAC Register Masks + * @{ + */ + +/* DATL Bit Fields */ +#define DAC_DATL_DATA0_MASK 0xFFu +#define DAC_DATL_DATA0_SHIFT 0 +#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) +#define DMA_ES_REG(base) ((base)->ES) +#define DMA_ERQ_REG(base) ((base)->ERQ) +#define DMA_EEI_REG(base) ((base)->EEI) +#define DMA_CEEI_REG(base) ((base)->CEEI) +#define DMA_SEEI_REG(base) ((base)->SEEI) +#define DMA_CERQ_REG(base) ((base)->CERQ) +#define DMA_SERQ_REG(base) ((base)->SERQ) +#define DMA_CDNE_REG(base) ((base)->CDNE) +#define DMA_SSRT_REG(base) ((base)->SSRT) +#define DMA_CERR_REG(base) ((base)->CERR) +#define DMA_CINT_REG(base) ((base)->CINT) +#define DMA_INT_REG(base) ((base)->INT) +#define DMA_ERR_REG(base) ((base)->ERR) +#define DMA_HRS_REG(base) ((base)->HRS) +#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) +#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) +#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) +#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) +#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) +#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) +#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) +#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) +#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) +#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) +#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) +#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) +#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) +#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) +#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) +#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) +#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) +#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) +#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) +#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) +#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) +#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) +#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) +#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) +#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) +#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) +#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) +#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) +#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) +#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) +#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) + +/*! + * @} + */ /* end of group DMA_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define DMA_CR_EDBG_MASK 0x2u +#define DMA_CR_EDBG_SHIFT 1 +#define DMA_CR_ERCA_MASK 0x4u +#define DMA_CR_ERCA_SHIFT 2 +#define DMA_CR_HOE_MASK 0x10u +#define DMA_CR_HOE_SHIFT 4 +#define DMA_CR_HALT_MASK 0x20u +#define DMA_CR_HALT_SHIFT 5 +#define DMA_CR_CLM_MASK 0x40u +#define DMA_CR_CLM_SHIFT 6 +#define DMA_CR_EMLM_MASK 0x80u +#define DMA_CR_EMLM_SHIFT 7 +#define DMA_CR_ECX_MASK 0x10000u +#define DMA_CR_ECX_SHIFT 16 +#define DMA_CR_CX_MASK 0x20000u +#define DMA_CR_CX_SHIFT 17 +/* ES Bit Fields */ +#define DMA_ES_DBE_MASK 0x1u +#define DMA_ES_DBE_SHIFT 0 +#define DMA_ES_SBE_MASK 0x2u +#define DMA_ES_SBE_SHIFT 1 +#define DMA_ES_SGE_MASK 0x4u +#define DMA_ES_SGE_SHIFT 2 +#define DMA_ES_NCE_MASK 0x8u +#define DMA_ES_NCE_SHIFT 3 +#define DMA_ES_DOE_MASK 0x10u +#define DMA_ES_DOE_SHIFT 4 +#define DMA_ES_DAE_MASK 0x20u +#define DMA_ES_DAE_SHIFT 5 +#define DMA_ES_SOE_MASK 0x40u +#define DMA_ES_SOE_SHIFT 6 +#define DMA_ES_SAE_MASK 0x80u +#define DMA_ES_SAE_SHIFT 7 +#define DMA_ES_ERRCHN_MASK 0xF00u +#define DMA_ES_ERRCHN_SHIFT 8 +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) + +/*! + * @} + */ /* end of group DMAMUX_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/* CHCFG Bit Fields */ +#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu +#define DMAMUX_CHCFG_SOURCE_SHIFT 0 +#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))< MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */ + __IO uint32_t RMON_T_FRAG; /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */ + __IO uint32_t RMON_T_JAB; /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */ + __IO uint32_t RMON_T_COL; /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */ + __IO uint32_t RMON_T_P64; /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */ + __IO uint32_t RMON_T_P65TO127; /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */ + __IO uint32_t RMON_T_P128TO255; /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */ + __IO uint32_t RMON_T_P256TO511; /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */ + __IO uint32_t RMON_T_P512TO1023; /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */ + __IO uint32_t RMON_T_P1024TO2047; /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */ + __IO uint32_t RMON_T_P_GTE2048; /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */ + __IO uint32_t IEEE_T_DROP; /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */ + __IO uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */ + __IO uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */ + __IO uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */ + __IO uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */ + __IO uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */ + __IO uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */ + __IO uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */ + __IO uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */ + __IO uint32_t IEEE_T_SQE; /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */ + __IO uint32_t IEEE_T_FDXFC; /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */ + uint8_t RESERVED_14[12]; + __IO uint32_t RMON_R_PACKETS; /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */ + __IO uint32_t RMON_R_BC_PKT; /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */ + __IO uint32_t RMON_R_MC_PKT; /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */ + __IO uint32_t RMON_R_CRC_ALIGN; /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */ + __IO uint32_t RMON_R_UNDERSIZE; /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */ + __IO uint32_t RMON_R_OVERSIZE; /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */ + __IO uint32_t RMON_R_FRAG; /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */ + __IO uint32_t RMON_R_JAB; /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */ + __IO uint32_t RMON_R_RESVD_0; /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */ + __IO uint32_t RMON_R_P64; /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */ + __IO uint32_t RMON_R_P65TO127; /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */ + __IO uint32_t RMON_R_P128TO255; /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */ + __IO uint32_t RMON_R_P256TO511; /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */ + __IO uint32_t RMON_R_P512TO1023; /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */ + __IO uint32_t RMON_R_P1024TO2047; /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */ + __IO uint32_t RMON_R_P_GTE2048; /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */ + __IO uint32_t IEEE_R_DROP; /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */ + __IO uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */ + __IO uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */ + __IO uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */ + __IO uint32_t IEEE_R_MACERR; /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */ + __IO uint32_t IEEE_R_FDXFC; /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */ + uint8_t RESERVED_15[284]; + __IO uint32_t ATCR; /**< Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __IO uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_16[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type, *ENET_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ENET - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros + * @{ + */ + + +/* ENET - Register accessors */ +#define ENET_EIR_REG(base) ((base)->EIR) +#define ENET_EIMR_REG(base) ((base)->EIMR) +#define ENET_RDAR_REG(base) ((base)->RDAR) +#define ENET_TDAR_REG(base) ((base)->TDAR) +#define ENET_ECR_REG(base) ((base)->ECR) +#define ENET_MMFR_REG(base) ((base)->MMFR) +#define ENET_MSCR_REG(base) ((base)->MSCR) +#define ENET_MIBC_REG(base) ((base)->MIBC) +#define ENET_RCR_REG(base) ((base)->RCR) +#define ENET_TCR_REG(base) ((base)->TCR) +#define ENET_PALR_REG(base) ((base)->PALR) +#define ENET_PAUR_REG(base) ((base)->PAUR) +#define ENET_OPD_REG(base) ((base)->OPD) +#define ENET_IAUR_REG(base) ((base)->IAUR) +#define ENET_IALR_REG(base) ((base)->IALR) +#define ENET_GAUR_REG(base) ((base)->GAUR) +#define ENET_GALR_REG(base) ((base)->GALR) +#define ENET_TFWR_REG(base) ((base)->TFWR) +#define ENET_RDSR_REG(base) ((base)->RDSR) +#define ENET_TDSR_REG(base) ((base)->TDSR) +#define ENET_MRBR_REG(base) ((base)->MRBR) +#define ENET_RSFL_REG(base) ((base)->RSFL) +#define ENET_RSEM_REG(base) ((base)->RSEM) +#define ENET_RAEM_REG(base) ((base)->RAEM) +#define ENET_RAFL_REG(base) ((base)->RAFL) +#define ENET_TSEM_REG(base) ((base)->TSEM) +#define ENET_TAEM_REG(base) ((base)->TAEM) +#define ENET_TAFL_REG(base) ((base)->TAFL) +#define ENET_TIPG_REG(base) ((base)->TIPG) +#define ENET_FTRL_REG(base) ((base)->FTRL) +#define ENET_TACC_REG(base) ((base)->TACC) +#define ENET_RACC_REG(base) ((base)->RACC) +#define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) +#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) +#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) +#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) +#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) +#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) +#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) +#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) +#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) +#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) +#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) +#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) +#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) +#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) +#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) +#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) +#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) +#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) +#define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) +#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) +#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) +#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) +#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) +#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) +#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) +#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) +#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) +#define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) +#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) +#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) +#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) +#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) +#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) +#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) +#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) +#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) +#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) +#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) +#define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) +#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) +#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) +#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) +#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) +#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) +#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) +#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) +#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) +#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) +#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) +#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) +#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) +#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) +#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) +#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) +#define ENET_ATCR_REG(base) ((base)->ATCR) +#define ENET_ATVR_REG(base) ((base)->ATVR) +#define ENET_ATOFF_REG(base) ((base)->ATOFF) +#define ENET_ATPER_REG(base) ((base)->ATPER) +#define ENET_ATCOR_REG(base) ((base)->ATCOR) +#define ENET_ATINC_REG(base) ((base)->ATINC) +#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) +#define ENET_TGSR_REG(base) ((base)->TGSR) +#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) +#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) + +/*! + * @} + */ /* end of group ENET_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/* EIR Bit Fields */ +#define ENET_EIR_TS_TIMER_MASK 0x8000u +#define ENET_EIR_TS_TIMER_SHIFT 15 +#define ENET_EIR_TS_AVAIL_MASK 0x10000u +#define ENET_EIR_TS_AVAIL_SHIFT 16 +#define ENET_EIR_WAKEUP_MASK 0x20000u +#define ENET_EIR_WAKEUP_SHIFT 17 +#define ENET_EIR_PLR_MASK 0x40000u +#define ENET_EIR_PLR_SHIFT 18 +#define ENET_EIR_UN_MASK 0x80000u +#define ENET_EIR_UN_SHIFT 19 +#define ENET_EIR_RL_MASK 0x100000u +#define ENET_EIR_RL_SHIFT 20 +#define ENET_EIR_LC_MASK 0x200000u +#define ENET_EIR_LC_SHIFT 21 +#define ENET_EIR_EBERR_MASK 0x400000u +#define ENET_EIR_EBERR_SHIFT 22 +#define ENET_EIR_MII_MASK 0x800000u +#define ENET_EIR_MII_SHIFT 23 +#define ENET_EIR_RXB_MASK 0x1000000u +#define ENET_EIR_RXB_SHIFT 24 +#define ENET_EIR_RXF_MASK 0x2000000u +#define ENET_EIR_RXF_SHIFT 25 +#define ENET_EIR_TXB_MASK 0x4000000u +#define ENET_EIR_TXB_SHIFT 26 +#define ENET_EIR_TXF_MASK 0x8000000u +#define ENET_EIR_TXF_SHIFT 27 +#define ENET_EIR_GRA_MASK 0x10000000u +#define ENET_EIR_GRA_SHIFT 28 +#define ENET_EIR_BABT_MASK 0x20000000u +#define ENET_EIR_BABT_SHIFT 29 +#define ENET_EIR_BABR_MASK 0x40000000u +#define ENET_EIR_BABR_SHIFT 30 +/* EIMR Bit Fields */ +#define ENET_EIMR_TS_TIMER_MASK 0x8000u +#define ENET_EIMR_TS_TIMER_SHIFT 15 +#define ENET_EIMR_TS_AVAIL_MASK 0x10000u +#define ENET_EIMR_TS_AVAIL_SHIFT 16 +#define ENET_EIMR_WAKEUP_MASK 0x20000u +#define ENET_EIMR_WAKEUP_SHIFT 17 +#define ENET_EIMR_PLR_MASK 0x40000u +#define ENET_EIMR_PLR_SHIFT 18 +#define ENET_EIMR_UN_MASK 0x80000u +#define ENET_EIMR_UN_SHIFT 19 +#define ENET_EIMR_RL_MASK 0x100000u +#define ENET_EIMR_RL_SHIFT 20 +#define ENET_EIMR_LC_MASK 0x200000u +#define ENET_EIMR_LC_SHIFT 21 +#define ENET_EIMR_EBERR_MASK 0x400000u +#define ENET_EIMR_EBERR_SHIFT 22 +#define ENET_EIMR_MII_MASK 0x800000u +#define ENET_EIMR_MII_SHIFT 23 +#define ENET_EIMR_RXB_MASK 0x1000000u +#define ENET_EIMR_RXB_SHIFT 24 +#define ENET_EIMR_RXF_MASK 0x2000000u +#define ENET_EIMR_RXF_SHIFT 25 +#define ENET_EIMR_TXB_MASK 0x4000000u +#define ENET_EIMR_TXB_SHIFT 26 +#define ENET_EIMR_TXF_MASK 0x8000000u +#define ENET_EIMR_TXF_SHIFT 27 +#define ENET_EIMR_GRA_MASK 0x10000000u +#define ENET_EIMR_GRA_SHIFT 28 +#define ENET_EIMR_BABT_MASK 0x20000000u +#define ENET_EIMR_BABT_SHIFT 29 +#define ENET_EIMR_BABR_MASK 0x40000000u +#define ENET_EIMR_BABR_SHIFT 30 +/* RDAR Bit Fields */ +#define ENET_RDAR_RDAR_MASK 0x1000000u +#define ENET_RDAR_RDAR_SHIFT 24 +/* TDAR Bit Fields */ +#define ENET_TDAR_TDAR_MASK 0x1000000u +#define ENET_TDAR_TDAR_SHIFT 24 +/* ECR Bit Fields */ +#define ENET_ECR_RESET_MASK 0x1u +#define ENET_ECR_RESET_SHIFT 0 +#define ENET_ECR_ETHEREN_MASK 0x2u +#define ENET_ECR_ETHEREN_SHIFT 1 +#define ENET_ECR_MAGICEN_MASK 0x4u +#define ENET_ECR_MAGICEN_SHIFT 2 +#define ENET_ECR_SLEEP_MASK 0x8u +#define ENET_ECR_SLEEP_SHIFT 3 +#define ENET_ECR_EN1588_MASK 0x10u +#define ENET_ECR_EN1588_SHIFT 4 +#define ENET_ECR_DBGEN_MASK 0x40u +#define ENET_ECR_DBGEN_SHIFT 6 +#define ENET_ECR_STOPEN_MASK 0x80u +#define ENET_ECR_STOPEN_SHIFT 7 +#define ENET_ECR_DBSWP_MASK 0x100u +#define ENET_ECR_DBSWP_SHIFT 8 +/* MMFR Bit Fields */ +#define ENET_MMFR_DATA_MASK 0xFFFFu +#define ENET_MMFR_DATA_SHIFT 0 +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define EWM_SERV_REG(base) ((base)->SERV) +#define EWM_CMPL_REG(base) ((base)->CMPL) +#define EWM_CMPH_REG(base) ((base)->CMPH) +#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER) + +/*! + * @} + */ /* end of group EWM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define EWM_CTRL_EWMEN_MASK 0x1u +#define EWM_CTRL_EWMEN_SHIFT 0 +#define EWM_CTRL_ASSIN_MASK 0x2u +#define EWM_CTRL_ASSIN_SHIFT 1 +#define EWM_CTRL_INEN_MASK 0x4u +#define EWM_CTRL_INEN_SHIFT 2 +#define EWM_CTRL_INTEN_MASK 0x8u +#define EWM_CTRL_INTEN_SHIFT 3 +/* SERV Bit Fields */ +#define EWM_SERV_SERVICE_MASK 0xFFu +#define EWM_SERV_SERVICE_SHIFT 0 +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR) +#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) +#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) +#define FB_CSPMCR_REG(base) ((base)->CSPMCR) + +/*! + * @} + */ /* end of group FB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FB_Register_Masks FB Register Masks + * @{ + */ + +/* CSAR Bit Fields */ +#define FB_CSAR_BA_MASK 0xFFFF0000u +#define FB_CSAR_BA_SHIFT 16 +#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR) +#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) +#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) +#define FMC_TAGVD_REG(base,index,index2) ((base)->TAGVD[index][index2]) +#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) +#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) + +/*! + * @} + */ /* end of group FMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/* PFAPR Bit Fields */ +#define FMC_PFAPR_M0AP_MASK 0x3u +#define FMC_PFAPR_M0AP_SHIFT 0 +#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) +#define FTFL_FCNFG_REG(base) ((base)->FCNFG) +#define FTFL_FSEC_REG(base) ((base)->FSEC) +#define FTFL_FOPT_REG(base) ((base)->FOPT) +#define FTFL_FCCOB3_REG(base) ((base)->FCCOB3) +#define FTFL_FCCOB2_REG(base) ((base)->FCCOB2) +#define FTFL_FCCOB1_REG(base) ((base)->FCCOB1) +#define FTFL_FCCOB0_REG(base) ((base)->FCCOB0) +#define FTFL_FCCOB7_REG(base) ((base)->FCCOB7) +#define FTFL_FCCOB6_REG(base) ((base)->FCCOB6) +#define FTFL_FCCOB5_REG(base) ((base)->FCCOB5) +#define FTFL_FCCOB4_REG(base) ((base)->FCCOB4) +#define FTFL_FCCOBB_REG(base) ((base)->FCCOBB) +#define FTFL_FCCOBA_REG(base) ((base)->FCCOBA) +#define FTFL_FCCOB9_REG(base) ((base)->FCCOB9) +#define FTFL_FCCOB8_REG(base) ((base)->FCCOB8) +#define FTFL_FPROT3_REG(base) ((base)->FPROT3) +#define FTFL_FPROT2_REG(base) ((base)->FPROT2) +#define FTFL_FPROT1_REG(base) ((base)->FPROT1) +#define FTFL_FPROT0_REG(base) ((base)->FPROT0) +#define FTFL_FEPROT_REG(base) ((base)->FEPROT) +#define FTFL_FDPROT_REG(base) ((base)->FDPROT) + +/*! + * @} + */ /* end of group FTFL_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FTFL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTFL_Register_Masks FTFL Register Masks + * @{ + */ + +/* FSTAT Bit Fields */ +#define FTFL_FSTAT_MGSTAT0_MASK 0x1u +#define FTFL_FSTAT_MGSTAT0_SHIFT 0 +#define FTFL_FSTAT_FPVIOL_MASK 0x10u +#define FTFL_FSTAT_FPVIOL_SHIFT 4 +#define FTFL_FSTAT_ACCERR_MASK 0x20u +#define FTFL_FSTAT_ACCERR_SHIFT 5 +#define FTFL_FSTAT_RDCOLERR_MASK 0x40u +#define FTFL_FSTAT_RDCOLERR_SHIFT 6 +#define FTFL_FSTAT_CCIF_MASK 0x80u +#define FTFL_FSTAT_CCIF_SHIFT 7 +/* FCNFG Bit Fields */ +#define FTFL_FCNFG_EEERDY_MASK 0x1u +#define FTFL_FCNFG_EEERDY_SHIFT 0 +#define FTFL_FCNFG_RAMRDY_MASK 0x2u +#define FTFL_FCNFG_RAMRDY_SHIFT 1 +#define FTFL_FCNFG_PFLSH_MASK 0x4u +#define FTFL_FCNFG_PFLSH_SHIFT 2 +#define FTFL_FCNFG_SWAP_MASK 0x8u +#define FTFL_FCNFG_SWAP_SHIFT 3 +#define FTFL_FCNFG_ERSSUSP_MASK 0x10u +#define FTFL_FCNFG_ERSSUSP_SHIFT 4 +#define FTFL_FCNFG_ERSAREQ_MASK 0x20u +#define FTFL_FCNFG_ERSAREQ_SHIFT 5 +#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u +#define FTFL_FCNFG_RDCOLLIE_SHIFT 6 +#define FTFL_FCNFG_CCIE_MASK 0x80u +#define FTFL_FCNFG_CCIE_SHIFT 7 +/* FSEC Bit Fields */ +#define FTFL_FSEC_SEC_MASK 0x3u +#define FTFL_FSEC_SEC_SHIFT 0 +#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<SC) +#define FTM_CNT_REG(base) ((base)->CNT) +#define FTM_MOD_REG(base) ((base)->MOD) +#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) +#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) +#define FTM_CNTIN_REG(base) ((base)->CNTIN) +#define FTM_STATUS_REG(base) ((base)->STATUS) +#define FTM_MODE_REG(base) ((base)->MODE) +#define FTM_SYNC_REG(base) ((base)->SYNC) +#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) +#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) +#define FTM_COMBINE_REG(base) ((base)->COMBINE) +#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) +#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) +#define FTM_POL_REG(base) ((base)->POL) +#define FTM_FMS_REG(base) ((base)->FMS) +#define FTM_FILTER_REG(base) ((base)->FILTER) +#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) +#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) +#define FTM_CONF_REG(base) ((base)->CONF) +#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) +#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) +#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) +#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) +#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) + +/*! + * @} + */ /* end of group FTM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) +#define GPIO_PSOR_REG(base) ((base)->PSOR) +#define GPIO_PCOR_REG(base) ((base)->PCOR) +#define GPIO_PTOR_REG(base) ((base)->PTOR) +#define GPIO_PDIR_REG(base) ((base)->PDIR) +#define GPIO_PDDR_REG(base) ((base)->PDDR) + +/*! + * @} + */ /* end of group GPIO_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* PDOR Bit Fields */ +#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu +#define GPIO_PDOR_PDO_SHIFT 0 +#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) +#define I2C_F_REG(base) ((base)->F) +#define I2C_C1_REG(base) ((base)->C1) +#define I2C_S_REG(base) ((base)->S) +#define I2C_D_REG(base) ((base)->D) +#define I2C_C2_REG(base) ((base)->C2) +#define I2C_FLT_REG(base) ((base)->FLT) +#define I2C_RA_REG(base) ((base)->RA) +#define I2C_SMB_REG(base) ((base)->SMB) +#define I2C_A2_REG(base) ((base)->A2) +#define I2C_SLTH_REG(base) ((base)->SLTH) +#define I2C_SLTL_REG(base) ((base)->SLTL) + +/*! + * @} + */ /* end of group I2C_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* A1 Bit Fields */ +#define I2C_A1_AD_MASK 0xFEu +#define I2C_A1_AD_SHIFT 1 +#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) +#define I2S_TCR1_REG(base) ((base)->TCR1) +#define I2S_TCR2_REG(base) ((base)->TCR2) +#define I2S_TCR3_REG(base) ((base)->TCR3) +#define I2S_TCR4_REG(base) ((base)->TCR4) +#define I2S_TCR5_REG(base) ((base)->TCR5) +#define I2S_TDR_REG(base,index) ((base)->TDR[index]) +#define I2S_TFR_REG(base,index) ((base)->TFR[index]) +#define I2S_TMR_REG(base) ((base)->TMR) +#define I2S_RCSR_REG(base) ((base)->RCSR) +#define I2S_RCR1_REG(base) ((base)->RCR1) +#define I2S_RCR2_REG(base) ((base)->RCR2) +#define I2S_RCR3_REG(base) ((base)->RCR3) +#define I2S_RCR4_REG(base) ((base)->RCR4) +#define I2S_RCR5_REG(base) ((base)->RCR5) +#define I2S_RDR_REG(base,index) ((base)->RDR[index]) +#define I2S_RFR_REG(base,index) ((base)->RFR[index]) +#define I2S_RMR_REG(base) ((base)->RMR) +#define I2S_MCR_REG(base) ((base)->MCR) +#define I2S_MDR_REG(base) ((base)->MDR) + +/*! + * @} + */ /* end of group I2S_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x7u +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<PE1) +#define LLWU_PE2_REG(base) ((base)->PE2) +#define LLWU_PE3_REG(base) ((base)->PE3) +#define LLWU_PE4_REG(base) ((base)->PE4) +#define LLWU_ME_REG(base) ((base)->ME) +#define LLWU_F1_REG(base) ((base)->F1) +#define LLWU_F2_REG(base) ((base)->F2) +#define LLWU_F3_REG(base) ((base)->F3) +#define LLWU_FILT1_REG(base) ((base)->FILT1) +#define LLWU_FILT2_REG(base) ((base)->FILT2) +#define LLWU_RST_REG(base) ((base)->RST) + +/*! + * @} + */ /* end of group LLWU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- LLWU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LLWU_Register_Masks LLWU Register Masks + * @{ + */ + +/* PE1 Bit Fields */ +#define LLWU_PE1_WUPE0_MASK 0x3u +#define LLWU_PE1_WUPE0_SHIFT 0 +#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) +#define LPTMR_PSR_REG(base) ((base)->PSR) +#define LPTMR_CMR_REG(base) ((base)->CMR) +#define LPTMR_CNR_REG(base) ((base)->CNR) + +/*! + * @} + */ /* end of group LPTMR_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/* CSR Bit Fields */ +#define LPTMR_CSR_TEN_MASK 0x1u +#define LPTMR_CSR_TEN_SHIFT 0 +#define LPTMR_CSR_TMS_MASK 0x2u +#define LPTMR_CSR_TMS_SHIFT 1 +#define LPTMR_CSR_TFC_MASK 0x4u +#define LPTMR_CSR_TFC_SHIFT 2 +#define LPTMR_CSR_TPP_MASK 0x8u +#define LPTMR_CSR_TPP_SHIFT 3 +#define LPTMR_CSR_TPS_MASK 0x30u +#define LPTMR_CSR_TPS_SHIFT 4 +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<C1) +#define MCG_C2_REG(base) ((base)->C2) +#define MCG_C3_REG(base) ((base)->C3) +#define MCG_C4_REG(base) ((base)->C4) +#define MCG_C5_REG(base) ((base)->C5) +#define MCG_C6_REG(base) ((base)->C6) +#define MCG_S_REG(base) ((base)->S) +#define MCG_SC_REG(base) ((base)->SC) +#define MCG_ATCVH_REG(base) ((base)->ATCVH) +#define MCG_ATCVL_REG(base) ((base)->ATCVL) +#define MCG_C7_REG(base) ((base)->C7) +#define MCG_C8_REG(base) ((base)->C8) +#define MCG_C9_REG(base) ((base)->C9) +#define MCG_C10_REG(base) ((base)->C10) + +/*! + * @} + */ /* end of group MCG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCG_Register_Masks MCG Register Masks + * @{ + */ + +/* C1 Bit Fields */ +#define MCG_C1_IREFSTEN_MASK 0x1u +#define MCG_C1_IREFSTEN_SHIFT 0 +#define MCG_C1_IRCLKEN_MASK 0x2u +#define MCG_C1_IRCLKEN_SHIFT 1 +#define MCG_C1_IREFS_MASK 0x4u +#define MCG_C1_IREFS_SHIFT 2 +#define MCG_C1_FRDIV_MASK 0x38u +#define MCG_C1_FRDIV_SHIFT 3 +#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<PLASC) +#define MCM_PLAMC_REG(base) ((base)->PLAMC) +#define MCM_CR_REG(base) ((base)->CR) +#define MCM_ISR_REG(base) ((base)->ISR) +#define MCM_ETBCC_REG(base) ((base)->ETBCC) +#define MCM_ETBRL_REG(base) ((base)->ETBRL) +#define MCM_ETBCNT_REG(base) ((base)->ETBCNT) +#define MCM_PID_REG(base) ((base)->PID) + +/*! + * @} + */ /* end of group MCM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/* PLASC Bit Fields */ +#define MCM_PLASC_ASC_MASK 0xFFu +#define MCM_PLASC_ASC_SHIFT 0 +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CESR) +#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) +#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) +#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) +#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) + +/*! + * @} + */ /* end of group MPU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MPU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MPU_Register_Masks MPU Register Masks + * @{ + */ + +/* CESR Bit Fields */ +#define MPU_CESR_VLD_MASK 0x1u +#define MPU_CESR_VLD_SHIFT 0 +#define MPU_CESR_NRGD_MASK 0xF00u +#define MPU_CESR_NRGD_SHIFT 8 +#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<BACKKEY3) +#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) +#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) +#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) +#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) +#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) +#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) +#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) +#define NV_FPROT3_REG(base) ((base)->FPROT3) +#define NV_FPROT2_REG(base) ((base)->FPROT2) +#define NV_FPROT1_REG(base) ((base)->FPROT1) +#define NV_FPROT0_REG(base) ((base)->FPROT0) +#define NV_FSEC_REG(base) ((base)->FSEC) +#define NV_FOPT_REG(base) ((base)->FOPT) +#define NV_FEPROT_REG(base) ((base)->FEPROT) +#define NV_FDPROT_REG(base) ((base)->FDPROT) + +/*! + * @} + */ /* end of group NV_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- NV Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NV_Register_Masks NV Register Masks + * @{ + */ + +/* BACKKEY3 Bit Fields */ +#define NV_BACKKEY3_KEY_MASK 0xFFu +#define NV_BACKKEY3_KEY_SHIFT 0 +#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) + +/*! + * @} + */ /* end of group OSC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- OSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Register_Masks OSC Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define OSC_CR_SC16P_MASK 0x1u +#define OSC_CR_SC16P_SHIFT 0 +#define OSC_CR_SC8P_MASK 0x2u +#define OSC_CR_SC8P_SHIFT 1 +#define OSC_CR_SC4P_MASK 0x4u +#define OSC_CR_SC4P_SHIFT 2 +#define OSC_CR_SC2P_MASK 0x8u +#define OSC_CR_SC2P_SHIFT 3 +#define OSC_CR_EREFSTEN_MASK 0x20u +#define OSC_CR_EREFSTEN_SHIFT 5 +#define OSC_CR_ERCLKEN_MASK 0x80u +#define OSC_CR_ERCLKEN_SHIFT 7 + +/*! + * @} + */ /* end of group OSC_Register_Masks */ + + +/* OSC - Peripheral instance base addresses */ +/** Peripheral OSC base address */ +#define OSC_BASE (0x40065000u) +/** Peripheral OSC base pointer */ +#define OSC ((OSC_Type *)OSC_BASE) +#define OSC_BASE_PTR (OSC) +/** Array initializer of OSC peripheral base addresses */ +#define OSC_BASE_ADDRS { OSC_BASE } +/** Array initializer of OSC peripheral base pointers */ +#define OSC_BASE_PTRS { OSC } + +/* ---------------------------------------------------------------------------- + -- OSC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros + * @{ + */ + + +/* OSC - Register instance definitions */ +/* OSC */ +#define OSC_CR OSC_CR_REG(OSC) + +/*! + * @} + */ /* end of group OSC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group OSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer + * @{ + */ + +/** PDB - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */ + __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */ + __I uint32_t CNT; /**< Counter Register, offset: 0x8 */ + __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */ + __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */ + __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */ + uint8_t RESERVED_0[24]; + } CH[2]; + uint8_t RESERVED_0[240]; + struct { /* offset: 0x150, array step: 0x8 */ + __IO uint32_t INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */ + __IO uint32_t INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */ + } DAC[2]; + uint8_t RESERVED_1[48]; + __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ + __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ +} PDB_Type, *PDB_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- PDB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros + * @{ + */ + + +/* PDB - Register accessors */ +#define PDB_SC_REG(base) ((base)->SC) +#define PDB_MOD_REG(base) ((base)->MOD) +#define PDB_CNT_REG(base) ((base)->CNT) +#define PDB_IDLY_REG(base) ((base)->IDLY) +#define PDB_C1_REG(base,index) ((base)->CH[index].C1) +#define PDB_S_REG(base,index) ((base)->CH[index].S) +#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) +#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) +#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) +#define PDB_POEN_REG(base) ((base)->POEN) +#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) + +/*! + * @} + */ /* end of group PDB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PDB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDB_Register_Masks PDB Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define PDB_SC_LDOK_MASK 0x1u +#define PDB_SC_LDOK_SHIFT 0 +#define PDB_SC_CONT_MASK 0x2u +#define PDB_SC_CONT_SHIFT 1 +#define PDB_SC_MULT_MASK 0xCu +#define PDB_SC_MULT_SHIFT 2 +#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) +#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) +#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) +#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) + +/*! + * @} + */ /* end of group PIT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define PIT_MCR_FRZ_MASK 0x1u +#define PIT_MCR_FRZ_SHIFT 0 +#define PIT_MCR_MDIS_MASK 0x2u +#define PIT_MCR_MDIS_SHIFT 1 +/* LDVAL Bit Fields */ +#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu +#define PIT_LDVAL_TSV_SHIFT 0 +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) +#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) +#define PMC_REGSC_REG(base) ((base)->REGSC) + +/*! + * @} + */ /* end of group PMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/* LVDSC1 Bit Fields */ +#define PMC_LVDSC1_LVDV_MASK 0x3u +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) +#define PORT_GPCLR_REG(base) ((base)->GPCLR) +#define PORT_GPCHR_REG(base) ((base)->GPCHR) +#define PORT_ISFR_REG(base) ((base)->ISFR) +#define PORT_DFER_REG(base) ((base)->DFER) +#define PORT_DFCR_REG(base) ((base)->DFCR) +#define PORT_DFWR_REG(base) ((base)->DFWR) + +/*! + * @} + */ /* end of group PORT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/* PCR Bit Fields */ +#define PORT_PCR_PS_MASK 0x1u +#define PORT_PCR_PS_SHIFT 0 +#define PORT_PCR_PE_MASK 0x2u +#define PORT_PCR_PE_SHIFT 1 +#define PORT_PCR_SRE_MASK 0x4u +#define PORT_PCR_SRE_SHIFT 2 +#define PORT_PCR_PFE_MASK 0x10u +#define PORT_PCR_PFE_SHIFT 4 +#define PORT_PCR_ODE_MASK 0x20u +#define PORT_PCR_ODE_SHIFT 5 +#define PORT_PCR_DSE_MASK 0x40u +#define PORT_PCR_DSE_SHIFT 6 +#define PORT_PCR_MUX_MASK 0x700u +#define PORT_PCR_MUX_SHIFT 8 +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0) +#define RCM_SRS1_REG(base) ((base)->SRS1) +#define RCM_RPFC_REG(base) ((base)->RPFC) +#define RCM_RPFW_REG(base) ((base)->RPFW) +#define RCM_MR_REG(base) ((base)->MR) + +/*! + * @} + */ /* end of group RCM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RCM_Register_Masks RCM Register Masks + * @{ + */ + +/* SRS0 Bit Fields */ +#define RCM_SRS0_WAKEUP_MASK 0x1u +#define RCM_SRS0_WAKEUP_SHIFT 0 +#define RCM_SRS0_LVD_MASK 0x2u +#define RCM_SRS0_LVD_SHIFT 1 +#define RCM_SRS0_LOC_MASK 0x4u +#define RCM_SRS0_LOC_SHIFT 2 +#define RCM_SRS0_LOL_MASK 0x8u +#define RCM_SRS0_LOL_SHIFT 3 +#define RCM_SRS0_WDOG_MASK 0x20u +#define RCM_SRS0_WDOG_SHIFT 5 +#define RCM_SRS0_PIN_MASK 0x40u +#define RCM_SRS0_PIN_SHIFT 6 +#define RCM_SRS0_POR_MASK 0x80u +#define RCM_SRS0_POR_SHIFT 7 +/* SRS1 Bit Fields */ +#define RCM_SRS1_JTAG_MASK 0x1u +#define RCM_SRS1_JTAG_SHIFT 0 +#define RCM_SRS1_LOCKUP_MASK 0x2u +#define RCM_SRS1_LOCKUP_SHIFT 1 +#define RCM_SRS1_SW_MASK 0x4u +#define RCM_SRS1_SW_SHIFT 2 +#define RCM_SRS1_MDM_AP_MASK 0x8u +#define RCM_SRS1_MDM_AP_SHIFT 3 +#define RCM_SRS1_EZPT_MASK 0x10u +#define RCM_SRS1_EZPT_SHIFT 4 +#define RCM_SRS1_SACKERR_MASK 0x20u +#define RCM_SRS1_SACKERR_SHIFT 5 +/* RPFC Bit Fields */ +#define RCM_RPFC_RSTFLTSRW_MASK 0x3u +#define RCM_RPFC_RSTFLTSRW_SHIFT 0 +#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index]) + +/*! + * @} + */ /* end of group RFSYS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RFSYS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFSYS_Register_Masks RFSYS Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFSYS_REG_LL_MASK 0xFFu +#define RFSYS_REG_LL_SHIFT 0 +#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) + +/*! + * @} + */ /* end of group RFVBAT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RFVBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFVBAT_REG_LL_MASK 0xFFu +#define RFVBAT_REG_LL_SHIFT 0 +#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR) +#define RNG_SR_REG(base) ((base)->SR) +#define RNG_ER_REG(base) ((base)->ER) +#define RNG_OR_REG(base) ((base)->OR) + +/*! + * @} + */ /* end of group RNG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define RNG_CR_GO_MASK 0x1u +#define RNG_CR_GO_SHIFT 0 +#define RNG_CR_HA_MASK 0x2u +#define RNG_CR_HA_SHIFT 1 +#define RNG_CR_INTM_MASK 0x4u +#define RNG_CR_INTM_SHIFT 2 +#define RNG_CR_CLRI_MASK 0x8u +#define RNG_CR_CLRI_SHIFT 3 +#define RNG_CR_SLP_MASK 0x10u +#define RNG_CR_SLP_SHIFT 4 +/* SR Bit Fields */ +#define RNG_SR_SECV_MASK 0x1u +#define RNG_SR_SECV_SHIFT 0 +#define RNG_SR_LRS_MASK 0x2u +#define RNG_SR_LRS_SHIFT 1 +#define RNG_SR_ORU_MASK 0x4u +#define RNG_SR_ORU_SHIFT 2 +#define RNG_SR_ERRI_MASK 0x8u +#define RNG_SR_ERRI_SHIFT 3 +#define RNG_SR_SLP_MASK 0x10u +#define RNG_SR_SLP_SHIFT 4 +#define RNG_SR_OREG_LVL_MASK 0xFF00u +#define RNG_SR_OREG_LVL_SHIFT 8 +#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<TSR) +#define RTC_TPR_REG(base) ((base)->TPR) +#define RTC_TAR_REG(base) ((base)->TAR) +#define RTC_TCR_REG(base) ((base)->TCR) +#define RTC_CR_REG(base) ((base)->CR) +#define RTC_SR_REG(base) ((base)->SR) +#define RTC_LR_REG(base) ((base)->LR) +#define RTC_IER_REG(base) ((base)->IER) +#define RTC_WAR_REG(base) ((base)->WAR) +#define RTC_RAR_REG(base) ((base)->RAR) + +/*! + * @} + */ /* end of group RTC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/* TSR Bit Fields */ +#define RTC_TSR_TSR_MASK 0xFFFFFFFFu +#define RTC_TSR_TSR_SHIFT 0 +#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<DSADDR) +#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) +#define SDHC_CMDARG_REG(base) ((base)->CMDARG) +#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) +#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) +#define SDHC_DATPORT_REG(base) ((base)->DATPORT) +#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) +#define SDHC_PROCTL_REG(base) ((base)->PROCTL) +#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) +#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) +#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) +#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) +#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) +#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) +#define SDHC_WML_REG(base) ((base)->WML) +#define SDHC_FEVT_REG(base) ((base)->FEVT) +#define SDHC_ADMAES_REG(base) ((base)->ADMAES) +#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) +#define SDHC_VENDOR_REG(base) ((base)->VENDOR) +#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) +#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) + +/*! + * @} + */ /* end of group SDHC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDHC_Register_Masks SDHC Register Masks + * @{ + */ + +/* DSADDR Bit Fields */ +#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu +#define SDHC_DSADDR_DSADDR_SHIFT 2 +#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) +#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) +#define SIM_SOPT2_REG(base) ((base)->SOPT2) +#define SIM_SOPT4_REG(base) ((base)->SOPT4) +#define SIM_SOPT5_REG(base) ((base)->SOPT5) +#define SIM_SOPT7_REG(base) ((base)->SOPT7) +#define SIM_SDID_REG(base) ((base)->SDID) +#define SIM_SCGC1_REG(base) ((base)->SCGC1) +#define SIM_SCGC2_REG(base) ((base)->SCGC2) +#define SIM_SCGC3_REG(base) ((base)->SCGC3) +#define SIM_SCGC4_REG(base) ((base)->SCGC4) +#define SIM_SCGC5_REG(base) ((base)->SCGC5) +#define SIM_SCGC6_REG(base) ((base)->SCGC6) +#define SIM_SCGC7_REG(base) ((base)->SCGC7) +#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) +#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) +#define SIM_FCFG1_REG(base) ((base)->FCFG1) +#define SIM_FCFG2_REG(base) ((base)->FCFG2) +#define SIM_UIDH_REG(base) ((base)->UIDH) +#define SIM_UIDMH_REG(base) ((base)->UIDMH) +#define SIM_UIDML_REG(base) ((base)->UIDML) +#define SIM_UIDL_REG(base) ((base)->UIDL) + +/*! + * @} + */ /* end of group SIM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/* SOPT1 Bit Fields */ +#define SIM_SOPT1_RAMSIZE_MASK 0xF000u +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) +#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) +#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) +#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) + +/*! + * @} + */ /* end of group SMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMC_Register_Masks SMC Register Masks + * @{ + */ + +/* PMPROT Bit Fields */ +#define SMC_PMPROT_AVLLS_MASK 0x2u +#define SMC_PMPROT_AVLLS_SHIFT 1 +#define SMC_PMPROT_ALLS_MASK 0x8u +#define SMC_PMPROT_ALLS_SHIFT 3 +#define SMC_PMPROT_AVLP_MASK 0x20u +#define SMC_PMPROT_AVLP_SHIFT 5 +/* PMCTRL Bit Fields */ +#define SMC_PMCTRL_STOPM_MASK 0x7u +#define SMC_PMCTRL_STOPM_SHIFT 0 +#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<MCR) +#define SPI_TCR_REG(base) ((base)->TCR) +#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) +#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) +#define SPI_SR_REG(base) ((base)->SR) +#define SPI_RSER_REG(base) ((base)->RSER) +#define SPI_PUSHR_REG(base) ((base)->PUSHR) +#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) +#define SPI_POPR_REG(base) ((base)->POPR) +#define SPI_TXFR0_REG(base) ((base)->TXFR0) +#define SPI_TXFR1_REG(base) ((base)->TXFR1) +#define SPI_TXFR2_REG(base) ((base)->TXFR2) +#define SPI_TXFR3_REG(base) ((base)->TXFR3) +#define SPI_RXFR0_REG(base) ((base)->RXFR0) +#define SPI_RXFR1_REG(base) ((base)->RXFR1) +#define SPI_RXFR2_REG(base) ((base)->RXFR2) +#define SPI_RXFR3_REG(base) ((base)->RXFR3) + +/*! + * @} + */ /* end of group SPI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define SPI_MCR_HALT_MASK 0x1u +#define SPI_MCR_HALT_SHIFT 0 +#define SPI_MCR_SMPL_PT_MASK 0x300u +#define SPI_MCR_SMPL_PT_SHIFT 8 +#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<GENCS) +#define TSI_SCANC_REG(base) ((base)->SCANC) +#define TSI_PEN_REG(base) ((base)->PEN) +#define TSI_WUCNTR_REG(base) ((base)->WUCNTR) +#define TSI_CNTR1_REG(base) ((base)->CNTR1) +#define TSI_CNTR3_REG(base) ((base)->CNTR3) +#define TSI_CNTR5_REG(base) ((base)->CNTR5) +#define TSI_CNTR7_REG(base) ((base)->CNTR7) +#define TSI_CNTR9_REG(base) ((base)->CNTR9) +#define TSI_CNTR11_REG(base) ((base)->CNTR11) +#define TSI_CNTR13_REG(base) ((base)->CNTR13) +#define TSI_CNTR15_REG(base) ((base)->CNTR15) +#define TSI_THRESHOLD_REG(base) ((base)->THRESHOLD) + +/*! + * @} + */ /* end of group TSI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- TSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSI_Register_Masks TSI Register Masks + * @{ + */ + +/* GENCS Bit Fields */ +#define TSI_GENCS_STPE_MASK 0x1u +#define TSI_GENCS_STPE_SHIFT 0 +#define TSI_GENCS_STM_MASK 0x2u +#define TSI_GENCS_STM_SHIFT 1 +#define TSI_GENCS_ESOR_MASK 0x10u +#define TSI_GENCS_ESOR_SHIFT 4 +#define TSI_GENCS_ERIE_MASK 0x20u +#define TSI_GENCS_ERIE_SHIFT 5 +#define TSI_GENCS_TSIIE_MASK 0x40u +#define TSI_GENCS_TSIIE_SHIFT 6 +#define TSI_GENCS_TSIEN_MASK 0x80u +#define TSI_GENCS_TSIEN_SHIFT 7 +#define TSI_GENCS_SWTS_MASK 0x100u +#define TSI_GENCS_SWTS_SHIFT 8 +#define TSI_GENCS_SCNIP_MASK 0x200u +#define TSI_GENCS_SCNIP_SHIFT 9 +#define TSI_GENCS_OVRF_MASK 0x1000u +#define TSI_GENCS_OVRF_SHIFT 12 +#define TSI_GENCS_EXTERF_MASK 0x2000u +#define TSI_GENCS_EXTERF_SHIFT 13 +#define TSI_GENCS_OUTRGF_MASK 0x4000u +#define TSI_GENCS_OUTRGF_SHIFT 14 +#define TSI_GENCS_EOSF_MASK 0x8000u +#define TSI_GENCS_EOSF_SHIFT 15 +#define TSI_GENCS_PS_MASK 0x70000u +#define TSI_GENCS_PS_SHIFT 16 +#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<BDH) +#define UART_BDL_REG(base) ((base)->BDL) +#define UART_C1_REG(base) ((base)->C1) +#define UART_C2_REG(base) ((base)->C2) +#define UART_S1_REG(base) ((base)->S1) +#define UART_S2_REG(base) ((base)->S2) +#define UART_C3_REG(base) ((base)->C3) +#define UART_D_REG(base) ((base)->D) +#define UART_MA1_REG(base) ((base)->MA1) +#define UART_MA2_REG(base) ((base)->MA2) +#define UART_C4_REG(base) ((base)->C4) +#define UART_C5_REG(base) ((base)->C5) +#define UART_ED_REG(base) ((base)->ED) +#define UART_MODEM_REG(base) ((base)->MODEM) +#define UART_IR_REG(base) ((base)->IR) +#define UART_PFIFO_REG(base) ((base)->PFIFO) +#define UART_CFIFO_REG(base) ((base)->CFIFO) +#define UART_SFIFO_REG(base) ((base)->SFIFO) +#define UART_TWFIFO_REG(base) ((base)->TWFIFO) +#define UART_TCFIFO_REG(base) ((base)->TCFIFO) +#define UART_RWFIFO_REG(base) ((base)->RWFIFO) +#define UART_RCFIFO_REG(base) ((base)->RCFIFO) +#define UART_C7816_REG(base) ((base)->C7816) +#define UART_IE7816_REG(base) ((base)->IE7816) +#define UART_IS7816_REG(base) ((base)->IS7816) +#define UART_WP7816T0_REG(base) ((base)->WP7816T0) +#define UART_WP7816T1_REG(base) ((base)->WP7816T1) +#define UART_WN7816_REG(base) ((base)->WN7816) +#define UART_WF7816_REG(base) ((base)->WF7816) +#define UART_ET7816_REG(base) ((base)->ET7816) +#define UART_TL7816_REG(base) ((base)->TL7816) +#define UART_C6_REG(base) ((base)->C6) +#define UART_PCTH_REG(base) ((base)->PCTH) +#define UART_PCTL_REG(base) ((base)->PCTL) +#define UART_B1T_REG(base) ((base)->B1T) +#define UART_SDTH_REG(base) ((base)->SDTH) +#define UART_SDTL_REG(base) ((base)->SDTL) +#define UART_PRE_REG(base) ((base)->PRE) +#define UART_TPL_REG(base) ((base)->TPL) +#define UART_IE_REG(base) ((base)->IE) +#define UART_WB_REG(base) ((base)->WB) +#define UART_S3_REG(base) ((base)->S3) +#define UART_S4_REG(base) ((base)->S4) +#define UART_RPL_REG(base) ((base)->RPL) +#define UART_RPREL_REG(base) ((base)->RPREL) +#define UART_CPW_REG(base) ((base)->CPW) +#define UART_RIDT_REG(base) ((base)->RIDT) +#define UART_TIDT_REG(base) ((base)->TIDT) + +/*! + * @} + */ /* end of group UART_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* BDH Bit Fields */ +#define UART_BDH_SBR_MASK 0x1Fu +#define UART_BDH_SBR_SHIFT 0 +#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) +#define USB_IDCOMP_REG(base) ((base)->IDCOMP) +#define USB_REV_REG(base) ((base)->REV) +#define USB_ADDINFO_REG(base) ((base)->ADDINFO) +#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) +#define USB_OTGICR_REG(base) ((base)->OTGICR) +#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) +#define USB_OTGCTL_REG(base) ((base)->OTGCTL) +#define USB_ISTAT_REG(base) ((base)->ISTAT) +#define USB_INTEN_REG(base) ((base)->INTEN) +#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) +#define USB_ERREN_REG(base) ((base)->ERREN) +#define USB_STAT_REG(base) ((base)->STAT) +#define USB_CTL_REG(base) ((base)->CTL) +#define USB_ADDR_REG(base) ((base)->ADDR) +#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) +#define USB_FRMNUML_REG(base) ((base)->FRMNUML) +#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) +#define USB_TOKEN_REG(base) ((base)->TOKEN) +#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) +#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) +#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) +#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) +#define USB_USBCTRL_REG(base) ((base)->USBCTRL) +#define USB_OBSERVE_REG(base) ((base)->OBSERVE) +#define USB_CONTROL_REG(base) ((base)->CONTROL) +#define USB_USBTRC0_REG(base) ((base)->USBTRC0) +#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) + +/*! + * @} + */ /* end of group USB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/* PERID Bit Fields */ +#define USB_PERID_ID_MASK 0x3Fu +#define USB_PERID_ID_SHIFT 0 +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<CONTROL) +#define USBDCD_CLOCK_REG(base) ((base)->CLOCK) +#define USBDCD_STATUS_REG(base) ((base)->STATUS) +#define USBDCD_TIMER0_REG(base) ((base)->TIMER0) +#define USBDCD_TIMER1_REG(base) ((base)->TIMER1) +#define USBDCD_TIMER2_REG(base) ((base)->TIMER2) + +/*! + * @} + */ /* end of group USBDCD_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USBDCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBDCD_Register_Masks USBDCD Register Masks + * @{ + */ + +/* CONTROL Bit Fields */ +#define USBDCD_CONTROL_IACK_MASK 0x1u +#define USBDCD_CONTROL_IACK_SHIFT 0 +#define USBDCD_CONTROL_IF_MASK 0x100u +#define USBDCD_CONTROL_IF_SHIFT 8 +#define USBDCD_CONTROL_IE_MASK 0x10000u +#define USBDCD_CONTROL_IE_SHIFT 16 +#define USBDCD_CONTROL_START_MASK 0x1000000u +#define USBDCD_CONTROL_START_SHIFT 24 +#define USBDCD_CONTROL_SR_MASK 0x2000000u +#define USBDCD_CONTROL_SR_SHIFT 25 +/* CLOCK Bit Fields */ +#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u +#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 +#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu +#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 +#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<TRM) +#define VREF_SC_REG(base) ((base)->SC) + +/*! + * @} + */ /* end of group VREF_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/* TRM Bit Fields */ +#define VREF_TRM_TRIM_MASK 0x3Fu +#define VREF_TRM_TRIM_SHIFT 0 +#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) +#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) +#define WDOG_TOVALH_REG(base) ((base)->TOVALH) +#define WDOG_TOVALL_REG(base) ((base)->TOVALL) +#define WDOG_WINH_REG(base) ((base)->WINH) +#define WDOG_WINL_REG(base) ((base)->WINL) +#define WDOG_REFRESH_REG(base) ((base)->REFRESH) +#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) +#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) +#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) +#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) +#define WDOG_PRESC_REG(base) ((base)->PRESC) + +/*! + * @} + */ /* end of group WDOG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* STCTRLH Bit Fields */ +#define WDOG_STCTRLH_WDOGEN_MASK 0x1u +#define WDOG_STCTRLH_WDOGEN_SHIFT 0 +#define WDOG_STCTRLH_CLKSRC_MASK 0x2u +#define WDOG_STCTRLH_CLKSRC_SHIFT 1 +#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u +#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 +#define WDOG_STCTRLH_WINEN_MASK 0x8u +#define WDOG_STCTRLH_WINEN_SHIFT 3 +#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u +#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 +#define WDOG_STCTRLH_DBGEN_MASK 0x20u +#define WDOG_STCTRLH_DBGEN_SHIFT 5 +#define WDOG_STCTRLH_STOPEN_MASK 0x40u +#define WDOG_STCTRLH_STOPEN_SHIFT 6 +#define WDOG_STCTRLH_WAITEN_MASK 0x80u +#define WDOG_STCTRLH_WAITEN_SHIFT 7 +#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u +#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 +#define WDOG_STCTRLH_TESTSEL_MASK 0x800u +#define WDOG_STCTRLH_TESTSEL_SHIFT 11 +#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u +#define WDOG_STCTRLH_BYTESEL_SHIFT 12 +#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))< MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */ + __IO uint32_t RMON_T_FRAG; /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */ + __IO uint32_t RMON_T_JAB; /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */ + __IO uint32_t RMON_T_COL; /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */ + __IO uint32_t RMON_T_P64; /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */ + __IO uint32_t RMON_T_P65TO127; /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */ + __IO uint32_t RMON_T_P128TO255; /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */ + __IO uint32_t RMON_T_P256TO511; /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */ + __IO uint32_t RMON_T_P512TO1023; /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */ + __IO uint32_t RMON_T_P1024TO2047; /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */ + __IO uint32_t RMON_T_P_GTE2048; /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */ + __IO uint32_t RMON_T_OCTETS; /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */ + __IO uint32_t IEEE_T_DROP; /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */ + __IO uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */ + __IO uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */ + __IO uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */ + __IO uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */ + __IO uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */ + __IO uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */ + __IO uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */ + __IO uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */ + __IO uint32_t IEEE_T_SQE; /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */ + __IO uint32_t IEEE_T_FDXFC; /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */ + __IO uint32_t IEEE_T_OCTETS_OK; /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */ + uint8_t RESERVED_14[12]; + __IO uint32_t RMON_R_PACKETS; /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */ + __IO uint32_t RMON_R_BC_PKT; /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */ + __IO uint32_t RMON_R_MC_PKT; /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */ + __IO uint32_t RMON_R_CRC_ALIGN; /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */ + __IO uint32_t RMON_R_UNDERSIZE; /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */ + __IO uint32_t RMON_R_OVERSIZE; /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */ + __IO uint32_t RMON_R_FRAG; /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */ + __IO uint32_t RMON_R_JAB; /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */ + __IO uint32_t RMON_R_RESVD_0; /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */ + __IO uint32_t RMON_R_P64; /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */ + __IO uint32_t RMON_R_P65TO127; /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */ + __IO uint32_t RMON_R_P128TO255; /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */ + __IO uint32_t RMON_R_P256TO511; /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */ + __IO uint32_t RMON_R_P512TO1023; /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */ + __IO uint32_t RMON_R_P1024TO2047; /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */ + __IO uint32_t RMON_R_P_GTE2048; /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */ + __IO uint32_t RMON_R_OCTETS; /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */ + __IO uint32_t RMON_R_DROP; /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */ + __IO uint32_t RMON_R_FRAME_OK; /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */ + __IO uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */ + __IO uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */ + __IO uint32_t IEEE_R_MACERR; /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */ + __IO uint32_t IEEE_R_FDXFC; /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */ + __IO uint32_t IEEE_R_OCTETS_OK; /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */ + uint8_t RESERVED_15[284]; + __IO uint32_t ATCR; /**< Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __IO uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_16[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/* EIR Bit Fields */ +#define ENET_EIR_TS_TIMER_MASK 0x8000u +#define ENET_EIR_TS_TIMER_SHIFT 15 +#define ENET_EIR_TS_AVAIL_MASK 0x10000u +#define ENET_EIR_TS_AVAIL_SHIFT 16 +#define ENET_EIR_WAKEUP_MASK 0x20000u +#define ENET_EIR_WAKEUP_SHIFT 17 +#define ENET_EIR_PLR_MASK 0x40000u +#define ENET_EIR_PLR_SHIFT 18 +#define ENET_EIR_UN_MASK 0x80000u +#define ENET_EIR_UN_SHIFT 19 +#define ENET_EIR_RL_MASK 0x100000u +#define ENET_EIR_RL_SHIFT 20 +#define ENET_EIR_LC_MASK 0x200000u +#define ENET_EIR_LC_SHIFT 21 +#define ENET_EIR_EBERR_MASK 0x400000u +#define ENET_EIR_EBERR_SHIFT 22 +#define ENET_EIR_MII_MASK 0x800000u +#define ENET_EIR_MII_SHIFT 23 +#define ENET_EIR_RXB_MASK 0x1000000u +#define ENET_EIR_RXB_SHIFT 24 +#define ENET_EIR_RXF_MASK 0x2000000u +#define ENET_EIR_RXF_SHIFT 25 +#define ENET_EIR_TXB_MASK 0x4000000u +#define ENET_EIR_TXB_SHIFT 26 +#define ENET_EIR_TXF_MASK 0x8000000u +#define ENET_EIR_TXF_SHIFT 27 +#define ENET_EIR_GRA_MASK 0x10000000u +#define ENET_EIR_GRA_SHIFT 28 +#define ENET_EIR_BABT_MASK 0x20000000u +#define ENET_EIR_BABT_SHIFT 29 +#define ENET_EIR_BABR_MASK 0x40000000u +#define ENET_EIR_BABR_SHIFT 30 +/* EIMR Bit Fields */ +#define ENET_EIMR_TS_TIMER_MASK 0x8000u +#define ENET_EIMR_TS_TIMER_SHIFT 15 +#define ENET_EIMR_TS_AVAIL_MASK 0x10000u +#define ENET_EIMR_TS_AVAIL_SHIFT 16 +#define ENET_EIMR_WAKEUP_MASK 0x20000u +#define ENET_EIMR_WAKEUP_SHIFT 17 +#define ENET_EIMR_PLR_MASK 0x40000u +#define ENET_EIMR_PLR_SHIFT 18 +#define ENET_EIMR_UN_MASK 0x80000u +#define ENET_EIMR_UN_SHIFT 19 +#define ENET_EIMR_RL_MASK 0x100000u +#define ENET_EIMR_RL_SHIFT 20 +#define ENET_EIMR_LC_MASK 0x200000u +#define ENET_EIMR_LC_SHIFT 21 +#define ENET_EIMR_EBERR_MASK 0x400000u +#define ENET_EIMR_EBERR_SHIFT 22 +#define ENET_EIMR_MII_MASK 0x800000u +#define ENET_EIMR_MII_SHIFT 23 +#define ENET_EIMR_RXB_MASK 0x1000000u +#define ENET_EIMR_RXB_SHIFT 24 +#define ENET_EIMR_RXF_MASK 0x2000000u +#define ENET_EIMR_RXF_SHIFT 25 +#define ENET_EIMR_TXB_MASK 0x4000000u +#define ENET_EIMR_TXB_SHIFT 26 +#define ENET_EIMR_TXF_MASK 0x8000000u +#define ENET_EIMR_TXF_SHIFT 27 +#define ENET_EIMR_GRA_MASK 0x10000000u +#define ENET_EIMR_GRA_SHIFT 28 +#define ENET_EIMR_BABT_MASK 0x20000000u +#define ENET_EIMR_BABT_SHIFT 29 +#define ENET_EIMR_BABR_MASK 0x40000000u +#define ENET_EIMR_BABR_SHIFT 30 +/* RDAR Bit Fields */ +#define ENET_RDAR_RDAR_MASK 0x1000000u +#define ENET_RDAR_RDAR_SHIFT 24 +/* TDAR Bit Fields */ +#define ENET_TDAR_TDAR_MASK 0x1000000u +#define ENET_TDAR_TDAR_SHIFT 24 +/* ECR Bit Fields */ +#define ENET_ECR_RESET_MASK 0x1u +#define ENET_ECR_RESET_SHIFT 0 +#define ENET_ECR_ETHEREN_MASK 0x2u +#define ENET_ECR_ETHEREN_SHIFT 1 +#define ENET_ECR_MAGICEN_MASK 0x4u +#define ENET_ECR_MAGICEN_SHIFT 2 +#define ENET_ECR_SLEEP_MASK 0x8u +#define ENET_ECR_SLEEP_SHIFT 3 +#define ENET_ECR_EN1588_MASK 0x10u +#define ENET_ECR_EN1588_SHIFT 4 +#define ENET_ECR_DBGEN_MASK 0x40u +#define ENET_ECR_DBGEN_SHIFT 6 +#define ENET_ECR_STOPEN_MASK 0x80u +#define ENET_ECR_STOPEN_SHIFT 7 +/* MMFR Bit Fields */ +#define ENET_MMFR_DATA_MASK 0xFFFFu +#define ENET_MMFR_DATA_SHIFT 0 +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))< + */ + +#ifndef CPU_CONF_H_ +#define CPU_CONF_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +#if defined(CPU_MODEL_K60DN512VLL10) || defined(CPU_MODEL_K60DN256VLL10) + +/* Rev. 2.x silicon */ +#define K60_CPU_REV 2 +#include "MK60D10.h" + +/** The expected CPUID value, can be used to implement a check that we are + * running on the right hardware */ +#define K60_EXPECTED_CPUID 0x410fc241u + +/* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */ +#define KINETIS_RNGA (RNG) + +#elif defined(CPU_MODEL_K60DN512ZVLL10) || defined(CPU_MODEL_K60DN256ZVLL10) + +/* Rev. 1.x silicon */ +#define K60_CPU_REV 1 +#include "MK60DZ10.h" + +/** The expected CPUID value, can be used to implement a check that we are + * running on the right hardware */ +#define K60_EXPECTED_CPUID 0x410fc240u + +/* K60 rev 1.x has the cryptographically strong RNGB module */ +#define KINETIS_RNGB (RNG) + +#else +#error Unknown CPU model. Update Makefile.include in the board directory. +#endif + +/* Compatibility definitions between the two different Freescale headers */ +#include "MK60-comp.h" + +/** + * @name GPIO pin mux function numbers + */ +/** @{ */ +#define PIN_MUX_FUNCTION_ANALOG 0 +#define PIN_MUX_FUNCTION_GPIO 1 +/** @} */ +/** + * @name GPIO interrupt flank settings + */ +/** @{ */ +#define PIN_INTERRUPT_RISING 0b1001 +#define PIN_INTERRUPT_FALLING 0b1010 +#define PIN_INTERRUPT_EDGE 0b1011 +/** @} */ +/** + * @name Kernel stack size configuration + * + * TODO: Tune this + * @{ + */ +#define KERNEL_CONF_STACKSIZE_PRINTF (1024) + +#ifndef KERNEL_CONF_STACKSIZE_DEFAULT +#define KERNEL_CONF_STACKSIZE_DEFAULT (1024) +#endif + +#define KERNEL_CONF_STACKSIZE_IDLE (256) +/** @} */ + +/** + * @name Length and address for reading CPU_ID (named UID in Freescale documents) + * @{ + */ +#define CPUID_ID_LEN (16) +#define CPUID_ID_PTR ((void *)(&(SIM->UIDH))) +/** @} */ + +#ifndef UART0_BUFSIZE +/** + * @brief UART0 buffer size definition for compatibility reasons + * + * TODO: remove once the remodeling of the uart0 driver is done + */ +#define UART0_BUFSIZE (128) +#endif + +/** + * @name UART driver settings + */ +/** @{ */ +/** UART typedef from CPU header. */ +#define KINETIS_UART UART_Type +/** @} */ + +/** + * @name Clock settings for the LPTMR0 timer + * @{ + */ +#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */ +#define LPTIMER_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1) /**< Enable LPTMR0 clock gate */ +#define LPTIMER_CLKDIS() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0) /**< Disable LPTMR0 clock gate */ +#define LPTIMER_CLKSRC_MCGIRCLK 0 /**< internal reference clock (4MHz) */ +#define LPTIMER_CLKSRC_LPO 1 /**< PMC 1kHz output */ +#define LPTIMER_CLKSRC_ERCLK32K 2 /**< RTC clock 32768Hz */ +#define LPTIMER_CLKSRC_OSCERCLK 3 /**< system oscillator output, clock from RF-Part */ + +#ifndef LPTIMER_CLKSRC +#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K /**< default clock source */ +#endif + +#if (LPTIMER_CLKSRC == LPTIMER_CLKSRC_MCGIRCLK) +#define LPTIMER_CLK_PRESCALE 1 +#define LPTIMER_SPEED 1000000 +#elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_OSCERCLK) +#define LPTIMER_CLK_PRESCALE 1 +#define LPTIMER_SPEED 1000000 +#elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_ERCLK32K) +#define LPTIMER_CLK_PRESCALE 0 +#define LPTIMER_SPEED 32768 +#else +#define LPTIMER_CLK_PRESCALE 0 +#define LPTIMER_SPEED 1000 +#endif + +/** IRQ priority for hwtimer interrupts */ +#define LPTIMER_IRQ_PRIO 1 +/** IRQ channel for hwtimer interrupts */ +#define LPTIMER_IRQ_CHAN LPTMR0_IRQn + +#if K60_CPU_REV == 1 +/* + * The CNR register latching in LPTMR0 was added in silicon rev 2.x. With + * rev 1.x we do not need to do anything in order to read the current timer counter + * value + */ +#define LPTIMER_CNR_NEEDS_LATCHING 0 + +#elif K60_CPU_REV == 2 + +#define LPTIMER_CNR_NEEDS_LATCHING 1 + +#endif +/** @} */ + +/** + * @name Power mode hardware details + */ +/** @{ */ +#if K60_CPU_REV == 1 +#define KINETIS_PMCTRL MC->PMCTRL +#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = MC_PMCTRL_LPLLSM(x) | MC_PMCTRL_LPWUI_MASK) +/* Clear LLS protection, clear VLPS, VLPW, VLPR protection */ +/* Note: This register can only be written once after each reset, so we must + * enable all power modes that we wish to use. */ +#define KINETIS_UNLOCK_PMPROT() (MC->PMPROT |= MC_PMPROT_ALLS_MASK | MC_PMPROT_AVLP_MASK) +#elif K60_CPU_REV == 2 +#define KINETIS_PMCTRL SMC->PMCTRL +#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK) +#define KINETIS_PMPROT_UNLOCK() (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK) +#else +#error Unknown K60 CPU revision! +#endif + +/** + * @name STOP mode bitfield values + * @{ + */ +/** @brief Normal STOP */ +#define KINETIS_POWER_MODE_NORMAL (0b000) +/** @brief VLPS STOP */ +#define KINETIS_POWER_MODE_VLPS (0b010) +/** @brief LLS STOP */ +#define KINETIS_POWER_MODE_LLS (0b011) +/** @} */ + +/** + * @brief Wake up source number for the LPTMR0 + * + * In order to let the hwtimer wake the CPU from low power modes, we need to + * enable this wake up source. + */ +#define KINETIS_LLWU_WAKEUP_MODULE_LPTMR 0 + +/** + * @brief IRQn name to enable LLWU IRQ in NVIC + */ +#define KINETIS_LLWU_IRQ LLW_IRQn + +/** + * @brief Enable clock gate on LLWU module. + */ +#define LLWU_UNLOCK() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1) + +/** + * @brief Internal modules whose interrupts are mapped to LLWU wake up sources. + * + * Other modules CAN NOT be used to wake the CPU from LLS or VLLSx power modes. + */ +typedef enum llwu_wakeup_module { + KINETIS_LPM_WAKEUP_MODULE_LPTMR = 0, + KINETIS_LPM_WAKEUP_MODULE_CMP0 = 1, + KINETIS_LPM_WAKEUP_MODULE_CMP1 = 2, + KINETIS_LPM_WAKEUP_MODULE_CMP2 = 3, + KINETIS_LPM_WAKEUP_MODULE_TSI = 4, + KINETIS_LPM_WAKEUP_MODULE_RTC_ALARM = 5, + KINETIS_LPM_WAKEUP_MODULE_RESERVED = 6, + KINETIS_LPM_WAKEUP_MODULE_RTC_SECONDS = 7, + KINETIS_LPM_WAKEUP_MODULE_END, +} llwu_wakeup_module_t; + +/** + * @brief enum that maps physical pins to wakeup pin numbers in LLWU module + * + * Other pins CAN NOT be used to wake the CPU from LLS or VLLSx power modes. + */ +typedef enum llwu_wakeup_pin { + KINETIS_LPM_WAKEUP_PIN_PTE1 = 0, + KINETIS_LPM_WAKEUP_PIN_PTE2 = 1, + KINETIS_LPM_WAKEUP_PIN_PTE4 = 2, + KINETIS_LPM_WAKEUP_PIN_PTA4 = 3, + KINETIS_LPM_WAKEUP_PIN_PTA13 = 4, + KINETIS_LPM_WAKEUP_PIN_PTB0 = 5, + KINETIS_LPM_WAKEUP_PIN_PTC1 = 6, + KINETIS_LPM_WAKEUP_PIN_PTC3 = 7, + KINETIS_LPM_WAKEUP_PIN_PTC4 = 8, + KINETIS_LPM_WAKEUP_PIN_PTC5 = 9, + KINETIS_LPM_WAKEUP_PIN_PTC6 = 10, + KINETIS_LPM_WAKEUP_PIN_PTC11 = 11, + KINETIS_LPM_WAKEUP_PIN_PTD0 = 12, + KINETIS_LPM_WAKEUP_PIN_PTD2 = 13, + KINETIS_LPM_WAKEUP_PIN_PTD4 = 14, + KINETIS_LPM_WAKEUP_PIN_PTD6 = 15, + KINETIS_LPM_WAKEUP_PIN_END +} llwu_wakeup_pin_t; + +/** @} */ + +/** @name K60 PORT ISR names + * @{ */ +#define ISR_PORT_A isr_porta_pin_detect +#define ISR_PORT_B isr_portb_pin_detect +#define ISR_PORT_C isr_portc_pin_detect +#define ISR_PORT_D isr_portd_pin_detect +#define ISR_PORT_E isr_porte_pin_detect +/** @} */ + +/** @brief Number of packets in transceiver queue */ +#define TRANSCEIVER_BUFFER_SIZE (3) + +/** + * @name Bit band macros + * @{ + */ +/* Generic bitband conversion routine */ +/** @brief Convert bit-band region address and bit number to bit-band alias address + * + * @param[in] addr base address in non-bit-banded memory + * @param[in] bit bit number within the word + * + * @return Address of the bit within the bit-band memory region + */ +#define BITBAND_ADDR(addr, bit) ((((uint32_t) (addr)) & 0xF0000000u) + 0x2000000 + ((((uint32_t) (addr)) & 0xFFFFF) << 5) + ((bit) << 2)) + +/** + * @brief Bitband 32 bit access to variable stored in SRAM_U + * + * @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up) + * @note var must be declared 'volatile' + */ +#define BITBAND_VAR32(var, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(var), (bit)))) + +/** + * @brief Bitband 16 bit access to variable stored in SRAM_U + * + * @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up) + * @note var must be declared 'volatile' + */ +#define BITBAND_VAR16(var, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(var), (bit)))) + +/** + * @brief Bitband 8 bit access to variable stored in SRAM_U + * + * @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up) + * @note var must be declared 'volatile' + */ +#define BITBAND_VAR8(var, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit)))) + +/** + * @brief Bitband 32 bit access to peripheral register + */ +#define BITBAND_PERIPH32(reg, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(reg), (bit)))) + +/** + * @brief Bitband 16 bit access to peripheral register + */ +#define BITBAND_PERIPH16(reg, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(reg), (bit)))) + +/** + * @brief Bitband 8 bit access to peripheral register + */ +#define BITBAND_PERIPH8(reg, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(reg), (bit)))) + +/** @} */ +#ifdef __cplusplus +} +#endif + +#endif /* CPU_CONF_H_ */ +/** @} */ diff --git a/cpu/k60/include/devio-null.h b/cpu/k60/include/devio-null.h new file mode 100644 index 0000000000..e6d161e211 --- /dev/null +++ b/cpu/k60/include/devio-null.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Device I/O helpers for a no-op device. + * + * @author Joakim Gebart + */ +#ifndef DEVIO_NULL_H_ +#define DEVIO_NULL_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +int devnull_open_r(struct _reent *r, const char *path, int flags, int mode); +int devnull_close_r(struct _reent *r, int fd); +long devnull_write_r(struct _reent *r, int fd, const char *ptr, int len); +long devnull_read_r(struct _reent *r, int fd, char *ptr, int len); +long devnull_lseek_r(struct _reent *r, int fd, int ptr, int dir); +long devnull_fstat_r(struct _reent *r, int fd, char *ptr, int len); + +#ifdef __cplusplus +} +#endif + +#endif /* !defined(DEVIO_NULL_H_) */ +/** @} */ diff --git a/cpu/k60/include/devio-uart.h b/cpu/k60/include/devio-uart.h new file mode 100644 index 0000000000..a6fa143049 --- /dev/null +++ b/cpu/k60/include/devio-uart.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +#include + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Device I/O helpers for UARTs on K60. + * + * @author Joakim Gebart + */ +#ifndef DEVIO_UART_H_ +#define DEVIO_UART_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +long uart0_write_r(struct _reent *r, int fd, const char *ptr, int len); +long uart1_write_r(struct _reent *r, int fd, const char *ptr, int len); +long uart2_write_r(struct _reent *r, int fd, const char *ptr, int len); +long uart3_write_r(struct _reent *r, int fd, const char *ptr, int len); +long uart4_write_r(struct _reent *r, int fd, const char *ptr, int len); +long uart0_read_r(struct _reent *r, int fd, char *ptr, int len); + +#ifdef __cplusplus +} +#endif + +#endif /* !defined(DEVIO_UART_H_) */ +/** @} */ diff --git a/cpu/k60/include/devopttab.h b/cpu/k60/include/devopttab.h new file mode 100644 index 0000000000..9575da065f --- /dev/null +++ b/cpu/k60/include/devopttab.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +#include +#include +#include +#include +#include + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Device operations table. + * + * @author Joakim Gebart + */ +#ifndef DEVOPTTAB_H_ +#define DEVOPTTAB_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief Device operations table + * + * Inspired by http://neptune.billgatliff.com/newlib.html + * + * A simple "device operations" table, with function pointers for all the kinds + * of activities you would expect a stream-like device to support. + */ +typedef struct { + const char *name; /**< Device filename */ + const int isatty; /**< isatty() return code (usually 0 or 1) */ + const int st_mode; /**< st_mode code, see man 2 stat */ + int (*open_r)(struct _reent *r, const char *path, int flags, + int mode); /**< pointer to open() function for this device */ + int (*close_r)(struct _reent *r, int fd); /**< pointer to close() function for this device */ + long(*write_r)(struct _reent *r, int fd, const char *ptr, + int len); /**< pointer to write() function for this device */ + long(*read_r)(struct _reent *r, int fd, char *ptr, + int len); /**< pointer to read() function for this device */ + long(*lseek_r)(struct _reent *r, int fd, int ptr, + int dir); /**< pointer to lseek() function for this device */ + long(*fstat_r)(struct _reent *r, int fd, char *ptr, + int len); /**< pointer to fstat() function for this device */ +} devoptab_t; + +#ifdef __cplusplus +} +#endif + +#endif +/** @} */ diff --git a/cpu/k60/include/hwtimer_cpu.h b/cpu/k60/include/hwtimer_cpu.h new file mode 100644 index 0000000000..7eb9bbdd25 --- /dev/null +++ b/cpu/k60/include/hwtimer_cpu.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief CPU specific hwtimer configuration options + * + * @author Hauke Petersen + */ + +#ifndef HWTIMER_CPU_H_ +#define HWTIMER_CPU_H_ + +#include "cpu.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @name Hardware timer configuration + * @{ + */ +#define HWTIMER_MAXTIMERS 1 /**< the HW timer is using the LPTMR as its hardware timer */ +#define HWTIMER_SPEED 32768 /**< LPTMR is running at 32.768 kHz */ +#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< Virtually extended to 32 bits from 16 bits hardware counter. */ +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* HWTIMER_CPU_H_ */ +/** @} */ diff --git a/cpu/k60/include/system_MK60D10.h b/cpu/k60/include/system_MK60D10.h new file mode 100644 index 0000000000..386b566057 --- /dev/null +++ b/cpu/k60/include/system_MK60D10.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +#ifndef SYSTEM_MK60D10_H_ +#define SYSTEM_MK60D10_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Device specific configuration file for MK60D10 (header file) + */ + + +/** + * \brief Current core clock frequency + * + * MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex-M4 core. + */ +extern uint32_t SystemCoreClock; + +/** + * \brief Current system clock frequency + * + * MCGOUTCLK divided by OUTDIV1 clocks the crossbar switch and bus masters + * directly connected to the crossbar. In addition, this clock is used for UART0 + * and UART1. + */ +extern uint32_t SystemSysClock; + +/** + * \brief Current bus clock frequency + * + * MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding + * memories). + */ +extern uint32_t SystemBusClock; + +/** + * \brief Current FlexBus clock frequency + * + * MCGOUTCLK divided by OUTDIV3 clocks the external FlexBus interface. + */ +extern uint32_t SystemFlexBusClock; + +/** + * \brief Current flash clock frequency + * + * MCGOUTCLK divided by OUTDIV4 clocks the flash memory. + */ +extern uint32_t SystemFlashClock; + +/** + * \brief Updates all of the SystemCoreClock variables. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and + * calculates the current core clock. + */ +void SystemCoreClockUpdate(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if !defined(SYSTEM_MK60D10_H_) */ diff --git a/cpu/k60/include/system_MK60DZ10.h b/cpu/k60/include/system_MK60DZ10.h new file mode 120000 index 0000000000..a630726e25 --- /dev/null +++ b/cpu/k60/include/system_MK60DZ10.h @@ -0,0 +1 @@ +system_MK60D10.h \ No newline at end of file diff --git a/cpu/k60/interrupt_vector.c b/cpu/k60/interrupt_vector.c new file mode 100644 index 0000000000..623fc57f9f --- /dev/null +++ b/cpu/k60/interrupt_vector.c @@ -0,0 +1,490 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * + * @brief Interrupt vector for K60 MCU. + * + * @author Joakim Gebart + * + * @note It is not necessary to modify this file to define custom interrupt + * service routines. All symbols are defined weak, it is only necessary to + * define a function with the same name in another file to override the default + * interrupt handlers. + */ + +/** + * @name Interrupt vector definition + * @{ + */ + +#include "cpu.h" +#include "fault_handlers.h" +#include "wdog.h" + +extern void *_estack[]; +extern void *_sstack[]; + +typedef void (*ISR_func)(void); + + +/** + * @brief Unconditional jump to isr_unhandled() + * + * This function is only necessary since we can not declare weak aliases to + * functions outside the translation unit (.c-file). The default isr_unhandled() + * is defined in kinetis_common/fault_handlers.c. + */ +void isr_default_handler(void) __attribute__((naked)); + +void isr_default_handler(void) +{ + __ASM volatile ("b isr_unhandled\n"); +} + +/** + * @brief Early reset handler used to instrument the stack before it becomes in use. + * + * This function will fill the interrupt context-stack with canary values so + * that it can be checked to measure stack usage, similar to CREATE_STACKTEST in + * @ref thread_create + */ +void pre_reset_handler(void); + +/** @brief Interrupt stack canary value + * + * @note 0xe7fe is the ARM Thumb machine code equivalent of asm("bl #-2\n") or + * 'while (1);', i.e. an infinite loop. + */ +#define STACK_CANARY_WORD 0xE7FEE7FEu + +void pre_reset_handler(void) +{ + /* + * Important: Keep this function as simple as possible, we must not use any + * stack space or we will crash, since we will overwrite all of the stack. + */ + /* Disable watchdog first, it is necessary to do within 256 cycles. + * After this we will completely overwrite the stack so all necessary + * variables must be stored in registers or as immediate values in the + * machine code. */ + wdog_disable(); + /* + * The register keyword suggests to the compiler to place the variable in a + * register instead of on the stack. Using the register keyword is not a + * guarantee that the variable will be placed in a register. However, this + * function has been verified manually by disassembling the GCC output to + * ensure no stack is being used until after the write loop is finished. + */ + register uint32_t *p; + + /* Fill stack space with canary values */ + for (p = (uint32_t *)_sstack; p < (uint32_t *)_estack; ++p) { + *p = STACK_CANARY_WORD; + } + + /* Now launch the real reset handler. */ + __ASM volatile("b reset_handler\n"); + + /* reset_handler should never return */ + while (1); +} + +#define ISR_VECTOR_SECTION __attribute__ ((used,section(".vector_table"))) + +#define UNHANDLED_ALIAS __attribute__((weak, alias("isr_default_handler"))); + +/* ARM Cortex defined interrupt vectors */ +/** + * @brief Default reset handler. + */ +void reset_handler(void) __attribute__((naked)); +void isr_nmi(void) UNHANDLED_ALIAS; +void isr_hard_fault(void) UNHANDLED_ALIAS; +void isr_mem_manage(void) UNHANDLED_ALIAS; +void isr_bus_fault(void) UNHANDLED_ALIAS; +void isr_usage_fault(void) UNHANDLED_ALIAS; +void isr_reserved(void) UNHANDLED_ALIAS; +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +void isr_svc(void) UNHANDLED_ALIAS; +void isr_debug_mon(void) UNHANDLED_ALIAS; +/* void _isr_reserved(void) UNHANDLED_ALIAS; */ +void isr_pendsv(void) UNHANDLED_ALIAS; +void isr_systick(void) UNHANDLED_ALIAS; + +/* device-specific (freescale) defined interrupt vectors */ +void isr_dma0_complete(void) UNHANDLED_ALIAS; +void isr_dma1_complete(void) UNHANDLED_ALIAS; +void isr_dma2_complete(void) UNHANDLED_ALIAS; +void isr_dma3_complete(void) UNHANDLED_ALIAS; +void isr_dma4_complete(void) UNHANDLED_ALIAS; +void isr_dma5_complete(void) UNHANDLED_ALIAS; +void isr_dma6_complete(void) UNHANDLED_ALIAS; +void isr_dma7_complete(void) UNHANDLED_ALIAS; +void isr_dma8_complete(void) UNHANDLED_ALIAS; +void isr_dma9_complete(void) UNHANDLED_ALIAS; +void isr_dma10_complete(void) UNHANDLED_ALIAS; +void isr_dma11_complete(void) UNHANDLED_ALIAS; +void isr_dma12_complete(void) UNHANDLED_ALIAS; +void isr_dma13_complete(void) UNHANDLED_ALIAS; +void isr_dma14_complete(void) UNHANDLED_ALIAS; +void isr_dma15_complete(void) UNHANDLED_ALIAS; +void isr_dma_error(void) UNHANDLED_ALIAS; +void isr_mcm(void) UNHANDLED_ALIAS; +void isr_flash_command_complete(void) UNHANDLED_ALIAS; +void isr_flash_read_collision(void) UNHANDLED_ALIAS; +void isr_low_voltage(void) UNHANDLED_ALIAS; +void isr_llwu(void) UNHANDLED_ALIAS; +void isr_watchdog(void) UNHANDLED_ALIAS; +void isr_random_number_generator(void) UNHANDLED_ALIAS; +void isr_i2c0(void) UNHANDLED_ALIAS; +void isr_i2c1(void) UNHANDLED_ALIAS; +void isr_spi0(void) UNHANDLED_ALIAS; +void isr_spi1(void) UNHANDLED_ALIAS; +void isr_spi2(void) UNHANDLED_ALIAS; +void isr_can0_ored_msg_buffer(void) UNHANDLED_ALIAS; +void isr_can0_bus_off(void) UNHANDLED_ALIAS; +void isr_can0_error(void) UNHANDLED_ALIAS; +void isr_can0_tx_warn(void) UNHANDLED_ALIAS; +void isr_can0_rx_warn(void) UNHANDLED_ALIAS; +void isr_can0_wake_up(void) UNHANDLED_ALIAS; +void isr_i2s0_tx(void) UNHANDLED_ALIAS; +void isr_i2s0_rx(void) UNHANDLED_ALIAS; +void isr_can1_ored_msg_buffer(void) UNHANDLED_ALIAS; +void isr_can1_bus_off(void) UNHANDLED_ALIAS; +void isr_can1_error(void) UNHANDLED_ALIAS; +void isr_can1_tx_warn(void) UNHANDLED_ALIAS; +void isr_can1_rx_warn(void) UNHANDLED_ALIAS; +void isr_can1_wake_up(void) UNHANDLED_ALIAS; +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +void isr_uart0_lon(void) UNHANDLED_ALIAS; +void isr_uart0_status(void) UNHANDLED_ALIAS; +void isr_uart0_error(void) UNHANDLED_ALIAS; +void isr_uart1_status(void) UNHANDLED_ALIAS; +void isr_uart1_error(void) UNHANDLED_ALIAS; +void isr_uart2_status(void) UNHANDLED_ALIAS; +void isr_uart2_error(void) UNHANDLED_ALIAS; +void isr_uart3_status(void) UNHANDLED_ALIAS; +void isr_uart3_error(void) UNHANDLED_ALIAS; +void isr_uart4_status(void) UNHANDLED_ALIAS; +void isr_uart4_error(void) UNHANDLED_ALIAS; +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +void isr_adc0(void) UNHANDLED_ALIAS; +void isr_adc1(void) UNHANDLED_ALIAS; +void isr_cmp0(void) UNHANDLED_ALIAS; +void isr_cmp1(void) UNHANDLED_ALIAS; +void isr_cmp2(void) UNHANDLED_ALIAS; +void isr_ftm0(void) UNHANDLED_ALIAS; +void isr_ftm1(void) UNHANDLED_ALIAS; +void isr_ftm2(void) UNHANDLED_ALIAS; +void isr_cmt(void) UNHANDLED_ALIAS; +void isr_rtc_alarm(void) UNHANDLED_ALIAS; +void isr_rtc_seconds(void) UNHANDLED_ALIAS; +void isr_pit0(void) UNHANDLED_ALIAS; +void isr_pit1(void) UNHANDLED_ALIAS; +void isr_pit2(void) UNHANDLED_ALIAS; +void isr_pit3(void) UNHANDLED_ALIAS; +void isr_pdb(void) UNHANDLED_ALIAS; +void isr_usb_otg(void) UNHANDLED_ALIAS; +void isr_usb_charger_detect(void) UNHANDLED_ALIAS; +void isr_enet_1588_timer(void) UNHANDLED_ALIAS; +void isr_enet_tx(void) UNHANDLED_ALIAS; +void isr_enet_rx(void) UNHANDLED_ALIAS; +void isr_enet_error_misc(void) UNHANDLED_ALIAS; +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +void isr_sdhc(void) UNHANDLED_ALIAS; +void isr_dac0(void) UNHANDLED_ALIAS; +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +void isr_tsi(void) UNHANDLED_ALIAS; +void isr_mcg(void) UNHANDLED_ALIAS; +void isr_lptmr0(void) UNHANDLED_ALIAS; +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +void isr_porta_pin_detect(void) UNHANDLED_ALIAS; +void isr_portb_pin_detect(void) UNHANDLED_ALIAS; +void isr_portc_pin_detect(void) UNHANDLED_ALIAS; +void isr_portd_pin_detect(void) UNHANDLED_ALIAS; +void isr_porte_pin_detect(void) UNHANDLED_ALIAS; +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +/* void isr_reserved(void) UNHANDLED_ALIAS; */ +void isr_software(void) UNHANDLED_ALIAS; + +/** + * @brief Interrupt vector definition + */ +const ISR_func isr_vector[256] ISR_VECTOR_SECTION = { + /* ARM Cortex defined interrupt vectors */ + (ISR_func)_estack, + pre_reset_handler, + isr_nmi, + isr_hard_fault, + isr_mem_manage, + isr_bus_fault, + isr_usage_fault, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_svc, + isr_debug_mon, + isr_reserved, + isr_pendsv, + isr_systick, + + /* Device-specific (Freescale defined) interrupt vectors */ + isr_dma0_complete, + isr_dma1_complete, + isr_dma2_complete, + isr_dma3_complete, + isr_dma4_complete, + isr_dma5_complete, + isr_dma6_complete, + isr_dma7_complete, + isr_dma8_complete, + isr_dma9_complete, + isr_dma10_complete, + isr_dma11_complete, + isr_dma12_complete, + isr_dma13_complete, + isr_dma14_complete, + isr_dma15_complete, + isr_dma_error, + isr_mcm, + isr_flash_command_complete, + isr_flash_read_collision, + isr_low_voltage, + isr_llwu, + isr_watchdog, + isr_random_number_generator, + isr_i2c0, + isr_i2c1, + isr_spi0, + isr_spi1, + isr_spi2, + isr_can0_ored_msg_buffer, + isr_can0_bus_off, + isr_can0_error, + isr_can0_tx_warn, + isr_can0_rx_warn, + isr_can0_wake_up, + isr_i2s0_tx, + isr_i2s0_rx, + isr_can1_ored_msg_buffer, + isr_can1_bus_off, + isr_can1_error, + isr_can1_tx_warn, + isr_can1_rx_warn, + isr_can1_wake_up, + isr_reserved, + isr_uart0_lon, + isr_uart0_status, + isr_uart0_error, + isr_uart1_status, + isr_uart1_error, + isr_uart2_status, + isr_uart2_error, + isr_uart3_status, + isr_uart3_error, + isr_uart4_status, + isr_uart4_error, + isr_reserved, + isr_reserved, + isr_adc0, + isr_adc1, + isr_cmp0, + isr_cmp1, + isr_cmp2, + isr_ftm0, + isr_ftm1, + isr_ftm2, + isr_cmt, + isr_rtc_alarm, + isr_rtc_seconds, + isr_pit0, + isr_pit1, + isr_pit2, + isr_pit3, + isr_pdb, + isr_usb_otg, + isr_usb_charger_detect, + isr_enet_1588_timer, + isr_enet_tx, + isr_enet_rx, + isr_enet_error_misc, + isr_reserved, + isr_sdhc, + isr_dac0, + isr_reserved, + isr_tsi, + isr_mcg, + isr_lptmr0, + isr_reserved, + isr_porta_pin_detect, + isr_portb_pin_detect, + isr_portc_pin_detect, + isr_portd_pin_detect, + isr_porte_pin_detect, + isr_reserved, + isr_reserved, + isr_software, /* Vector 110 */ + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved, + isr_reserved /* vector 255 */ +}; + +/** @} */ + +/** @} */ diff --git a/cpu/k60/ldscripts/K60DN256VLL10.ld b/cpu/k60/ldscripts/K60DN256VLL10.ld new file mode 100644 index 0000000000..bd0ac875dd --- /dev/null +++ b/cpu/k60/ldscripts/K60DN256VLL10.ld @@ -0,0 +1,13 @@ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +MEMORY +{ + vectors (rx) : ORIGIN = 0x0, LENGTH = 0x400 + flashsec (rx) : ORIGIN = 0x400, LENGTH = 0x10 + flash (rx) : ORIGIN = 0x410, LENGTH = 256K - 0x410 + sram_l (rwx) : ORIGIN = 0x20000000 - 32K, LENGTH = 32K /* Only accessible via code bus. */ + sram_u (rwx) : ORIGIN = 0x20000000, LENGTH = 32K /* Only accessible via system bus. */ +} + +INCLUDE kinetis-base.ld diff --git a/cpu/k60/ldscripts/K60DN256ZVLL10.ld b/cpu/k60/ldscripts/K60DN256ZVLL10.ld new file mode 120000 index 0000000000..75fccf5901 --- /dev/null +++ b/cpu/k60/ldscripts/K60DN256ZVLL10.ld @@ -0,0 +1 @@ +K60DN256VLL10.ld \ No newline at end of file diff --git a/cpu/k60/ldscripts/K60DN512VLL10.ld b/cpu/k60/ldscripts/K60DN512VLL10.ld new file mode 100644 index 0000000000..225f2996b8 --- /dev/null +++ b/cpu/k60/ldscripts/K60DN512VLL10.ld @@ -0,0 +1,13 @@ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +MEMORY +{ + vectors (rx) : ORIGIN = 0x0, LENGTH = 0x400 + flashsec (rx) : ORIGIN = 0x400, LENGTH = 0x10 + flash (rx) : ORIGIN = 0x410, LENGTH = 512K - 0x410 + sram_l (rwx) : ORIGIN = 0x20000000 - 64K, LENGTH = 64K /* Only accessible via code bus. */ + sram_u (rwx) : ORIGIN = 0x20000000, LENGTH = 64K /* Only accessible via system bus. */ +} + +INCLUDE kinetis-base.ld diff --git a/cpu/k60/ldscripts/K60DN512ZVLL10.ld b/cpu/k60/ldscripts/K60DN512ZVLL10.ld new file mode 120000 index 0000000000..5b7e909aba --- /dev/null +++ b/cpu/k60/ldscripts/K60DN512ZVLL10.ld @@ -0,0 +1 @@ +K60DN512VLL10.ld \ No newline at end of file diff --git a/cpu/k60/lpm_arch.c b/cpu/k60/lpm_arch.c new file mode 100644 index 0000000000..55e8b0c1a8 --- /dev/null +++ b/cpu/k60/lpm_arch.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2014 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Implementation of the kernel's power management interface + * + * @author Joakim Gebart + * + * @} + */ + +#include "cpu.h" +#include "arch/lpm_arch.h" + +static inline void wait(void) +{ + /* Clear the SLEEPDEEP bit to make sure we go into WAIT (sleep) mode instead + * of deep sleep. + */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* WFI instruction will start entry into WAIT mode */ + __WFI(); +} + +void lpm_arch_init(void) +{ + /* Stub waiting for https://github.com/RIOT-OS/RIOT/pull/2605 */ +} + +enum lpm_mode lpm_arch_set(enum lpm_mode target) +{ + switch (target) { + case LPM_ON: + /* MCU is active, do not go to low power */ + break; + + case LPM_IDLE: + case LPM_SLEEP: + case LPM_POWERDOWN: + case LPM_OFF: + wait(); + break; + + case LPM_UNKNOWN: + default: + break; + } + + return 0; +} + +enum lpm_mode lpm_arch_get(void) +{ + /* TODO */ + return LPM_ON; +} + +void lpm_arch_awake(void) +{ + /* TODO */ +} + +void lpm_arch_begin_awake(void) +{ + /* TODO */ +} + +void lpm_arch_end_awake(void) +{ + /* TODO */ +} diff --git a/cpu/k60/periph/Makefile b/cpu/k60/periph/Makefile new file mode 100644 index 0000000000..6d1887b640 --- /dev/null +++ b/cpu/k60/periph/Makefile @@ -0,0 +1,3 @@ +MODULE = periph + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/k60/ssp.c b/cpu/k60/ssp.c new file mode 100644 index 0000000000..a64bcbf58d --- /dev/null +++ b/cpu/k60/ssp.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +#include "cpu.h" + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Implementation of stack smashing protection helper functions used by GCC's -fstack-protector + * + * @author Joakim Gebart + */ + +void *__stack_chk_guard = 0; + +void __stack_chk_guard_setup(void) +{ + unsigned char *p; + p = (unsigned char *) &__stack_chk_guard; + + /* TODO: This should be replaced by a random number to use as a canary value */ + p[0] = 0; + p[1] = 0; + p[2] = '\n'; + p[3] = 255; +} + +/* + * Arrange so that the __stack_chk_guard_setup function is called during + * early init. + */ +void __attribute__((section(".preinit_array")))(*preinit__stack_chk_guard_setup[])(void) = {__stack_chk_guard_setup}; + +/** + * @brief Handler for stack smashing protection failure. + * + * This is called if the SSP checks fail, which means that the stack has been + * corrupted. + */ +void __attribute__((noreturn)) __stack_chk_fail(void) +{ + asm volatile ("bkpt #1"); + + while (1); +} +/** @} */ diff --git a/cpu/k60/syscalls.c b/cpu/k60/syscalls.c new file mode 100644 index 0000000000..94ad9ca96b --- /dev/null +++ b/cpu/k60/syscalls.c @@ -0,0 +1,609 @@ +/* + * Copyright (C) 2015 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpu.h" +#include "board.h" +#include "devopttab.h" +#include "devicemap.h" +#include "thread.h" +#if CFS_ENABLED +#include "cfs.h" +#endif /* CFS_ENABLED */ +#include "mutex.h" +#include "ringbuffer.h" +#include "periph/uart.h" +#ifdef MODULE_UART0 +#include "board_uart0.h" +#endif + +/** + * @ingroup cpu_k60 + * @{ + * + * @file + * @brief Syscall implementations for K60 CPU. + * + * @author Joakim Gebart + */ + + +/* Empty environment definition */ +char *__env[1] = { 0 }; +char **environ = __env; + +/* Lock variable used to protect sbrk_r from clobbering the break variable when + * called simultaneously from more than one thread. */ +static mutex_t sbrk_mutex = MUTEX_INIT; + +/* Align all sbrk arguments to this many bytes */ +#define DYNAMIC_MEMORY_ALIGN 4 + +#ifndef MODULE_UART0 +/** + * @brief use mutex for waiting on incoming UART chars + */ +static mutex_t uart_rx_mutex; +static char rx_buf_mem[STDIO_RX_BUFSIZE]; +static ringbuffer_t rx_buf; +#endif + +/** + * @brief Receive a new character from the UART and put it into the receive buffer + */ +static void stdio_rx_cb(void *arg, char data) +{ +#ifndef MODULE_UART0 + (void)arg; + + ringbuffer_add_one(&rx_buf, data); + mutex_unlock(&uart_rx_mutex); +#else + + if (uart0_handler_pid) { + uart0_handle_incoming(data); + + uart0_notify_thread(); + } + +#endif +} + +/** + * @brief Initialize NewLib, called by __libc_init_array() from the startup script + */ +void _init(void) +{ +#ifndef MODULE_UART0 + mutex_init(&uart_rx_mutex); + ringbuffer_init(&rx_buf, rx_buf_mem, STDIO_RX_BUFSIZE); +#endif + uart_init(STDIO, STDIO_BAUDRATE, stdio_rx_cb, 0, 0); +} + +/** + * @brief Free resources on NewLib de-initialization, not used for RIOT + */ +void _fini(void) +{ + /* nothing to do here */ +} + + +/* ************************ */ +/* Process control syscalls */ +/* ************************ */ + +void +_exit(int code) +{ +#if DEVELHELP + volatile int status; /* volatile to prevent optimizations to remove the variable from memory */ + status = code; + (void)status; /* Suppress compiler warnings about unused variable */ + + /* See local variable `status` during debugger break. */ + asm volatile ("bkpt #0"); +#else + NVIC_SystemReset(); +#endif + + while (1); +} + +int +_fork_r(struct _reent *r) +{ + /* return "not supported" */ + r->_errno = ENOTSUP; + return -1; +} + +int +_execve_r(struct _reent *r, const char *name, char *const *argv, char *const *env) +{ + /* Not supported */ + (void)name; /* Suppress compiler warnings about unused parameters */ + (void)argv; + (void)env; + + r->_errno = ENOMEM; + return -1; +} + +int +_kill_r(struct _reent *r, int pid, int sig) +{ + /* Not supported */ + (void)pid; /* Suppress compiler warnings about unused parameters */ + (void)sig; + + r->_errno = EINVAL; + return -1; +} + +pid_t +_getpid(void) +{ + return sched_active_pid; +} + +pid_t +_getpid_r(struct _reent *ptr) +{ + (void) ptr; + return sched_active_pid; +} + +clock_t +_times_r(struct _reent *r, struct tms *buf) +{ + /* Not supported, yet */ + (void)buf; /* Suppress compiler warnings about unused parameters */ + + r->_errno = EACCES; + return -1; +} + +int +_wait_r(struct _reent *r, int *status) +{ + /* Not supported, yet */ + (void)status; /* Suppress compiler warnings about unused parameters */ + + r->_errno = ECHILD; + return -1; +} + +/* ******************************** */ +/* File descriptor related syscalls */ +/* ******************************** */ + +/** + * @brief Internal helper for generating FDs + * + * @return An unallocated file descriptor, -1 if no free FD can be found. + */ +static int get_next_dev_fd(void); + +static int get_next_dev_fd(void) +{ + int fd; + + for (fd = 0; fd < MAX_OPEN_DEVICES; ++fd) { + if (devoptab_list[fd] == NULL) { + return fd; + } + } + + return -1; +} + +int +_open_r(struct _reent *r, const char *name, int flags, int mode) +{ + unsigned int i; + int fd; +#if CFS_ENABLED + int cfs_flags = 0; +#endif + + /* Search for devices */ + for (i = 0; i < devoptab_name_list.len; ++i) { + if (strcmp(devoptab_name_list.data[i].name, name) == 0) { + /* Device found */ + fd = get_next_dev_fd(); + + if (fd < 0) { + /* No free FDs. */ + /* ENFILE means too many file descriptors open, system-wide. */ + r->_errno = ENFILE; + return -1; + } + + /* Set up device operations table and call open method */ + devoptab_list[fd] = devoptab_name_list.data[i].devoptab; + /* open_r method is mandatory */ + devoptab_list[fd]->open_r(r, name, flags, mode); + return fd; + } + } + +#if CFS_ENABLED + + /* Not a device name, try searching for files. */ + /* Translate POSIX O_* flags to CFS */ + if (flags & O_APPEND) { + cfs_flags |= CFS_APPEND; + } + + if (flags & O_RDWR) { + cfs_flags |= CFS_READ | CFS_WRITE; + } + + if (flags & O_RDONLY) { + cfs_flags |= CFS_READ; + } + + if (flags & O_WRONLY) { + cfs_flags |= CFS_WRITE; + } + + fd = cfs_open(name, cfs_flags); + + if (fd < 0) { + /* Not found or whatever, CFS doesn't tell us why it failed. */ + r->_errno = ENOENT; + return -1; + } + + fd += MAX_OPEN_DEVICES; /* Remap from CFS FD number */ + return fd; +#else + r->_errno = ENOENT; + return -1; +#endif + +} + +int +_close_r(struct _reent *r, int fd) +{ + int ret; + + if (fd < 0) { + /* invalid file descriptor */ + r->_errno = EBADF; + return -1; + } + + if (fd >= MAX_OPEN_DEVICES) { +#if CFS_ENABLED + /* CFS file */ + fd -= MAX_OPEN_DEVICES; /* Remap to CFS FD number */ + cfs_close(fd); +#endif + return 0; /* cfs_close does not indicate failures */ + } + + if (devoptab_list[fd] == NULL) { + /* nothing mapped on that FD */ + r->_errno = EBADF; + return -1; + } + + if (devoptab_list[fd]->close_r == NULL) { + /* Function not implemented */ + r->_errno = ENOSYS; + return -1; + } + + /* Call method from device operations table */ + ret = devoptab_list[fd]->close_r(r, fd); + + if (ret == 0) { + /* Successfully closed, clear out device operations table entry to free up + * the file descriptor. */ + devoptab_list[fd] = NULL; + } + + return ret; +} + +ssize_t +_read_r(struct _reent *r, int fd, void *ptr, size_t len) +{ + + if (fd < 0) { + /* invalid file descriptor */ + r->_errno = EBADF; + return -1; + } + + if (fd >= MAX_OPEN_DEVICES) { +#if CFS_ENABLED + int ret; + /* CFS file */ + fd -= MAX_OPEN_DEVICES; /* Remap to CFS FD number */ + /* this is not really reentrant */ + ret = cfs_read(fd, ptr, len); + + if (ret < 0) { + r->_errno = EBADF; + } + + return ret; +#else + r->_errno = EBADF; + return -1; +#endif + } + + if (devoptab_list[fd] == NULL) { + /* nothing mapped on that FD */ + r->_errno = EBADF; + return -1; + } + + if (devoptab_list[fd]->read_r == NULL) { + /* Function not implemented */ + r->_errno = ENOSYS; + return -1; + } + + /* Call method from device operations table */ + return devoptab_list[fd]->read_r(r, fd, ptr, len); +} + +ssize_t +_write_r(struct _reent *r, int fd, const void *ptr, size_t len) +{ + + if (fd < 0) { + /* invalid file descriptor */ + r->_errno = EBADF; + return -1; + } + + if (fd >= MAX_OPEN_DEVICES) { +#if CFS_ENABLED + int ret; + /* CFS file */ + fd -= MAX_OPEN_DEVICES; /* Remap to CFS FD number */ + /* this is not really reentrant */ + ret = cfs_write(fd, (const char *)ptr, len); + + if (ret < 0) { + r->_errno = EBADF; + } + + return ret; +#else + r->_errno = EBADF; + return -1; +#endif + } + + if (devoptab_list[fd] == NULL) { + /* nothing mapped on that FD */ + r->_errno = EBADF; + return -1; + } + + if (devoptab_list[fd]->write_r == NULL) { + /* Function not implemented */ + r->_errno = ENOSYS; + return -1; + } + + /* Call method from device operations table */ + return devoptab_list[fd]->write_r(r, fd, ptr, len); +} + +off_t +_lseek_r(struct _reent *r, int fd, off_t offset, int whence) +{ + + if (fd < 0) { + /* invalid file descriptor */ + r->_errno = EBADF; + return -1; + } + + if (fd >= MAX_OPEN_DEVICES) { +#if CFS_ENABLED + int ret; + /* CFS file */ + fd -= MAX_OPEN_DEVICES; /* Remap to CFS FD number */ + /* CFS_SEEK_* macros used by the CFS whence parameter is assumed to + * correspond with POSIX constants */ + /* this is not really reentrant */ + ret = cfs_seek(fd, offset, whence); + + if (ret < 0) { + r->_errno = EBADF; + } + + return ret; +#else + r->_errno = EBADF; + return -1; +#endif + } + + if (devoptab_list[fd] == NULL) { + /* nothing mapped on that FD */ + r->_errno = EBADF; + return -1; + } + + if (devoptab_list[fd]->lseek_r == NULL) { + /* Function not implemented */ + r->_errno = ENOSYS; + return -1; + } + + /* Call method from device operations table */ + return devoptab_list[fd]->lseek_r(r, fd, offset, whence); +} + +int +_fstat_r(struct _reent *r, int fd, struct stat *st) +{ + + if (fd < 0) { + /* invalid file descriptor */ + r->_errno = EBADF; + return -1; + } + + if (fd >= MAX_OPEN_DEVICES) { + /* CFS file */ + st->st_mode = S_IFREG | S_IRWXU | S_IRWXG | S_IRWXO; /* regular file, 0777 perms (-rwxrwxrwx) */ + /** \todo Handle file size with fstat */ + /* st->st_uid = 0; */ + /* st->st_gid = 0; */ + /* st->st_size = 0; */ + return 0; + } + + if (devoptab_list[fd] != NULL) { + /* Check device operations table to determine mode */ + st->st_mode = devoptab_list[fd]->st_mode; + return 0; + } + else { + /* nothing mapped on that FD */ + r->_errno = EBADF; + return -1; + } +} + +int +_isatty_r(struct _reent *r, int fd) +{ + + if (fd < 0) { + /* invalid file descriptor */ + r->_errno = EBADF; + return -1; + } + + if (fd >= MAX_OPEN_DEVICES) { + /* CFS file, not a TTY */ + r->_errno = ENOTTY; + return 0; + } + + if (devoptab_list[fd] != NULL) { + /* Check device operations table to determine if it is considered a TTY */ + if (devoptab_list[fd]->isatty == 0) { + r->_errno = ENOTTY; + } + + return devoptab_list[fd]->isatty; + } + else { + /* nothing mapped on that FD */ + r->_errno = EBADF; + return -1; + } +} + +/* Compatibility define for newlib built without REENTRANT_SYSCALLS_PROVIDED */ +int +_isatty(int fd) +{ + /* _REENT is an internal newlib macro, this may cause issues in some situations. */ + return _isatty_r(_REENT, fd); +} + +/* **************************** */ +/* File system related syscalls */ +/* **************************** */ + +int +_stat_r(struct _reent *r, const char *file, struct stat *st) +{ + /* not supported, yet */ + (void)file; /* Suppress compiler warnings about unused parameters */ + (void)st; + r->_errno = ENOENT; + return -1; +} + +int +_link_r(struct _reent *r, const char *old, const char *new) +{ + /* not supported, yet */ + (void)old; /* Suppress compiler warnings about unused parameters */ + (void)new; + r->_errno = EMLINK; + return -1; +} + +int +_unlink_r(struct _reent *r, const char *name) +{ + /* not supported, yet */ + (void)name; /* Suppress compiler warnings about unused parameters */ + r->_errno = ENOENT; + return -1; +} + +/* ********************************** */ +/* Memory management related syscalls */ +/* ********************************** */ + +/* Beginning of unallocated RAM, defined by the linker script */ +extern int _heap_start; +/* End of RAM area available for allocation */ +extern int _heap_end; +/* Current edge of dynamically allocated space */ +static void *current_break = (void *)(&_heap_start); + +/** + * Move the program break. + * + * This function can increase the size of the allocated memory. + * + * NEVER call this from ISRs (or anything that may call this function, e.g. malloc, free). + */ +void *_sbrk_r(struct _reent *r, ptrdiff_t increment) +{ + void *ret; + /* Make sure we have exclusive access to the system break variable. */ + mutex_lock(&sbrk_mutex); + + /* Align memory increment to nearest DYNAMIC_MEMORY_ALIGN bytes upward */ + if (increment % DYNAMIC_MEMORY_ALIGN) { + increment += DYNAMIC_MEMORY_ALIGN - (increment % DYNAMIC_MEMORY_ALIGN); + } + + if (((uint8_t *)current_break + increment) < ((uint8_t *)(&_heap_end))) { + ret = current_break; + current_break = (void *)(((uint8_t *)current_break) + increment); + } + else { + r->_errno = ENOMEM; + ret = (void *) - 1; + } + + mutex_unlock(&sbrk_mutex); + return ret; +} +/** @} */ diff --git a/dist/tools/licenses/patterns/cmsis-pal-freescale-mk60dz10 b/dist/tools/licenses/patterns/cmsis-pal-freescale-mk60dz10 new file mode 100644 index 0000000000..eedf524825 --- /dev/null +++ b/dist/tools/licenses/patterns/cmsis-pal-freescale-mk60dz10 @@ -0,0 +1 @@ +Version: rev\. 1\.2, 2011-09-08 Abstract: CMSIS Peripheral Access Layer for MK60DZ10 Copyright: 1997 - 2011 Freescale Semiconductor, Inc\. All Rights Reserved\. diff --git a/doc/doxygen/riot.doxyfile b/doc/doxygen/riot.doxyfile index c825054888..9506cb71a3 100644 --- a/doc/doxygen/riot.doxyfile +++ b/doc/doxygen/riot.doxyfile @@ -826,6 +826,8 @@ EXCLUDE_PATTERNS = */board/*/tools/* \ */cpu/x86/include/x86_pci.h \ */cpu/sam3x8e/include/sam3x8e.h \ */cpu/stm32l1/include/stm32l1xx.h \ + */cpu/k60/include/MK60D10.h \ + */cpu/k60/include/MK60DZ10.h \ # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names