kinetis: Handle ADC modules without extra ADICLK divider

Newer CPUs have alternate clock sources on ADICLK=1 instead of Bus/2

cpu/k60/include/cpu_conf.h

@@ -43,6 +43,11 @@ extern "C"
 #error Unknown CPU model. Update Makefile.include in the board directory.
 #endif
 
+/**
+ * @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
+ */
+#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
+
 /**
  * @brief   ARM Cortex-M specific CPU configuration
  * @{

cpu/kinetis_common/periph/adc.c

@@ -171,7 +171,16 @@ int adc_init(adc_t line)
     /* For the calibration it is important that the ADC clock is <= 4 MHz */
     uint32_t adiv;
     if (CLOCK_BUSCLOCK > (ADC_MAX_CLK << 3)) {
+#if KINETIS_HAVE_ADICLK_BUS_DIV_2
+        /* Some CPUs, e.g. MK60D10, MKW22D5, provide an additional divide by two
+         * divider for the bus clock as CFG1[ADICLK] = 0b01
+         */
         adiv = ADC_CFG1_ADIV(3) | ADC_CFG1_ADICLK(1);
+#else
+        /* Newer CPUs seem to have replaced this with various alternate clock
+         * sources instead */
+        adiv = ADC_CFG1_ADIV(3);
+#endif
     }
     else {
         unsigned int i = 0;

cpu/kw2xd/include/cpu_conf.h

@@ -51,6 +51,11 @@ extern "C"
 #define CPU_FLASH_BASE                  (0x00000000)
 /** @} */
 
+/**
+ * @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
+ */
+#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
+
 /**
  * @name GPIO pin mux function numbers
  */