From e3bb708e4d52c0445da7d293af429a39ae27fc68 Mon Sep 17 00:00:00 2001
From: Gunar Schorcht <gunar@schorcht.net>
Date: Thu, 28 Nov 2019 08:57:12 +0100
Subject: [PATCH] cpu/esp32/periph: flush UART TX FIFO before a baudrate change

---
 cpu/esp32/periph/uart.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/cpu/esp32/periph/uart.c b/cpu/esp32/periph/uart.c
index 77905de63f..5e3d7c200b 100644
--- a/cpu/esp32/periph/uart.c
+++ b/cpu/esp32/periph/uart.c
@@ -281,6 +281,8 @@ static void _uart_config (uart_t uart)
 
     /* setup the baudrate */
     if (uart == UART_DEV(0) || uart == UART_DEV(1)) {
+        /* wait until TX FIFO is empty */
+        while (_uarts[uart].regs->status.txfifo_cnt) { }
         /* for UART0 and UART1, we can us the ROM function */
         uart_div_modify(uart, (UART_CLK_FREQ << 4) / _uarts[uart].baudrate);
     }