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cpu/saml21: Use {} notation for empty while loops

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This commit is contained in:
Joakim Nohlgård 2016-01-26 20:01:06 +01:00
parent 2ea2cdc9e1
commit e607de5b95
7 changed files with 28 additions and 29 deletions
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6
cpu/saml21/cpu.c
View File

@ -24,7 +24,7 @@
static void _gclk_setup(int gclk, uint32_t reg)
{
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk));
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk)) {}
GCLK->GENCTRL[gclk].reg = reg;
}
@ -57,8 +57,8 @@ void cpu_init(void)
/* Software reset the GCLK module to ensure it is re-initialized correctly */
GCLK->CTRLA.reg = GCLK_CTRLA_SWRST;
while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST);
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST);
while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {}
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
/* set OSC16M to 16MHz */
OSCCTRL->OSC16MCTRL.bit.FSEL = 3;

2
cpu/saml21/lpm_arch.c
View File

@ -62,7 +62,7 @@ enum lpm_mode lpm_arch_set(enum lpm_mode target)
PM->SLEEPCFG.bit.SLEEPMODE = mode;
/* make sure value has been set */
while (PM->SLEEPCFG.bit.SLEEPMODE != mode);
while (PM->SLEEPCFG.bit.SLEEPMODE != mode) {}
/* ensure all memory accesses have completed */
__DSB();

2
cpu/saml21/periph/gpio.c
View File

@ -153,7 +153,7 @@ int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank,
EIC->INTENSET.reg = (1 << exti);
/* enable the EIC module*/
EIC->CTRLA.reg = EIC_CTRLA_ENABLE;
while (EIC->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE);
while (EIC->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) {}
return 0;
}

8
cpu/saml21/periph/rtt.c
View File

@ -40,7 +40,7 @@ void rtt_init(void)
/* reset */
RTC->MODE0.CTRLA.bit.SWRST = 1;
while(RTC->MODE0.CTRLA.bit.SWRST);
while(RTC->MODE0.CTRLA.bit.SWRST) {}
/* set 32bit counting mode */
RTC->MODE0.CTRLA.bit.MODE = 0;
@ -50,7 +50,7 @@ void rtt_init(void)
/* enable */
RTC->MODE0.CTRLA.bit.ENABLE = 1;
while(RTC->MODE0.SYNCBUSY.bit.ENABLE);
while(RTC->MODE0.SYNCBUSY.bit.ENABLE) {}
/* initially clear flag */
RTC->MODE0.INTFLAG.bit.CMP0 = 1;
@ -84,7 +84,7 @@ void rtt_clear_overflow_cb(void)
uint32_t rtt_get_counter(void)
{
DEBUG("%s:%d\n", __func__, __LINE__);
while (RTC->MODE0.SYNCBUSY.bit.COUNT);
while (RTC->MODE0.SYNCBUSY.bit.COUNT) {}
return RTC->MODE0.COUNT.reg;
}
@ -96,7 +96,7 @@ void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
rtt_clear_alarm();
/* set COM register */
while (RTC->MODE0.SYNCBUSY.bit.COMP0);
while (RTC->MODE0.SYNCBUSY.bit.COMP0) {}
RTC->MODE0.COMP[0].reg = alarm;
/* setup callback */

16
cpu/saml21/periph/spi.c
View File

@ -131,7 +131,7 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
GCLK_PCHCTRL_CHEN |
GCLK_PCHCTRL_GEN_GCLK0;
while (!(GCLK->PCHCTRL[spi[dev].gclk_id].reg & GCLK_PCHCTRL_CHEN));
while (!(GCLK->PCHCTRL[spi[dev].gclk_id].reg & GCLK_PCHCTRL_CHEN)) {}
/* SCLK+MOSI = output */
gpio_init(spi[dev].sclk.pin, GPIO_DIR_OUT, GPIO_NOPULL);
@ -152,7 +152,7 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
/* Disable spi to write config */
spi_dev->CTRLA.bit.ENABLE = 0;
while (spi_dev->SYNCBUSY.reg);
while (spi_dev->SYNCBUSY.reg) {}
/* setup baud */
spi_dev->BAUD.bit.BAUD = (uint8_t) (((uint32_t) GCLK_REF) / (2 * f_baud) - 1); /* Syncronous mode*/
@ -163,9 +163,9 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
| (cpha << SERCOM_SPI_CTRLA_CPHA_Pos)
| (cpol << SERCOM_SPI_CTRLA_CPOL_Pos);
while (spi_dev->SYNCBUSY.reg);
while (spi_dev->SYNCBUSY.reg) {}
spi_dev->CTRLB.reg = (SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN);
while(spi_dev->SYNCBUSY.reg);
while(spi_dev->SYNCBUSY.reg) {}
spi_poweron(dev);
return 0;
}
@ -203,12 +203,12 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
{
SercomSpi* spi_dev = spi[dev].dev;
while (!spi_dev->INTFLAG.bit.DRE); /* while data register is not empty*/
while (!spi_dev->INTFLAG.bit.DRE) {} /* while data register is not empty */
spi_dev->DATA.bit.DATA = out;
if (in)
{
while (!spi_dev->INTFLAG.bit.RXC); /* while receive is not complete*/
while (!spi_dev->INTFLAG.bit.RXC) {} /* while receive is not complete */
*in = spi_dev->DATA.bit.DATA;
}
else
@ -223,14 +223,14 @@ void spi_poweron(spi_t dev)
{
SercomSpi* spi_dev = spi[dev].dev;
spi_dev->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
while(spi_dev->SYNCBUSY.bit.ENABLE);
while(spi_dev->SYNCBUSY.bit.ENABLE) {}
}
void spi_poweroff(spi_t dev)
{
SercomSpi* spi_dev = spi[dev].dev;
spi_dev->CTRLA.bit.ENABLE = 0;
while(spi_dev->SYNCBUSY.bit.ENABLE);
while(spi_dev->SYNCBUSY.bit.ENABLE) {}
}
#endif /* SPI_0_EN || SPI_1_EN */

7
cpu/saml21/periph/timer.c
View File

@ -48,7 +48,7 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
{
/* configure GCLK0 to feed TC0 & TC1*/;
GCLK->PCHCTRL[TC0_GCLK_ID].reg |= GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK0;
while (!(GCLK->PCHCTRL[TC0_GCLK_ID].reg & GCLK_PCHCTRL_CHEN));
while (!(GCLK->PCHCTRL[TC0_GCLK_ID].reg & GCLK_PCHCTRL_CHEN)) {}
/* select the timer and enable the timer specific peripheral clocks */
switch (dev) {
@ -60,7 +60,7 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
MCLK->APBCMASK.reg |= MCLK_APBCMASK_TC0;
/* reset timer */
TIMER_0_DEV.CTRLA.bit.SWRST = 1;
while (TIMER_0_DEV.SYNCBUSY.bit.SWRST);
while (TIMER_0_DEV.SYNCBUSY.bit.SWRST) {}
/* choosing 32 bit mode */
TIMER_0_DEV.CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT32_Val;
/* sourced by 4MHz with Presc 4 results in 1MHz*/
@ -159,9 +159,8 @@ unsigned int timer_read(tim_t dev)
case TIMER_0:
/* request syncronisation */
TIMER_0_DEV.CTRLBSET.bit.CMD = TC_CTRLBSET_CMD_READSYNC_Val;
while (TIMER_0_DEV.SYNCBUSY.bit.STATUS);
while (TIMER_0_DEV.SYNCBUSY.bit.STATUS) {}
return TIMER_0_DEV.COUNT.reg;
break;
#endif
default:
return 0;

16
cpu/saml21/periph/uart.c
View File

@ -88,8 +88,8 @@ static int init_base(uart_t uart, uint32_t baudrate)
| PORT_WRCONFIG_PMUXEN \
| UART_0_PINS;
UART_0_DEV.CTRLA.bit.ENABLE = 0; //Disable to write, need to sync tho
while(UART_0_DEV.SYNCBUSY.bit.ENABLE);
UART_0_DEV.CTRLA.bit.ENABLE = 0; /* Disable to write, need to sync tho */
while(UART_0_DEV.SYNCBUSY.bit.ENABLE) {}
/* set to LSB, asynchronous mode without parity, PAD0 Tx, PAD1 Rx,
* 16x over-sampling, internal clk */
@ -107,7 +107,7 @@ static int init_base(uart_t uart, uint32_t baudrate)
/* enable receiver and transmitter, one stop bit*/
UART_0_DEV.CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
while(UART_0_DEV.SYNCBUSY.bit.CTRLB);
while(UART_0_DEV.SYNCBUSY.bit.CTRLB) {}
break;
#endif
@ -124,10 +124,10 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
if (uart == UART_0) {
for (size_t i = 0; i < len; i++) {
while (UART_0_DEV.INTFLAG.bit.DRE == 0);
while(UART_0_DEV.SYNCBUSY.bit.ENABLE);
while (UART_0_DEV.INTFLAG.bit.DRE == 0) {}
while(UART_0_DEV.SYNCBUSY.bit.ENABLE) {}
UART_0_DEV.DATA.reg = data[i];
while (UART_0_DEV.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC);
while (UART_0_DEV.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {}
}
}
}
@ -151,13 +151,13 @@ static inline void irq_handler(uint8_t uartnum, SercomUsart *dev)
void uart_poweron(uart_t uart)
{
while (UART_0_DEV.SYNCBUSY.reg);
while (UART_0_DEV.SYNCBUSY.reg) {}
UART_0_DEV.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
}
void uart_poweroff(uart_t uart)
{
while (UART_0_DEV.SYNCBUSY.reg);
while (UART_0_DEV.SYNCBUSY.reg) {}
UART_0_DEV.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
}