boards/common/gd32v: add default SPI configuration

boards/common/gd32v/include/cfg_spi_default.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
+ *               2023 Gunar Schorcht <gunar@schorcht.net>
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_common_gd32v
+ * @{
+ *
+ * @file
+ * @brief       Common peripheral configuration for GD32VF103 boards
+ *
+ * @author      Koen Zandberg <koen@bergzand.net>
+ * @author      Gunar Schorcht <gunar@schorcht.net>
+ */
+
+#ifndef CFG_SPI_DEFAULT_H
+#define CFG_SPI_DEFAULT_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name   SPI configuration
+ * @{
+ */
+static const spi_conf_t spi_config[] = {
+    {
+        .dev      = SPI1,
+        .mosi_pin = GPIO_PIN(PORT_B, 15),
+        .miso_pin = GPIO_PIN(PORT_B, 14),
+        .sclk_pin = GPIO_PIN(PORT_B, 13),
+        .cs_pin   = GPIO_PIN(PORT_B, 12),
+        .rcumask  = RCU_APB1EN_SPI1EN_Msk,
+        .apbbus   = APB1,
+    },
+#ifndef MODULE_PERIPH_ADC
+    {
+        .dev      = SPI0,
+        .mosi_pin = GPIO_PIN(PORT_A, 7),
+        .miso_pin = GPIO_PIN(PORT_A, 6),
+        .sclk_pin = GPIO_PIN(PORT_A, 5),
+        .cs_pin   = GPIO_PIN(PORT_A, 4),
+        .rcumask  = RCU_APB2EN_SPI0EN_Msk,
+        .apbbus   = APB2,
+    },
+#endif
+};
+
+#define SPI_NUMOF           ARRAY_SIZE(spi_config)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CFG_SPI_DEFAULT_H */
+/** @} */