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remove legacy board specific cc2420 code

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Kaspar Schleiser 2015-08-05 10:54:37 +02:00
parent 723d0b2479
commit ebc9b2ab5f
3 changed files with 0 additions and 764 deletions
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245
boards/telosb/driver_cc2420.c
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@ -1,245 +0,0 @@
/*
* driver_cc2420.c - Implementation of the board dependent cc2420 functions.
* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "irq.h"
#include "hwtimer.h"
#include "panic.h"
#include "cc2420.h"
#include "cc2420_arch.h"
#include "cc2420_spi.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#define CC2420_RESETn_PIN 0x40
#define CC2420_VREGEN_PIN 0x20
#define CC2420_FIFOP_PIN 0x01
#define CC2420_GIO0_PIN 0x08
#define CC2420_GIO1_PIN 0x10
#define CC2420_CCA_PIN 0x40
#define CC2420_SFD_PIN 0x02
#define CC2420_FIFOP (P1IN & CC2420_FIFOP_PIN) /* FIFOP <-> packet interrupt (P1.0) */
#define CC2420_GIO0 (P1IN & CC2420_GIO0_PIN) /* FIFO <-> GIO0 - RX data available (P1.3) */
#define CC2420_GIO1 (P1IN & CC2420_GIO1_PIN) /* CCA <-> GIO1 - clear channel (P1.4) */
#define CC2420_SFD (P4IN & CC2420_SFD_PIN) /* SFD <-> TBL - start frame delimiter (P4.1) */
#define CC2420_CS_LOW (P4OUT &= ~0x04) /* P4.2 */
#define CC2420_CS_HIGH (P4OUT |= 0x04)
volatile int abort_count;
volatile int retry_count = 0;
void cc2420_reset(void)
{
P4OUT |= CC2420_VREGEN_PIN;
P4OUT &= ~CC2420_RESETn_PIN;
hwtimer_wait(500);
P4OUT |= CC2420_RESETn_PIN;
}
void cc2420_gio0_enable(void)
{
P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
P1IE |= CC2420_GIO0_PIN; /* Enable interrupt for GIO0 */
}
void cc2420_gio0_disable(void)
{
P1IE &= ~CC2420_GIO0_PIN; /* Disable interrupt for GIO0 */
P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
}
void cc2420_gio1_enable(void)
{
P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
P1IE |= CC2420_GIO1_PIN; /* Enable interrupt for GIO1 */
}
void cc2420_gio1_disable(void)
{
P1IE &= ~CC2420_GIO1_PIN; /* Disable interrupt for GIO1 */
P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
}
void cc2420_before_send(void)
{
/* Disable SFD interrupt before sending packet */
/* However this is not used atm */
}
void cc2420_after_send(void)
{
/* Enable SFD interrupt after sending packet */
/* However this is not used atm */
}
int cc2420_get_gio0(void)
{
return CC2420_GIO0;
}
int cc2420_get_gio1(void)
{
return CC2420_GIO1;
}
uint8_t cc2420_get_fifop(void)
{
return CC2420_FIFOP;
}
uint8_t cc2420_get_sfd(void)
{
return CC2420_SFD;
}
#define MAX_RSSI_WAIT 1000
uint8_t cc2420_get_cca(void)
{
uint8_t status;
long count = 0;
do {
unsigned int sr = disableIRQ();
cc2420_spi_select();
status = cc2420_txrx(NOBYTE);
cc2420_spi_unselect();
restoreIRQ(sr);
count++;
if (count >= MAX_RSSI_WAIT) {
core_panic(0x2420, "cc2420_get_cca(): RSSI never valid!");
}
} while (!(status & CC2420_STATUS_RSSI_VALID));
return CC2420_GIO1;
}
void cc2420_spi_cs(void)
{
CC2420_CS_LOW;
}
uint8_t cc2420_txrx(uint8_t data)
{
/* Ensure TX Buf is empty */
long c = 0;
IFG1 &= ~UTXIFG0;
IFG1 &= ~URXIFG0;
U0TXBUF = data;
while(!(IFG1 & UTXIFG0)) {
if (c++ == 1000000) {
core_panic(0x2420, "cc2420_txrx() alarm");
}
}
/* Wait for Byte received */
c = 0;
while(!(IFG1 & URXIFG0)) {
if (c++ == 1000000) {
core_panic(0x2420, "cc2420_txrx() alarm");
}
}
return U0RXBUF;
}
void cc2420_spi_select(void)
{
CC2420_CS_LOW;
}
void cc2420_spi_unselect(void) {
CC2420_CS_HIGH;
}
void cc2420_init_interrupts(void)
{
unsigned int state = disableIRQ(); /* Disable all interrupts */
P1SEL &= ~CC2420_FIFOP_PIN; /* must be <> 1 to use interrupts */
P1SEL &= ~CC2420_GIO0_PIN; /* must be <> 1 to use interrupts */
/* FIFO <-> GIO0 interrupt */
P1IES |= CC2420_GIO0_PIN; /* Enables external interrupt on falling edge (for GIO0/FIFO) */
P1IE |= CC2420_GIO0_PIN; /* Enable interrupt */
P1IFG &= ~CC2420_GIO0_PIN; /* Clears the interrupt flag */
/* FIFOP <-> Packet interrupt */
P1IE |= CC2420_FIFOP_PIN; /* Enable interrupt for FIFOP */
P1IFG &= ~CC2420_FIFOP_PIN; /* Clear IFG for FIFOP */
restoreIRQ(state); /* Enable all interrupts */
}
void cc2420_spi_init(void)
{
/* Switch off async UART */
while(!(U0TCTL & TXEPT)); /* Wait for empty UxTXBUF register */
IE1 &= ~(URXIE0 + UTXIE0); /* Disable USART0 receive&transmit interrupt */
ME1 &= ~(UTXE0 + URXE0);
/* configure SPI-related pins */
P3SEL |= 0x0E; /* P3.1 - SIMO mode, P3.2 - SOMI mode, P3.3 - SCL mode */
P3DIR |= 0x0A; /* P3.1 and P3.3 as output */
P3DIR &= ~(0x04); /* P3.2 as input for SOMI */
P4OUT |= 0x04; /* P4.2 radio CS, hold high */
P4DIR |= 0x04; /* P4.2 radio CS, output */
/* Keep peripheral in reset state */
U0CTL = SWRST;
/* 8-bit SPI Master 3-pin mode, with SMCLK as clock source */
/* CKPL works also, but not CKPH+CKPL or none of them!! */
U0CTL |= CHAR + SYNC + MM;
U0TCTL = CKPH + SSEL1 + SSEL0 + STC + TXEPT;;
/* Ignore clockrate argument for now, just use clock source/2 */
/* SMCLK = 8 MHz */
U0BR0 = 0x02; /* Ensure baud rate >= 2 */
U0BR1 = 0x00;
U0MCTL = 0x00; /* No modulation */
U0RCTL = 0x00; /* Reset Receive Control Register */
/* Enable SPI mode */
ME1 |= USPIE0;
/* Release for operation */
U0CTL &= ~SWRST;
}
/*
* CC2420 receive interrupt
*/
interrupt (PORT1_VECTOR) __attribute__ ((naked)) cc2420_isr(void)
{
__enter_isr();
/* Check IFG */
if ((P1IFG & CC2420_FIFOP_PIN) != 0) {
P1IFG &= ~CC2420_FIFOP_PIN;
cc2420_rx_irq();
DEBUG("rx interrupt");
}
/* GIO0 is falling => check if FIFOP is high, indicating an RXFIFO overflow */
else if ((P1IFG & CC2420_GIO0_PIN) != 0) {
P1IFG &= ~CC2420_GIO0_PIN;
if (cc2420_get_fifop()) {
cc2420_rxoverflow_irq();
DEBUG("[CC2420] rxfifo overflow");
}
}
else {
puts("cc2420_isr(): unexpected IFG!");
/* Should not occur - only GDO1 and GIO1 interrupts are enabled */
}
__exit_isr();
}

247
boards/wsn430-v1_4/driver_cc2420.c
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@ -1,247 +0,0 @@
/*
* driver_cc2420.c - Implementation of the board dependent cc2420 functions.
* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will
* Copyright (C) 2013 Milan Babel <babel@inf.fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "irq.h"
#include "hwtimer.h"
#include "panic.h"
#include "cc2420.h"
#include "cc2420_arch.h"
#include "cc2420_spi.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#define CC2420_RESETn_PIN 0x80
#define CC2420_VREGEN_PIN 0x01
#define CC2420_GDO0_PIN 0x08
#define CC2420_GDO2_PIN 0x10
#define CC2420_SFD_PIN 0x20
#define CC2420_CCA_PIN 0x40
#define CC2420_GDO0 (P1IN & CC2420_GDO0_PIN) // read serial I/O (GDO0)
#define CC2420_GDO2 (P1IN & CC2420_GDO2_PIN) // read serial I/O (GDO2)
#define CC2420_SFD (P1IN & CC2420_SFD_PIN) // read serial I/0 (SFD)
#define CC2420_CCA (P1IN & CC2420_CCA_PIN) // read serial I/O (CCA)
#define CC2420_CS_LOW (P4OUT &= ~0x04)
#define CC2420_CS_HIGH (P4OUT |= 0x04)
#define CC2420_GDO1_LOW_COUNT (2700) // loop count (timeout ~ 500 us) to wait
#define CC2420_GDO1_LOW_RETRY (100) // max. retries for GDO1 to go low
volatile int abort_count;
volatile int retry_count = 0;
void cc2420_reset(void)
{
P3OUT |= CC2420_VREGEN_PIN;
P1OUT &= ~CC2420_RESETn_PIN;
hwtimer_wait(500);
P1OUT |= CC2420_RESETn_PIN;
}
void cc2420_gdo0_enable(void)
{
P1IFG &= ~CC2420_GDO0_PIN; /* Clear IFG for GDO0 */
P1IE |= CC2420_GDO0_PIN; /* Enable interrupt for GDO0 */
}
void cc2420_gdo0_disable(void)
{
P1IE &= ~CC2420_GDO0_PIN; /* Disable interrupt for GDO0 */
P1IFG &= ~CC2420_GDO0_PIN; /* Clear IFG for GDO0 */
}
void cc2420_gdo2_enable(void)
{
P1IFG &= ~CC2420_GDO2_PIN; /* Clear IFG for GDO2 */
P1IE |= CC2420_GDO2_PIN; /* Enable interrupt for GDO2 */
}
void cc2420_gdo2_disable(void)
{
P1IE &= ~CC2420_GDO2_PIN; /* Disable interrupt for GDO2 */
P1IFG &= ~CC2420_GDO2_PIN; /* Clear IFG for GDO2 */
}
void cc2420_before_send(void)
{
// Disable SFD interrupt before sending packet
// However this is not used atm
}
void cc2420_after_send(void)
{
// Enable SFD interrupt after sending packet
// However this is not used atm
}
int cc2420_get_gdo0(void)
{
return CC2420_GDO0;
}
int cc2420_get_gdo2(void)
{
return CC2420_GDO2;
}
uint8_t cc2420_get_sfd(void)
{
return CC2420_SFD;
}
uint8_t cc2420_get_fifop(void)
{
return CC2420_GDO2;
}
#define MAX_RSSI_WAIT 1000
uint8_t cc2420_get_cca(void)
{
uint8_t status;
long count = 0;
do {
unsigned int sr = disableIRQ();
cc2420_spi_select();
status = cc2420_txrx(NOBYTE);
cc2420_spi_unselect();
restoreIRQ(sr);
count++;
if (count >= MAX_RSSI_WAIT) {
core_panic(0x2420, "cc2420_get_cca(): RSSI never valid!");
}
} while (!(status & CC2420_STATUS_RSSI_VALID));
return CC2420_CCA;
}
void cc2420_spi_cs(void)
{
CC2420_CS_LOW;
}
uint8_t cc2420_txrx(uint8_t data)
{
/* Ensure TX Buf is empty */
long c = 0;
IFG2 &= ~UTXIFG1;
IFG2 &= ~URXIFG1;
U1TXBUF = data;
while(!(IFG2 & UTXIFG1)) {
if (c++ == 1000000) {
core_panic(0x2420, "cc2420_txrx() alarm");
}
}
/* Wait for Byte received */
c = 0;
while(!(IFG2 & URXIFG1)) {
if (c++ == 1000000) {
core_panic(0x2420, "cc2420_txrx() alarm");
}
}
return U1RXBUF;
}
void cc2420_spi_select(void)
{
CC2420_CS_LOW;
}
void cc2420_spi_unselect(void) {
CC2420_CS_HIGH;
}
void cc2420_init_interrupts(void)
{
unsigned int state = disableIRQ(); /* Disable all interrupts */
P1SEL = 0x00; /* must be <> 1 to use interrupts */
P1IES |= CC2420_GDO2_PIN; /* Enables external interrupt on falling edge (for GDO2) */
P1IE |= CC2420_GDO2_PIN; /* Enable interrupt */
P1IFG &= ~CC2420_GDO2_PIN; /* Clears the interrupt flag */
P1IES |= CC2420_SFD_PIN; /* Enables external interrupt on falling edge (for GDO2) */
P1IE |= CC2420_SFD_PIN; /* Enable interrupt */
P1IFG &= ~CC2420_SFD_PIN; /* Clears the interrupt flag */
P1IE &= ~CC2420_GDO0_PIN; /* Disable interrupt for GDO0 */
P1IFG &= ~CC2420_GDO0_PIN; /* Clear IFG for GDO0 */
restoreIRQ(state); /* Enable all interrupts */
}
void cc2420_spi_init(void)
{
// Switch off async UART
while(!(U1TCTL & TXEPT)); // Wait for empty UxTXBUF register
IE2 &= ~(URXIE1 + UTXIE1); // Disable USART1 receive&transmit interrupt
ME2 &= ~(UTXE1 + URXE1);
P5DIR |= 0x0A; // output for CLK and SIMO
P5DIR &= ~(0x04); // input for SOMI
P5SEL |= 0x0E; // Set pins as SPI
// Keep peripheral in reset state
U1CTL = SWRST;
// 8-bit SPI Master 3-pin mode, with SMCLK as clock source
// CKPL works also, but not CKPH+CKPL or none of them!!
U1CTL |= CHAR + SYNC + MM;
U1TCTL = CKPH + SSEL1 + SSEL0 + STC;
// Ignore clockrate argument for now, just use clock source/2
// SMCLK = 8 MHz
U1BR0 = 0x02; // Ensure baud rate >= 2
U1BR1 = 0x00;
U1MCTL = 0x00; // No modulation
U1RCTL = 0x00; // Reset Receive Control Register
// Enable SPI mode
ME2 |= USPIE1;
// Release for operation
U1CTL &= ~SWRST;
}
/*
* CC2420 receive interrupt
*/
interrupt (PORT1_VECTOR) __attribute__ ((naked)) cc2420_isr(void){
__enter_isr();
/* Check IFG */
if ((P1IFG & CC2420_GDO2_PIN) != 0) {
DEBUG("rx interrupt");
P1IFG &= ~CC2420_GDO2_PIN;
cc2420_rx_irq();
}
else if ((P1IFG & CC2420_GDO0_PIN) != 0) {
if (cc2420_get_gdo2()) {
cc2420_rxoverflow_irq();
DEBUG("[CC2420] rxfifo overflow");
}
P1IFG &= ~CC2420_GDO0_PIN; /* Clear IFG for GDO0 */
}
else if ((P1IFG & CC2420_SFD_PIN) != 0) {
DEBUG("sfd interrupt");
P1IFG &= ~CC2420_SFD_PIN;
cc2420_switch_to_rx();
}
else {
puts("cc2420_isr(): unexpected IFG!");
/* Should not occur - only GDO1 and GDO2 interrupts are enabled */
}
__exit_isr();
}

272
boards/z1/driver_cc2420.c
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/*
* driver_cc2420.c - Implementation of the board dependent cc2420 functions
* for Zolertia Z1.
* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
* Copyright (C) 2014 Kévin Roussel <Kevin.Roussel@inria.fr>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_z1
* @{
*
* @file
* @brief Board specific CC2420 driver HAL for the Zolertia Z1
*
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
*
* @}
*/
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "irq.h"
#include "hwtimer.h"
#include "panic.h"
#include "cc2420.h"
#include "cc2420_arch.h"
#include "cc2420_spi.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#define CC2420_RESETn_PIN 0x40 /* RADIO_RESET <-> P4.6 */
#define CC2420_VREGEN_PIN 0x20 /* RADIO_VREG_EN <-> P4.5 */
#define CC2420_FIFOP_PIN 0x04
#define CC2420_GIO0_PIN 0x08
#define CC2420_GIO1_PIN 0x10
#define CC2420_SFD_PIN 0x02
#define CC2420_FIFOP (P1IN & CC2420_FIFOP_PIN) /* FIFOP <-> packet interrupt (P1.2) */
#define CC2420_GIO0 (P1IN & CC2420_GIO0_PIN) /* FIFO <-> GIO0 - RX data available (P1.3) */
#define CC2420_GIO1 (P1IN & CC2420_GIO1_PIN) /* CCA <-> GIO1 - clear channel (P1.4) */
#define CC2420_SFD (P4IN & CC2420_SFD_PIN) /* SFD <-> TBL - start frame delimiter (P4.1) */
#define CC2420_CS_LOW (P3OUT &= ~0x01) /* RADIO_CS <-> P3.0 */
#define CC2420_CS_HIGH (P3OUT |= 0x01)
volatile int abort_count;
volatile int retry_count = 0;
void cc2420_reset(void)
{
P4OUT |= CC2420_VREGEN_PIN;
P4OUT &= ~CC2420_RESETn_PIN;
hwtimer_wait(500);
P4OUT |= CC2420_RESETn_PIN;
}
void cc2420_gio0_enable(void)
{
P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
P1IE |= CC2420_GIO0_PIN; /* Enable interrupt for GIO0 */
}
void cc2420_gio0_disable(void)
{
P1IE &= ~CC2420_GIO0_PIN; /* Disable interrupt for GIO0 */
P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
}
void cc2420_gio1_enable(void)
{
P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
P1IE |= CC2420_GIO1_PIN; /* Enable interrupt for GIO1 */
}
void cc2420_gio1_disable(void)
{
P1IE &= ~CC2420_GIO1_PIN; /* Disable interrupt for GIO1 */
P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
}
void cc2420_before_send(void)
{
/* Disable SFD interrupt before sending packet */
/* However there is no interrupt on MSP430F2617 port 4 */
}
void cc2420_after_send(void)
{
/* Enable SFD interrupt after sending packet */
/* However there is no interrupt on MSP430F2617 port 4 */
}
int cc2420_get_gio0(void)
{
return CC2420_GIO0;
}
int cc2420_get_gio1(void)
{
return CC2420_GIO1;
}
uint8_t cc2420_get_fifop(void)
{
return CC2420_FIFOP;
}
uint8_t cc2420_get_sfd(void)
{
return CC2420_SFD;
}
#define MAX_RSSI_WAIT 1000
uint8_t cc2420_get_cca(void)
{
uint8_t status;
long count = 0;
do {
unsigned int sr = disableIRQ();
cc2420_spi_select();
status = cc2420_txrx(NOBYTE);
cc2420_spi_unselect();
restoreIRQ(sr);
count++;
if (count >= MAX_RSSI_WAIT) {
core_panic(0x2420, "cc2420_get_cca(): RSSI never valid!");
}
} while (!(status & CC2420_STATUS_RSSI_VALID));
return CC2420_GIO1;
}
void cc2420_spi_cs(void)
{
CC2420_CS_LOW; /* Chip Select line is active-low */
}
#define MAX_SPI_WAIT 1000
uint8_t cc2420_txrx(uint8_t data)
{
/* Wait for SPI to be ready for transmission */
long count = 0;
do {
count++;
if (count >= MAX_SPI_WAIT) {
core_panic(0x2420, "cc2420_txrx(): SPI never ready for TX!");
}
} while (!(IFG2 & UCB0TXIFG));
/* Transmit data byte to CC2420, and wait for end of transmission */
IFG2 &= ~UCB0RXIFG;
UCB0TXBUF = data;
count = 0;
do {
count++;
if (count >= MAX_SPI_WAIT) {
core_panic(0x2420, "cc2420_txrx(): couldn't send byte!");
}
} while (UCB0STAT & UCBUSY);
/* Read the byte that CC2420 has (normally, during TX) returned */
count = 0;
do {
count++;
if (count >= MAX_SPI_WAIT) {
core_panic(0x2420, "cc2420_txrx(): couldn't receive byte!");
}
} while (!(IFG2 & UCB0RXIFG));
/* Return received byte */
return UCB0RXBUF;
}
void cc2420_spi_select(void)
{
CC2420_CS_LOW;
}
void cc2420_spi_unselect(void) {
CC2420_CS_HIGH;
}
void cc2420_init_interrupts(void)
{
unsigned int state = disableIRQ(); /* Disable all interrupts */
/* done in board.c : function z1_ports_init()
P1SEL &= ~CC2420_FIFOP_PIN; // must be <> 1 to use interrupts
P1SEL &= ~CC2420_GIO0_PIN; // must be <> 1 to use interrupts
*/
/* FIFO <-> GIO0 interrupt */
P1IES |= CC2420_GIO0_PIN; /* Enable external interrupt on falling edge for GIO0/FIFO */
P1IE |= CC2420_GIO0_PIN;
P1IFG &= ~CC2420_GIO0_PIN; /* Clear the interrupt flag */
/* FIFOP <-> Packet interrupt */
P1IES &= ~CC2420_FIFOP_PIN; /* Enable external interrupt on rising edge for FIFOP */
P1IE |= CC2420_FIFOP_PIN;
P1IFG &= ~CC2420_FIFOP_PIN; /* Clear IFG for FIFOP */
restoreIRQ(state); /* Enable all interrupts */
}
void cc2420_spi_init(void)
{
/*
* NOTES :
* - we will use SPI mode using block B of the USCI0,
* so as to avoid disturbing UART0 which is managed by USCI0 block A
* - MCU pin (GPIO port) initialisation is done in board.c,
* function z1_ports_init().
*/
/* Keep peripheral in reset state during configuration */
UCB0CTL1 = UCSWRST;
/* 8-bit SPI Master 3-pin mode, MSB first,
with SMCLK as clock source */
UCB0CTL0 = UCSYNC + UCMST + UCMODE_0 + UCMSB;
UCB0CTL1 |= UCSSEL_3;
UCB0CTL0 |= UCCKPH; /* Data captured on rising edge, changed on falling */
UCB0CTL0 &= ~UCCKPL; /* SPI data lines are active-high/inactive-low */
/* Ignore clockrate argument for now, just use clock source/2 */
UCB0BR0 = 0x02; /* Ensure baud rate <= SMCLK/2 */
UCB0BR1 = 0x00;
/* Release for operation */
UCB0CTL1 &= ~UCSWRST;
}
/*
* CC2420 receive interrupt
*/
interrupt (PORT1_VECTOR) __attribute__ ((naked)) cc2420_isr(void)
{
__enter_isr();
/* Check if FIFOP signal is raising => RX interrupt */
if ((P1IFG & CC2420_FIFOP_PIN) != 0) {
P1IFG &= ~CC2420_FIFOP_PIN;
cc2420_rx_irq();
DEBUG("rx interrupt");
}
/* GIO0 is falling => check if FIFOP is high, indicating an RXFIFO overflow */
else if ((P1IFG & CC2420_GIO0_PIN) != 0) {
P1IFG &= ~CC2420_GIO0_PIN;
if (cc2420_get_fifop()) {
cc2420_rxoverflow_irq();
DEBUG("[CC2420] rxfifo overflow");
}
}
else {
puts("cc2420_isr(): unexpected IFG!");
/* Should not occur - only FIFOP and GIO0 interrupts are enabled */
}
__exit_isr();
}