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cpu/stm32f7: add support for stm32f767zi
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@ -25,6 +25,8 @@
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#if defined(CPU_MODEL_STM32F746ZG)
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#include "vendor/stm32f746xx.h"
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#elif defined(CPU_MODEL_STM32F767ZI)
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#include "vendor/stm32f767xx.h"
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#elif defined(CPU_MODEL_STM32F769NI)
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#include "vendor/stm32f769xx.h"
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#endif
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@ -40,7 +42,7 @@ extern "C" {
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#if defined(CPU_MODEL_STM32F746ZG)
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#define CPU_IRQ_NUMOF (98U)
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#elif defined(CPU_MODEL_STM32F769NI)
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#elif defined(CPU_MODEL_STM32F769NI) || defined(CPU_MODEL_STM32F767ZI)
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#define CPU_IRQ_NUMOF (110U)
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#endif
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/** @} */
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10076
cpu/stm32f7/include/vendor/stm32f767xx.h
vendored
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10076
cpu/stm32f7/include/vendor/stm32f767xx.h
vendored
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File diff suppressed because it is too large
Load Diff
30
cpu/stm32f7/ldscripts/stm32f767zi.ld
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30
cpu/stm32f7/ldscripts/stm32f767zi.ld
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@ -0,0 +1,30 @@
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/*
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* Copyright (C) 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_stm32f7
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* @{
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*
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* @file
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* @brief Memory definitions for the STM32F767ZI
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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*/
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MEMORY
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{
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rom (rx) : ORIGIN = 0x08000000, LENGTH = 2M
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ram (rwx) : ORIGIN = 0x20000000, LENGTH = 512K
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cpuid (r) : ORIGIN = 0x1ff0f420, LENGTH = 12
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}
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_cpuid_address = ORIGIN(cpuid);
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INCLUDE cortexm_base.ld
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@ -126,7 +126,7 @@ WEAK_DEFAULT void isr_cec(void);
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WEAK_DEFAULT void isr_i2c4_ev(void);
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WEAK_DEFAULT void isr_i2c4_er(void);
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WEAK_DEFAULT void isr_spdif_rx(void);
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#if defined(CPU_MODEL_STM32F769NI)
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#if defined(CPU_MODEL_STM32F769NI) || defined(CPU_MODEL_STM32F767ZI)
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WEAK_DEFAULT void isr_dsi(void);
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WEAK_DEFAULT void isr_dfsdm1_flt0(void);
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WEAK_DEFAULT void isr_dfsdm1_flt1(void);
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@ -264,6 +264,10 @@ ISR_VECTORS const void *interrupt_vector[] = {
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(void*) isr_spdif_rx,
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#if defined(CPU_MODEL_STM32F769NI)
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(void*) isr_dsi,
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#elif defined(CPU_MODEL_STM32F767ZI)
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(void*) (0UL),
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#endif
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#if defined(CPU_MODEL_STM32F769NI) || defined(CPU_MODEL_STM32F767ZI)
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(void*) isr_dfsdm1_flt0,
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(void*) isr_dfsdm1_flt1,
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(void*) isr_dfsdm1_flt2,
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