diff --git a/boards/nucleo-f103/dist/openocd.cfg b/boards/nucleo-f103/dist/openocd.cfg
index 4017f6f358..82df176c41 100755
--- a/boards/nucleo-f103/dist/openocd.cfg
+++ b/boards/nucleo-f103/dist/openocd.cfg
@@ -1 +1,2 @@
+#source [find board/st_nucleo_f1.cfg]
 source [find board/st_nucleo_f103rb.cfg]
diff --git a/boards/nucleo-f103/include/board.h b/boards/nucleo-f103/include/board.h
index 7641bd1b37..977e053d9e 100755
--- a/boards/nucleo-f103/include/board.h
+++ b/boards/nucleo-f103/include/board.h
@@ -35,8 +35,9 @@ extern "C" {
 /**
  * @name xtimer configuration
  */
-#define XTIMER_MASK         (0xffff0000)
-#define XTIMER_BACKOFF      5
+#define XTIMER_MASK                 (0xffff0000)
+#define XTIMER_BACKOFF              5
+#define XTIMER_SHIFT_ON_COMPARE     (1)
 /** @} */
 
 #ifdef __cplusplus
diff --git a/boards/nucleo-f103/include/periph_conf.h b/boards/nucleo-f103/include/periph_conf.h
index 71334499c4..9eec1c83fc 100644
--- a/boards/nucleo-f103/include/periph_conf.h
+++ b/boards/nucleo-f103/include/periph_conf.h
@@ -29,12 +29,12 @@ extern "C" {
  * @name Clock system configuration
  * @{
  */
-#define CLOCK_HSI           (8000000U)              /* external oscillator */
-#define CLOCK_CORECLOCK     (64000000U)             /* desired core clock frequency */
+#define CLOCK_HSE           (8000000U)              /* external oscillator */
+#define CLOCK_CORECLOCK     (72000000U)             /* desired core clock frequency */
 
 /* the actual PLL values are automatically generated */
 #define CLOCK_PLL_DIV       (0)
-#define CLOCK_PLL_MUL       (16)
+#define CLOCK_PLL_MUL       (9)
 
 /* AHB, APB1, APB2 dividers */
 #define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
@@ -44,8 +44,6 @@ extern "C" {
 /* resulting bus clocks */
 #define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
 #define CLOCK_APB2          (CLOCK_CORECLOCK)
-#define CLOCK_APB1_TIMERS   ((CLOCK_APB1_DIV > 0) ? (CLOCK_APB1 << 1) : (CLOCK_APB1))
-#define CLOCK_APB2_TIMERS   ((CLOCK_APB2_DIV > 0) ? (CLOCK_APB2 << 1) : (CLOCK_APB2))
 
 /* Flash latency */
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2    /* for >= 72 MHz */
diff --git a/cpu/stm32f1/periph/timer.c b/cpu/stm32f1/periph/timer.c
index 2efb34f2e3..30933f883a 100644
--- a/cpu/stm32f1/periph/timer.c
+++ b/cpu/stm32f1/periph/timer.c
@@ -56,7 +56,7 @@ int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
     dev(tim)->CR2  = 0;
     dev(tim)->ARR  = TIMER_MAXVAL;
     /* set prescaler */
-    dev(tim)->PSC = ((((timer_config[tim].bus == APB1) ? CLOCK_APB1_TIMERS : CLOCK_APB2_TIMERS) / freq) - 1);
+    dev(tim)->PSC = (((CLOCK_CORECLOCK) / freq) - 1);
     /* generate an update event to apply our configuration */
     dev(tim)->EGR = TIM_EGR_UG;