diff --git a/cpu/arm7_common/common.s b/cpu/arm7_common/common.s
index ec828fbe81..a9c98d2daf 100644
--- a/cpu/arm7_common/common.s
+++ b/cpu/arm7_common/common.s
@@ -40,25 +40,6 @@
   .global  cpu_switch_context_exit
   .global  task_return
   .global  ctx_switch
-  .global  dINT
-  .global  eINT
-
-.func
-dINT:
-    mrs     r0,  cpsr
-
-    orr     r0, r0, #NOINT              /* Disable Int */
-    msr     CPSR_c, r0
-    mov     pc,lr
-.endfunc
-
-.func
-eINT:
-    mrs     r0,  cpsr
-    and     r0, r0, #~NOINT              /* Enable Int */
-    msr     CPSR_c, r0
-    mov     pc,lr
-.endfunc
 
 ctx_switch:
     /* Save return address on stack */
diff --git a/cpu/arm7_common/include/arm_cpu.h b/cpu/arm7_common/include/arm_cpu.h
index d883753fae..b196e69875 100644
--- a/cpu/arm7_common/include/arm_cpu.h
+++ b/cpu/arm7_common/include/arm_cpu.h
@@ -20,9 +20,6 @@
 #define NEW_TASK_CPSR 0x1F
 #define WORDSIZE 32
 
-extern void dINT(void);
-extern void eINT(void);
-
 uint32_t get_system_speed(void);
 void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t *prescale);
 
diff --git a/cpu/atmega_common/include/cpu.h b/cpu/atmega_common/include/cpu.h
index b7a83a9557..b7c7d83d2f 100644
--- a/cpu/atmega_common/include/cpu.h
+++ b/cpu/atmega_common/include/cpu.h
@@ -43,9 +43,6 @@
 extern "C" {
 #endif
 
-#define eINT            enableIRQ
-#define dINT            disableIRQ
-
 /**
  * @brief global in-ISR state variable
  */
diff --git a/cpu/cortexm_common/include/cpu.h b/cpu/cortexm_common/include/cpu.h
index 9cd14039d4..a7c2f1e59f 100644
--- a/cpu/cortexm_common/include/cpu.h
+++ b/cpu/cortexm_common/include/cpu.h
@@ -64,14 +64,6 @@ extern "C" {
 #endif
 /** @} */
 
-/**
- * @brief   Deprecated interrupt control function for backward compatibility
- * @{
- */
-#define eINT                            enableIRQ
-#define dINT                            disableIRQ
-/** @} */
-
 /**
  * @brief   Some members of the Cortex-M family have architecture specific
  *          atomic operations in atomic_arch.c
diff --git a/cpu/native/include/cpu.h b/cpu/native/include/cpu.h
index 2db6bdb844..a544ef5469 100644
--- a/cpu/native/include/cpu.h
+++ b/cpu/native/include/cpu.h
@@ -26,10 +26,6 @@
 extern "C" {
 #endif
 
-/* TODO: remove once these have been removed from RIOT: */
-void dINT(void);
-void eINT(void);
-
 /**
  * @brief   Prints the last instruction's address
  */
diff --git a/cpu/native/irq_cpu.c b/cpu/native/irq_cpu.c
index 7e77320707..bd02ce43e1 100644
--- a/cpu/native/irq_cpu.c
+++ b/cpu/native/irq_cpu.c
@@ -218,17 +218,6 @@ int inISR(void)
     return _native_in_isr;
 }
 
-
-void dINT(void)
-{
-    disableIRQ();
-}
-
-void eINT(void)
-{
-    enableIRQ();
-}
-
 int _native_popsig(void)
 {
     int nread, nleft, i;
diff --git a/cpu/native/syscalls.c b/cpu/native/syscalls.c
index 83ce8ba5f7..f138ade2ea 100644
--- a/cpu/native/syscalls.c
+++ b/cpu/native/syscalls.c
@@ -121,7 +121,7 @@ void _native_syscall_leave(void)
        )
     {
         _native_in_isr = 1;
-        disableIRQ();
+        unsigned int mask = disableIRQ();
         _native_cur_ctx = (ucontext_t *)sched_active_thread->sp;
         native_isr_context.uc_stack.ss_sp = __isr_stack;
         native_isr_context.uc_stack.ss_size = SIGSTKSZ;
@@ -130,7 +130,7 @@ void _native_syscall_leave(void)
         if (swapcontext(_native_cur_ctx, &native_isr_context) == -1) {
             err(EXIT_FAILURE, "_native_syscall_leave: swapcontext");
         }
-        enableIRQ();
+        restoreIRQ(mask);
     }
 }
 
diff --git a/sys/posix/pthread/pthread.c b/sys/posix/pthread/pthread.c
index d1014d4fe8..26b01ac923 100644
--- a/sys/posix/pthread/pthread.c
+++ b/sys/posix/pthread/pthread.c
@@ -206,7 +206,7 @@ void pthread_exit(void *retval)
             }
         }
 
-        dINT();
+        disableIRQ();
         if (self->stack) {
             msg_t m;
             m.content.ptr = self->stack;