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Merge pull request #15632 from aabadie/pr/boards/stm32f2f4f7_clock_kconfig_only

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cpu/stm32f2f4f7: expose clock configuration in kconfig
This commit is contained in:
Alexandre Abadie 2021-01-20 09:14:55 +01:00 committed by GitHub
commit f0606b0a73
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GPG Key ID: 4AEE18F83AFDEB23
45 changed files with 271 additions and 6 deletions
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6
boards/common/weact-f4x1cx/Kconfig
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@ -17,3 +17,9 @@ config BOARD_COMMON_WEACT_F41XCX
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
select HAS_HIGHLEVEL_STDIO
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

3
boards/common/weact-f4x1cx/Makefile.features
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@ -12,3 +12,6 @@ FEATURES_PROVIDED += periph_usbdev
# Various other features (if any)
FEATURES_PROVIDED += highlevel_stdio
# weact-f4x1cx boards provide a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/common/weact-f4x1cx/clock.config

4
boards/common/weact-f4x1cx/clock.config Normal file
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@ -0,0 +1,4 @@
# weact-f4x1cx based boards provide a 25MHz HSE so they need a custom PLL config
# to output a 48MHz clock for USB.
CONFIG_CUSTOM_PLL_PARAMS=y
CONFIG_CLOCK_PLL_M=25

6
boards/f4vi1/Kconfig
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@ -16,3 +16,9 @@ config BOARD_F4VI1
# Put defined MCU peripherals here (in alphabetical order)
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

3
boards/f4vi1/Makefile.features
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@ -5,3 +5,6 @@ CPU_MODEL = stm32f415rg
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# f4vi1 provides a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/f4vi1/clock.config

4
boards/f4vi1/clock.config Normal file
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@ -0,0 +1,4 @@
# f4vi1 provides a 16MHz HSE so they need a custom PLL config
# to remain in 180MHz max clock.
CONFIG_CUSTOM_PLL_PARAMS=y
CONFIG_CLOCK_PLL_N=90

6
boards/msbiot/Kconfig
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@ -22,3 +22,9 @@ config BOARD_MSBIOT
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

3
boards/msbiot/Makefile.features
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@ -10,3 +10,6 @@ FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# msbiot provides a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/msbiot/clock.config

5
boards/msbiot/clock.config Normal file
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@ -0,0 +1,5 @@
# msbiot provides a 16MHz HSE so its needs a custom PLL config to output a
# 180MHz clock.
CONFIG_CUSTOM_PLL_PARAMS=y
CONFIG_CLOCK_PLL_M=16
CONFIG_CLOCK_PLL_N=360

4
boards/nucleo-f207zg/Kconfig
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@ -28,4 +28,8 @@ config BOARD_NUCLEO_F207ZG
# Put other features for this board (in alphabetical order)
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

4
boards/nucleo-f401re/Kconfig
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@ -25,4 +25,8 @@ config BOARD_NUCLEO_F401RE
select HAS_PERIPH_UART
select HAS_PERIPH_QDEC
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

4
boards/nucleo-f410rb/Kconfig
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@ -23,4 +23,8 @@ config BOARD_NUCLEO_F410RB
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

4
boards/nucleo-f411re/Kconfig
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@ -24,4 +24,8 @@ config BOARD_NUCLEO_F411RE
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

4
boards/nucleo-f412zg/Kconfig
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@ -25,4 +25,8 @@ config BOARD_NUCLEO_F412ZG
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo144/Kconfig"

4
boards/nucleo-f413zh/Kconfig
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@ -28,4 +28,8 @@ config BOARD_NUCLEO_F413ZH
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo144/Kconfig"

4
boards/nucleo-f429zi/Kconfig
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@ -25,4 +25,8 @@ config BOARD_NUCLEO_F429ZI
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo144/Kconfig"

4
boards/nucleo-f446re/Kconfig
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@ -30,4 +30,8 @@ config BOARD_NUCLEO_F446RE
select HAS_MOTOR_DRIVER
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

4
boards/nucleo-f446ze/Kconfig
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@ -25,4 +25,8 @@ config BOARD_NUCLEO_F446ZE
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo144/Kconfig"

4
boards/nucleo-f722ze/Kconfig
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@ -25,4 +25,8 @@ config BOARD_NUCLEO_F722ZE
# Put other features for this board (in alphabetical order)
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo144/Kconfig"

4
boards/nucleo-f746zg/Kconfig
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@ -29,4 +29,8 @@ config BOARD_NUCLEO_F746ZG
# Put other features for this board (in alphabetical order)
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo144/Kconfig"

4
boards/nucleo-f767zi/Kconfig
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@ -31,4 +31,8 @@ config BOARD_NUCLEO_F767ZI
# Put other features for this board (in alphabetical order)
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/nucleo144/Kconfig"

6
boards/pyboard/Kconfig
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@ -21,3 +21,9 @@ config BOARD_PYBOARD
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

3
boards/pyboard/Makefile.features
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@ -9,3 +9,6 @@ FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# pyboard provides a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/pyboard/clock.config

5
boards/pyboard/clock.config Normal file
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@ -0,0 +1,5 @@
# pyboard provides a 12MHz HSE so its needs a custom PLL config to output a
# 48MHz clock for USB.
CONFIG_CUSTOM_PLL_PARAMS=y
CONFIG_CLOCK_PLL_M=12
CONFIG_CLOCK_PLL_N=336

6
boards/stm32f429i-disc1/Kconfig
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@ -23,3 +23,9 @@ config BOARD_STM32F429I_DISC1
# Put other features for this board (in alphabetical order)
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

6
boards/stm32f429i-disco/Kconfig
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@ -24,3 +24,9 @@ config BOARD_STM32F429I_DISCO
# Put other features for this board (in alphabetical order)
select HAS_HIGHLEVEL_STDIO
select HAS_RIOTBOOT
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

5
boards/stm32f4discovery/Kconfig
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@ -28,6 +28,11 @@ config BOARD_STM32F4DISCOVERY
# Various other features (if any)
select HAS_ARDUINO
# Clock configuration
select BOARD_HAS_HSE
source "$(RIOTBOARD)/common/stm32/Kconfig"
config ERROR_MODULES_CONFLICT
default "On stm32f4discovery boards there are the same pins for the DAC and/or SPI_0." if MODULE_PERIPH_SPI && MODULE_PERIPH_DAC
depends on BOARD_STM32F4DISCOVERY

6
boards/stm32f723e-disco/Kconfig
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@ -21,3 +21,9 @@ config BOARD_STM32F723E_DISCO
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

3
boards/stm32f723e-disco/Makefile.features
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@ -10,3 +10,6 @@ FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# stm32f723e-disco provides a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/stm32f723e-disco/clock.config

5
boards/stm32f723e-disco/clock.config Normal file
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@ -0,0 +1,5 @@
# stm32f723e-disco provides a 25MHz HSE so they need a custom PLL config
# to remain in 216MHz max clock.
CONFIG_CUSTOM_PLL_PARAMS=y
CONFIG_CLOCK_PLL_M=25
CONFIG_CLOCK_PLL_N=432

6
boards/stm32f769i-disco/Kconfig
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@ -19,3 +19,9 @@ config BOARD_STM32F769I_DISCO
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

3
boards/stm32f769i-disco/Makefile.features
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@ -7,3 +7,6 @@ FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# stm32f769i-disco provides a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/stm32f769i-disco/clock.config

5
boards/stm32f769i-disco/clock.config Normal file
View File

@ -0,0 +1,5 @@
# stm32f769i-disco provides a 25MHz HSE so they need a custom PLL config
# to remain in 216MHz max clock.
CONFIG_CUSTOM_PLL_PARAMS=y
CONFIG_CLOCK_PLL_M=25
CONFIG_CLOCK_PLL_M=432

6
boards/ublox-c030-u201/Kconfig
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@ -21,3 +21,9 @@ config BOARD_UBLOX_C030_U201
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig"

3
boards/ublox-c030-u201/Makefile.features
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@ -9,3 +9,6 @@ FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# ublox-c030-u201 provides a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/ublox-c030-u201/clock.config

5
boards/ublox-c030-u201/clock.config Normal file
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@ -0,0 +1,5 @@
# ublox-c030-u201 provides a 12MHz HSE so its needs a custom PLL config to
# output a 180MHz clock.
CONFIG_CUSTOM_PLL_PARAMS=y
CONFIG_CLOCK_PLL_M=12
CONFIG_CLOCK_PLL_N=360

3
boards/weact-f401cc/Makefile.features
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@ -1,3 +1,6 @@
CPU_MODEL = stm32f401cc
include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features
# weact-f401cc provides a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/weact-f401cc/clock.config

1
boards/weact-f401cc/clock.config Normal file
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@ -0,0 +1 @@
CONFIG_CLOCK_PLL_N=336

3
boards/weact-f401ce/Makefile.features
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@ -1,3 +1,6 @@
CPU_MODEL = stm32f401ce
include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features
# weact-f401ce provides a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/weact-f401ce/clock.config

1
boards/weact-f401ce/clock.config Normal file
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@ -0,0 +1 @@
CONFIG_CLOCK_PLL_N=336

3
boards/weact-f411ce/Makefile.features
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@ -1,3 +1,6 @@
CPU_MODEL = stm32f411ce
include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features
# weact-f411ce provides a custom default Kconfig clock configuration
KCONFIG_ADD_CONFIG += $(RIOTBOARD)/weact-f411ce/clock.config

1
boards/weact-f411ce/clock.config Normal file
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@ -0,0 +1 @@
CONFIG_CLOCK_PLL_N=192

66
cpu/stm32/kconfigs/Kconfig.clk
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@ -11,7 +11,7 @@ config CLOCK_HAS_NO_MCO_PRE
Indicates that the CPU has no MCO prescaler
menu "STM32 clock configuration"
depends on !CPU_FAM_F2 && !CPU_FAM_F4 && !CPU_FAM_F7
depends on CPU_STM32
choice
bool "Clock source selection"
@ -56,9 +56,10 @@ config CUSTOM_PLL_PARAMS
bool "Configure PLL parameters"
depends on USE_CLOCK_PLL
if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
config CLOCK_PLL_M
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
default 4 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
default 1 if CPU_FAM_G0
default 6 if CPU_FAM_G4 && BOARD_HAS_HSE
default 4 if CPU_FAM_G4
@ -70,15 +71,68 @@ config CLOCK_PLL_M
config CLOCK_PLL_N
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
default 120 if BOARD_HAS_HSE && CPU_FAM_F2
default 60 if CPU_FAM_F2
default 168 if CPU_FAM_F4 && CLOCK_MAX_84MHZ && BOARD_HAS_HSE
default 84 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
default 96 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 48 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 100 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE
default 50 if CPU_FAM_F4 && CLOCK_MAX_100MHZ
default 168 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 84 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 180 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE
default 90 if CPU_FAM_F4 && CLOCK_MAX_180MHZ
default 216 if CPU_FAM_F7 && BOARD_HAS_HSE
default 108 if CPU_FAM_F7
default 16 if CPU_FAM_WB
default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX
default 27 if CPU_FAM_L5
default 20 if CPU_FAM_G0 || CPU_FAM_L4
default 85 if CPU_FAM_G4
range 8 86 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5
range 50 432 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
range 8 127 if CPU_FAM_G4
range 6 127 if CPU_FAM_WB
if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
choice
bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS
default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
default PLL_P_DIV_2
config PLL_P_DIV_2
bool "Divide by 2"
config PLL_P_DIV_4
bool "Divide by 4"
config PLL_P_DIV_6
bool "Divide by 6"
config PLL_P_DIV_8
bool "Divide by 8"
endchoice
config CLOCK_PLL_P
int
default 2 if PLL_P_DIV_2
default 4 if PLL_P_DIV_4
default 6 if PLL_P_DIV_6
default 8 if PLL_P_DIV_8
config CLOCK_PLL_Q
int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS
default 5 if CPU_FAM_F2
default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ
default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 9 if CPU_FAM_F7
default 8
range 2 15
endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
if CPU_FAM_G0 || CPU_FAM_WB
config CLOCK_PLL_R
int "Q: VCO division factor" if CUSTOM_PLL_PARAMS
@ -115,7 +169,7 @@ config CLOCK_PLL_R
default 8 if PLL_R_DIV_8
endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
endif # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3
config CLOCK_PLL_PREDIV
@ -313,8 +367,8 @@ endif # CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
choice
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
default CLOCK_APB1_DIV_4 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB1_DIV_2 if CPU_FAM_F1 || CPU_FAM_F3
default CLOCK_APB1_DIV_4 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB1_DIV_2 if CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_F4
default CLOCK_APB1_DIV_1
config CLOCK_APB1_DIV_1
@ -345,7 +399,7 @@ config CLOCK_APB1_DIV
choice
bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
depends on !CPU_FAM_G0 && !CPU_FAM_F0
default CLOCK_APB2_DIV_2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB2_DIV_2 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB2_DIV_1
config CLOCK_APB2_DIV_1

15
cpu/stm32/kconfigs/f4/Kconfig
View File

@ -21,3 +21,18 @@ config HAS_CPU_STM32F4
bool
help
Indicates that the cpu being used belongs to the 'stm32f4' family.
config CLOCK_MAX_84MHZ
bool
help
Indicates that the CPU max core clock frequency is 84MHz
config CLOCK_MAX_100MHZ
bool
help
Indicates that the CPU max core clock frequency is 100MHz
config CLOCK_MAX_180MHZ
bool
help
Indicates that the CPU max core clock frequency is 180MHz

23
cpu/stm32/kconfigs/f4/Kconfig.lines
View File

@ -13,99 +13,122 @@
config CPU_LINE_STM32F401XC
bool
select CPU_FAM_F4
select CLOCK_MAX_84MHZ
config CPU_LINE_STM32F401XE
bool
select CPU_FAM_F4
select CLOCK_MAX_84MHZ
config CPU_LINE_STM32F405XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F407XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F410CX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F410RX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F410TX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F411XE
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F412CX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F412RX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F412VX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F412ZX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F413XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F415XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F417XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F423XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F427XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F429XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F437XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F439XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F446XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F469XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F479XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ