boards/nrf5340dk-app: add initial support

Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>

boards/nrf5340dk-app/Makefile

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+MODULE = board
+
+include $(RIOTBASE)/Makefile.base

boards/nrf5340dk-app/Makefile.features

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+CPU_MODEL = nrf5340_app
+CPU = nrf53
+
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+FEATURES_PROVIDED += periph_uart_hw_fc

boards/nrf5340dk-app/Makefile.include

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+# include this module into the build
+INCLUDES += -I$(RIOTBOARD)/nrf5340dk-app/include

boards/nrf5340dk-app/doc.txt

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+/**
+@defgroup    boards_nrf5340dk-app nRF5340DK
+@ingroup     boards
+@brief       Support for the nRF5340DK-app board
+
+### General information
+
+The nRF5340DK is a devboard based on nRF5340 MCU which offers a dual core
+Cortex-M33 with one application core and one network core.
+The network core is able to handle Bluetooth 5.3, BLE, mesh, NFC, Thread and
+Zigbee connectivity.
+Currently only the application core can be used with RIOT-OS.
+
+The board features four LEDs, four user buttons/switches and a reset button.
+
+### Links
+
+- [nRF5340DK web page](https://infocenter.nordicsemi.com/topic/ug_nrf5340_dk/UG/dk/intro.html)
+- [documentation and hardware description](https://infocenter.nordicsemi.com/index.jsp?topic=%2Fstruct_nrf53%2Fstruct%2Fnrf5340.html)
+
+### Flash the board
+
+The board is flashed using JLink or nrfjprog software. Programs needs to
+be installed.
+
+The process is automated in the usual `make flash` target.
+
+### Accessing STDIO via UART
+
+The STDIO is directly accessible via the USB port. On a Linux host, it's
+generally mapped to `/dev/ttyACM0`.
+
+Use the `term` target to connect to the board serial port<br/>
+```
+    make BOARD=nrf5340dk-app -C examples/hello-world term
+```
+
+ */

boards/nrf5340dk-app/include/board.h

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+/*
+ * Copyright (C) 2023 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nrf5340dk-app
+ * @{
+ *
+ * @file
+ * @brief       Board configuration for the nRF5340DK-app board
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include "cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   System core clock speed, for all NRF53 Application core.
+ */
+#define CLOCK_CORECLOCK     MHZ(128)
+
+/**
+ * @name    HF Clock configuration
+ *
+ *
+ * @{
+ */
+
+ /* CLOCK_HFCLKSRC_SRC_HFXO to use external 32MHz crystal
+  *   CLOCK_HFCLKSRC_SRC_HFINT to use internal crystal */
+#define CLOCK_HFCLK         (CLOCK_HFCLKSRC_SRC_HFXO) /**< HFCLK Source selection */
+#define CLOCK_LFCLK         (3) /**< LFCLK Source selection */
+/** @} */
+
+/**
+ * @name    LED pin configuration
+ * @{
+ */
+#define LED0_PIN            GPIO_PIN(0, 28) /**< LED0 pin definition */
+#define LED1_PIN            GPIO_PIN(0, 29) /**< LED1 pin definition */
+#define LED2_PIN            GPIO_PIN(0, 30) /**< LED2 pin definition */
+#define LED3_PIN            GPIO_PIN(0, 31) /**< LED3 pin definition */
+
+#define LED0_MASK           (1 << 28)       /**< LED0 PORT bitmask */
+#define LED1_MASK           (1 << 29)       /**< LED1 PORT bitmask */
+#define LED2_MASK           (1 << 30)       /**< LED2 PORT bitmask */
+#define LED3_MASK           (1 << 31)       /**< LED3 PORT bitmask */
+
+#define LED_PORT            (NRF_P0_S) /**< Default LED PORT */
+
+#define LED0_ON             (LED_PORT->OUTCLR = LED0_MASK) /**< LED0 ON macro */
+#define LED0_OFF            (LED_PORT->OUTSET = LED0_MASK) /**< LED0 OFF macro */
+#define LED0_TOGGLE         (LED_PORT->OUT   ^= LED0_MASK) /**< LED0 toggle macro */
+
+#define LED1_ON             (LED_PORT->OUTCLR = LED1_MASK) /**< LED1 ON macro */
+#define LED1_OFF            (LED_PORT->OUTSET = LED1_MASK) /**< LED1 OFF macro */
+#define LED1_TOGGLE         (LED_PORT->OUT   ^= LED1_MASK) /**< LED1 toggle macro */
+
+#define LED2_ON             (LED_PORT->OUTCLR = LED2_MASK) /**< LED2 ON macro */
+#define LED2_OFF            (LED_PORT->OUTSET = LED2_MASK) /**< LED2 OFF macro */
+#define LED2_TOGGLE         (LED_PORT->OUT   ^= LED2_MASK) /**< LED2 toggle macro */
+
+#define LED3_ON             (LED_PORT->OUTCLR = LED3_MASK) /**< LED3 ON macro */
+#define LED3_OFF            (LED_PORT->OUTSET = LED3_MASK) /**< LED3 OFF macro */
+#define LED3_TOGGLE         (LED_PORT->OUT   ^= LED3_MASK) /**< LED3 toggle macro */
+/** @} */
+
+/**
+ * @name    Button pin configuration
+ * @{
+ */
+#define BTN0_PIN            GPIO_PIN(0, 23)  /**< BTN0 pin definition */
+#define BTN0_MODE           GPIO_IN_PU       /**< BTN0 default mode */
+#define BTN1_PIN            GPIO_PIN(0, 24)  /**< BTN1 pin definition */
+#define BTN1_MODE           GPIO_IN_PU       /**< BTN1 default mode */
+#define BTN2_PIN            GPIO_PIN(0, 8)   /**< BTN2 pin definition */
+#define BTN2_MODE           GPIO_IN_PU       /**< BTN2 default mode */
+#define BTN3_PIN            GPIO_PIN(0, 9)   /**< BTN3 pin definition */
+#define BTN3_MODE           GPIO_IN_PU       /**< BTN3 default mode */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+/** @} */

boards/nrf5340dk-app/include/periph_conf.h

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+/*
+ * Copyright (C) 2023 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup    boards_nrf5340dk-app
+ * @{
+ *
+ * @file
+ * @brief       Peripheral configuration for the nRF5340DK-app
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ *
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "periph_cpu.h"
+
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name   Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = NRF_TIMER0_S,
+        .channels = 5,
+        .bitmode  = TIMER_BITMODE_BITMODE_32Bit,
+        .irqn     = TIMER0_IRQn
+    },
+    {
+        .dev      = NRF_TIMER1_S,
+        .channels = 5,
+        .bitmode  = TIMER_BITMODE_BITMODE_32Bit,
+        .irqn     = TIMER1_IRQn
+    },
+};
+
+#define TIMER_0_ISR         isr_timer0 /**< Timer0 IRQ*/
+#define TIMER_1_ISR         isr_timer1 /**< Timer1 IRQ */
+
+#define TIMER_NUMOF         ARRAY_SIZE(timer_config) /**< Timer configuration NUMOF */
+/** @} */
+
+/**
+ * @name    UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+    {
+        .dev        = NRF_UARTE0_S,
+        .rx_pin     = GPIO_PIN(1, 0),
+        .tx_pin     = GPIO_PIN(1, 1),
+#ifdef MODULE_PERIPH_UART_HW_FC
+        .rts_pin    = GPIO_UNDEF,
+        .cts_pin    = GPIO_UNDEF,
+#endif
+        .irqn       = SERIAL0_IRQn,
+    },
+};
+
+#define UART_0_ISR          (isr_serial0) /**< SERIAL0_IRQn */
+
+#define UART_NUMOF          ARRAY_SIZE(uart_config) /**< UART configuration NUMOF */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */