From fe28f93691f8bd5a875d327b742a5af5b7df860e Mon Sep 17 00:00:00 2001 From: Joshua DeWeese Date: Thu, 18 May 2023 16:46:23 -0400 Subject: [PATCH] cpu/stm32/periph/adc: fix setting ADC clock The current implementation uses the core clock frequency to calculate the needed prescalar to achieve a given ADC clock frequency. This is incorrect. This patch fixes the calculation to use the correct source clock (PCKLK2 ie APB2). It also changes the defined max clock rate to use the frequency macro to improve readability. --- cpu/stm32/periph/adc_f1.c | 4 ++-- cpu/stm32/periph/adc_f2.c | 4 ++-- cpu/stm32/periph/adc_f4_f7.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu/stm32/periph/adc_f1.c b/cpu/stm32/periph/adc_f1.c index 2323598137..bb1e1aa2b8 100644 --- a/cpu/stm32/periph/adc_f1.c +++ b/cpu/stm32/periph/adc_f1.c @@ -28,7 +28,7 @@ /** * @brief Maximum allowed ADC clock speed */ -#define MAX_ADC_SPEED (14000000U) +#define MAX_ADC_SPEED MHZ(14) /** * @brief Allocate locks for all three available ADC devices @@ -93,7 +93,7 @@ int adc_init(adc_t line) } /* set clock prescaler to get the maximal possible ADC clock value */ for (clk_div = 2; clk_div < 8; clk_div += 2) { - if ((CLOCK_CORECLOCK / clk_div) <= MAX_ADC_SPEED) { + if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) { break; } } diff --git a/cpu/stm32/periph/adc_f2.c b/cpu/stm32/periph/adc_f2.c index b6c7acaf96..8f75c5e3a9 100644 --- a/cpu/stm32/periph/adc_f2.c +++ b/cpu/stm32/periph/adc_f2.c @@ -29,7 +29,7 @@ /** * @brief Maximum allowed ADC clock speed */ -#define MAX_ADC_SPEED (12000000U) +#define MAX_ADC_SPEED MHZ(12) /** * @brief Default VBAT undefined value @@ -86,7 +86,7 @@ int adc_init(adc_t line) } /* set clock prescaler to get the maximal possible ADC clock value */ for (clk_div = 2; clk_div < 8; clk_div += 2) { - if ((CLOCK_CORECLOCK / clk_div) <= MAX_ADC_SPEED) { + if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) { break; } } diff --git a/cpu/stm32/periph/adc_f4_f7.c b/cpu/stm32/periph/adc_f4_f7.c index a36a80282a..4c1dfa4b97 100644 --- a/cpu/stm32/periph/adc_f4_f7.c +++ b/cpu/stm32/periph/adc_f4_f7.c @@ -28,7 +28,7 @@ /** * @brief Maximum allowed ADC clock speed */ -#define MAX_ADC_SPEED (12000000U) +#define MAX_ADC_SPEED MHZ(12) /** * @brief Maximum sampling time for each channel (480 cycles) @@ -94,7 +94,7 @@ int adc_init(adc_t line) dev(line)->CR2 = ADC_CR2_ADON; /* set clock prescaler to get the maximal possible ADC clock value */ for (clk_div = 2; clk_div < 8; clk_div += 2) { - if ((CLOCK_CORECLOCK / clk_div) <= MAX_ADC_SPEED) { + if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) { break; } }