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cpu/sam3: adapted GPIO driver

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This commit is contained in:
Hauke Petersen 2016-02-20 15:23:48 +01:00
parent af84a5e7aa
commit f389754de3
2 changed files with 50 additions and 26 deletions
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25
cpu/sam3/include/periph_cpu.h
View File

@ -71,15 +71,28 @@ typedef uint32_t gpio_t;
#define TIMER_CHANNELS (3)
/**
* @brief Override values for pull register configuration
* @brief Generate GPIO mode bitfields
*
* We use 3 bit to determine the pin functions:
* - bit 0: in/out
* - bit 1: PU enable
* - bit 2: OD enable
*/
#define GPIO_MODE(io, pu, od) (io | (pu << 1) | (od << 2))
/**
* @brief Override GPIO modes
* @{
*/
#define HAVE_GPIO_PP_T
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_NOPULL = 4, /**< do not use internal pull resistors */
GPIO_PULLUP = 9, /**< enable internal pull-up resistor */
GPIO_PULLDOWN = 8 /**< enable internal pull-down resistor */
} gpio_pp_t;
GPIO_IN = GPIO_MODE(0, 0, 0), /**< IN */
GPIO_IN_PD = 0xf, /**< not supported by HW */
GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< IN with pull-up */
GPIO_OUT = GPIO_MODE(1, 0, 0), /**< OUT (push-pull) */
GPIO_OD = GPIO_MODE(1, 0, 1), /**< OD */
GPIO_OD_PU = GPIO_MODE(1, 1, 1), /**< OD with pull-up */
} gpio_mode_t;
/** @} */
/**

51
cpu/sam3/periph/gpio.c
View File

@ -42,6 +42,15 @@
*/
#define CTX_NUMOF (7U)
/**
* @brief Bit positions in the GPIO mode value
* @{
*/
#define MODE_BIT_IO (0x1)
#define MODE_BIT_PUE (0x2)
#define MODE_BIT_ODE (0x4)
/** @} */
/**
* @brief Allocation of memory for 7 independent interrupt slots
*/
@ -137,14 +146,14 @@ static void _ctx_clear(int port, int pin)
}
}
int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pushpull)
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
Pio *port = _port(pin);
int pin_num = _pin_num(pin);
int port_num = _port_num(pin);
/* make sure port is valid */
if (!_port_valid(port)) {
/* make sure port is valid and no pull-down is selected*/
if (!_port_valid(port) || (mode == GPIO_IN_PD)) {
return -1;
}
@ -157,31 +166,33 @@ int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pushpull)
/* give the PIO module the power over the corresponding pin */
port->PIO_PER = (1 << pin_num);
/* configure the pin's pull resistor state */
switch (pushpull) {
case GPIO_PULLDOWN:
return -1;
case GPIO_PULLUP:
port->PIO_PUER = (1 << pin_num);
break;
case GPIO_NOPULL:
port->PIO_PUDR = (1 << pin_num);
break;
}
if (dir == GPIO_DIR_OUT) {
/* configure pin as output */
/* configure pin direction (in/out) */
if (mode & MODE_BIT_IO) {
port->PIO_OER = (1 << pin_num);
port->PIO_CODR = (1 << pin_num);
}
else {
/* configure pin as input */
port->PIO_ODR = (1 << pin_num);
}
/* set pull-up */
if (mode & MODE_BIT_PUE) {
port->PIO_PUER = (1 << pin_num);
}
else {
port->PIO_PUDR = (1 << pin_num);
}
/* set multi-driver (open-drain) mode */
if (mode & MODE_BIT_ODE) {
port->PIO_MDER = (1 << pin_num);
}
else {
port->PIO_MDDR = (1 << pin_num);
}
return 0;
}
int gpio_init_int(gpio_t pin, gpio_pp_t pushpull, gpio_flank_t flank,
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
Pio *port = _port(pin);
@ -194,7 +205,7 @@ int gpio_init_int(gpio_t pin, gpio_pp_t pushpull, gpio_flank_t flank,
}
/* configure pin as input */
gpio_init(pin, GPIO_DIR_IN, pushpull);
gpio_init(pin, mode);
/* try go grab a free spot in the context array */
int ctx_num = _get_free_ctx();