mirror of
https://github.com/RIOT-OS/RIOT.git
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Merge pull request #9096 from OTAkeys/pr/stm32_cpu_line
cpu/stm32: add CPU_LINE_* variable and use it for stm32f0 and stm32f4
This commit is contained in:
Vincent Dupont
GitHub
commit
f4c01499c6
@ -21,12 +21,25 @@ LINKER_SCRIPT ?= stm32_common.ld
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# export the common include directory
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export INCLUDES += -I$(RIOTCPU)/stm32_common/include
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# Compute ROM_LEN and RAM_LEN
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include $(RIOTCPU)/stm32_common/stm32_mem_lengths.mk
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KB := 1024
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LEN := $(shell echo $(ROM_LEN) | sed 's/K//')
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FLASHSIZE := $(shell echo $$(( $(LEN) * $(KB) )) )
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# Get CPU_LINE_ variable
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-include $(RIOTCPU)/$(CPU)/stm32_line.mk
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CPU_LINE ?= $(shell echo $(CPU_MODEL) | cut -c -9 | tr 'a-z-' 'A-Z_')xx
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# Set CFLAGS
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export CFLAGS += -D$(CPU_LINE) -DCPU_LINE_$(CPU_LINE)
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export CFLAGS += -DSTM32_FLASHSIZE=$(FLASHSIZE)U
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info-stm32:
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@$(COLOR_ECHO) "CPU: $(CPU_MODEL)"
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@$(COLOR_ECHO) "\tLine: $(CPU_LINE)"
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@$(COLOR_ECHO) "\tPin count:\t$(STM32_PINCOUNT)"
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@$(COLOR_ECHO) "\tROM size:\t$(ROM_LEN)"
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@$(COLOR_ECHO) "\tROM size:\t$(ROM_LEN) ($(FLASHSIZE) Bytes)"
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@$(COLOR_ECHO) "\tRAM size:\t$(RAM_LEN)"
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ifneq (,$(CCMRAM_LEN))
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@ -25,27 +25,8 @@
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#include "cpu_conf_common.h"
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#ifdef CPU_MODEL_STM32F051R8
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#include "vendor/stm32f051x8.h"
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#endif
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#ifdef CPU_MODEL_STM32F091RC
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#include "vendor/stm32f091xc.h"
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#endif
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#ifdef CPU_MODEL_STM32F072RB
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#include "vendor/stm32f072xb.h"
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#endif
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#ifdef CPU_MODEL_STM32F070RB
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#include "vendor/stm32f070xb.h"
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#endif
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#ifdef CPU_MODEL_STM32F030R8
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#include "vendor/stm32f030x8.h"
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#endif
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#ifdef CPU_MODEL_STM32F042K6
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#include "vendor/stm32f042x6.h"
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#endif
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#ifdef CPU_MODEL_STM32F031K6
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#include "vendor/stm32f031x6.h"
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#endif
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#include "vendor/stm32f0xx.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -55,13 +36,13 @@ extern "C" {
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#if defined(CPU_MODEL_STM32F030R8)
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#if defined(CPU_LINE_STM32F030x8)
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#define CPU_IRQ_NUMOF (29U)
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#elif defined(CPU_MODEL_STM32F031K6)
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#elif defined(CPU_LINE_STM32F031x6)
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#define CPU_IRQ_NUMOF (28U)
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#elif defined(CPU_MODEL_STM32F051R8) || defined(CPU_MODEL_STM32F091RC)
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#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F091xC)
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#define CPU_IRQ_NUMOF (31U)
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#else /* CPU_MODEL_STM32F042K6, CPU_MODEL_STM32F070RB, CPU_MODEL_STM32F072RB */
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#else
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#define CPU_IRQ_NUMOF (32U)
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#endif
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/** @} */
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@ -74,21 +55,14 @@ extern "C" {
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*
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* @{
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*/
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#if defined(CPU_MODEL_STM32F091RC) || defined(CPU_MODEL_STM32F072RB)
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#if defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB)
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#define FLASHPAGE_SIZE (2048U)
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#elif defined(CPU_MODEL_STM32F051R8) || defined(CPU_MODEL_STM32F042K6) \
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|| defined(CPU_MODEL_STM32F070RB) || defined(CPU_MODEL_STM32F030R8)
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#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
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|| defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8)
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#define FLASHPAGE_SIZE (1024U)
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#endif
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#if defined(CPU_MODEL_STM32F091RC)
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#define FLASHPAGE_NUMOF (128U)
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#elif defined(CPU_MODEL_STM32F051R8) || defined(CPU_MODEL_STM32F072RB) \
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|| defined(CPU_MODEL_STM32F030R8) || defined(CPU_MODEL_STM32F070RB)
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#define FLASHPAGE_NUMOF (64U)
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#elif defined(CPU_MODEL_STM32F042K6)
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#define FLASHPAGE_NUMOF (32U)
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#endif
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#define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
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/* The minimum block size which can be written is 2B. However, the erase
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* block is always FLASHPAGE_SIZE.
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242
cpu/stm32f0/include/vendor/stm32f0xx.h
vendored
Normal file
242
cpu/stm32f0/include/vendor/stm32f0xx.h
vendored
Normal file
@ -0,0 +1,242 @@
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/**
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******************************************************************************
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* @file stm32f0xx.h
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* @author MCD Application Team
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* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32F0xx device used in the target application
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* - To use or not the peripherals drivers in application code(i.e.
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* code will be based on direct access to peripherals registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f0xx
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* @{
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*/
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#ifndef __STM32F0xx_H
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#define __STM32F0xx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/**
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* @brief STM32 Family
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*/
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#if !defined (STM32F0)
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#define STM32F0
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#endif /* STM32F0 */
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/* Uncomment the line below according to the target STM32 device used in your
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application
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*/
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#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
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!defined (STM32F031x6) && !defined (STM32F038xx) && \
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!defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
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!defined (STM32F051x8) && !defined (STM32F058xx) && \
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!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
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!defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
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/* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
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/* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
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/* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
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/* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
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/* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
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/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
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/* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
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/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
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/* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
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/* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
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/* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
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/* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
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/* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
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/* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
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/* #define STM32F091xC */ /*!< STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */
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/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_HAL_DRIVER */
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V2.3.2
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*/
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#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
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#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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#define __STM32F0_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
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#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
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|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\
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|(__STM32F0_DEVICE_VERSION_SUB2 << 8 )\
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|(__STM32F0_DEVICE_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(STM32F030x6)
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#include "stm32f030x6.h"
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#elif defined(STM32F030x8)
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#include "stm32f030x8.h"
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#elif defined(STM32F031x6)
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#include "stm32f031x6.h"
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#elif defined(STM32F038xx)
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#include "stm32f038xx.h"
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#elif defined(STM32F042x6)
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#include "stm32f042x6.h"
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#elif defined(STM32F048xx)
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#include "stm32f048xx.h"
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#elif defined(STM32F051x8)
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#include "stm32f051x8.h"
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#elif defined(STM32F058xx)
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#include "stm32f058xx.h"
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#elif defined(STM32F070x6)
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#include "stm32f070x6.h"
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#elif defined(STM32F070xB)
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#include "stm32f070xb.h"
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#elif defined(STM32F071xB)
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#include "stm32f071xb.h"
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#elif defined(STM32F072xB)
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#include "stm32f072xb.h"
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#elif defined(STM32F078xx)
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#include "stm32f078xx.h"
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#elif defined(STM32F091xC)
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#include "stm32f091xc.h"
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#elif defined(STM32F098xx)
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#include "stm32f098xx.h"
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#elif defined(STM32F030xC)
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#include "stm32f030xc.h"
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#else
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#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
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#endif
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/**
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* @}
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*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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{
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ERROR = 0,
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SUCCESS = !ERROR
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} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Exported_macros
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* @{
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*/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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/**
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* @}
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*/
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#if defined (USE_HAL_DRIVER)
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#include "stm32f0xx_hal.h"
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#endif /* USE_HAL_DRIVER */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __STM32F0xx_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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27
cpu/stm32f0/stm32_line.mk
Normal file
27
cpu/stm32f0/stm32_line.mk
Normal file
@ -0,0 +1,27 @@
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# Compute CPU_LINE
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LINE := $(shell echo $(CPU_MODEL) | tr 'a-z-' 'A-Z_' | sed -E -e 's/^STM32F([0-9][0-9][0-9])(.)(.)/\1 \2 \3/')
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TYPE := $(word 1, $(LINE))
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MODEL1 := $(word 2, $(LINE))
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MODEL2 := $(word 3, $(LINE))
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ifneq (, $(filter $(TYPE), 030 031 042 070))
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ifneq (, $(filter $(MODEL2), 4 6))
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CPU_LINE = STM32F$(TYPE)x6
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else ifneq (, $(filter $(MODEL2), 8))
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CPU_LINE = STM32F$(TYPE)x8
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else ifneq (, $(filter $(MODEL2), B))
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CPU_LINE = STM32F$(TYPE)xB
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endif
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else ifneq (, $(filter $(TYPE), 051))
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CPU_LINE = STM32F$(TYPE)x8
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else ifneq (, $(filter $(TYPE), 071 072))
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CPU_LINE = STM32F$(TYPE)xB
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else ifneq (, $(filter $(TYPE), 091))
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CPU_LINE = STM32F$(TYPE)xC
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else
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CPU_LINE = STM32F$(TYPE)xx
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endif
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ifeq ($(CPU_LINE), )
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$(error Unsupported CPU)
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endif
|
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@ -80,7 +80,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
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[22] = isr_tim17, /* [22] TIM17 global Interrupt */
|
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[25] = isr_spi1, /* [25] SPI1 global Interrupt */
|
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|
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#if defined(CPU_MODEL_STM32F030R8)
|
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#if defined(CPU_LINE_STM32F030x8)
|
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[ 4] = isr_rcc, /* [ 4] RCC global Interrupt */
|
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[ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */
|
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[ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupt */
|
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@ -97,7 +97,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
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[26] = isr_spi2, /* [26] SPI2 global Interrupt */
|
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[27] = isr_usart1, /* [27] USART1 global Interrupt */
|
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[28] = isr_usart2, /* [28] USART2 global Interrupt */
|
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#elif defined(CPU_MODEL_STM32F031K6)
|
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#elif defined(CPU_LINE_STM32F031x6)
|
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[ 1] = isr_pvd, /* [ 1] PVD Interrupt through EXTI Lines 16 */
|
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[ 4] = isr_rcc, /* [ 4] RCC global Interrupt */
|
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[ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */
|
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@ -111,7 +111,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
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[15] = isr_tim2, /* [15] TIM2 global Interrupt */
|
||||
[23] = isr_i2c1, /* [23] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
|
||||
[27] = isr_usart1, /* [27] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
|
||||
#elif defined(CPU_MODEL_STM32F042K6)
|
||||
#elif defined(CPU_LINE_STM32F042x6)
|
||||
[ 1] = isr_pvd_vddio2, /* [ 1] PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
|
||||
[ 4] = isr_rcc_crs, /* [ 4] RCC & CRS Global Interrupts */
|
||||
[ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupts */
|
||||
@ -130,7 +130,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[28] = isr_usart2, /* [28] USART2 global Interrupt */
|
||||
[30] = isr_cec_can, /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */
|
||||
[31] = isr_usb, /* [31] USB global Interrupts & EXTI Line18 Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F051R8)
|
||||
#elif defined(CPU_LINE_STM32F051x8)
|
||||
[ 1] = isr_pvd, /* [ 1] PVD Interrupt through EXTI Lines 16 */
|
||||
[ 4] = isr_rcc, /* [ 4] RCC global Interrupt */
|
||||
[ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupts */
|
||||
@ -151,7 +151,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[27] = isr_usart1, /* [27] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
|
||||
[28] = isr_usart2, /* [28] USART2 global Interrupt */
|
||||
[30] = isr_cec_can, /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F070RB)
|
||||
#elif defined(CPU_LINE_STM32F070xB)
|
||||
[ 4] = isr_rcc, /* [ 4] RCC global Interrupt */
|
||||
[ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */
|
||||
[ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupt */
|
||||
@ -171,7 +171,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[28] = isr_usart2, /* [28] USART2 global Interrupt */
|
||||
[29] = isr_usart3_4, /* [29] USART3 and USART4 global Interrupt */
|
||||
[31] = isr_usb, /* [31] USB global Interrupt & EXTI Line18 Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F072RB)
|
||||
#elif defined(CPU_LINE_STM32F072xB)
|
||||
[ 1] = isr_pvd_vddio2, /* [ 1] PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */
|
||||
[ 4] = isr_rcc_crs, /* [ 4] RCC & CRS global Interrupt */
|
||||
[ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */
|
||||
@ -195,7 +195,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[29] = isr_usart3_4, /* [29] USART3 and USART4 global Interrupt */
|
||||
[30] = isr_cec_can, /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */
|
||||
[31] = isr_usb, /* [31] USB global Interrupt & EXTI Line18 Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F091RC)
|
||||
#elif defined(CPU_LINE_STM32F091xC)
|
||||
[ 1] = isr_pvd_vddio2, /* [ 1] PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
|
||||
[ 4] = isr_rcc_crs, /* [ 4] RCC & CRS global Interrupts */
|
||||
[ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupts */
|
||||
|
||||
@ -25,35 +25,7 @@
|
||||
|
||||
#include "cpu_conf_common.h"
|
||||
|
||||
#if defined(CPU_MODEL_STM32F401RE)
|
||||
#include "vendor/stm32f401xe.h"
|
||||
#elif defined(CPU_MODEL_STM32F407VG)
|
||||
#include "vendor/stm32f407xx.h"
|
||||
#elif defined(CPU_MODEL_STM32F410RB)
|
||||
#include "vendor/stm32f410rx.h"
|
||||
#elif defined(CPU_MODEL_STM32F411RE)
|
||||
#include "vendor/stm32f411xe.h"
|
||||
#elif defined(CPU_MODEL_STM32F412ZG)
|
||||
#include "vendor/stm32f412zx.h"
|
||||
#elif defined(CPU_MODEL_STM32F413CG) || defined(CPU_MODEL_STM32F413RG) \
|
||||
|| defined(CPU_MODEL_STM32F413MG) || defined(CPU_MODEL_STM32F413VG) \
|
||||
|| defined(CPU_MODEL_STM32F413ZG) || defined(CPU_MODEL_STM32F413CH) \
|
||||
|| defined(CPU_MODEL_STM32F413RH) || defined(CPU_MODEL_STM32F413MH) \
|
||||
|| defined(CPU_MODEL_STM32F413VH) || defined(CPU_MODEL_STM32F413ZH)
|
||||
#include "vendor/stm32f413xx.h"
|
||||
#elif defined(CPU_MODEL_STM32F415RG)
|
||||
#include "vendor/stm32f415xx.h"
|
||||
#elif defined(CPU_MODEL_STM32F423CH) || defined(CPU_MODEL_STM32F423RH) \
|
||||
|| defined(CPU_MODEL_STM32F423MH) || defined(CPU_MODEL_STM32F423VH) \
|
||||
|| defined(CPU_MODEL_STM32F423ZH)
|
||||
#include "vendor/stm32f423xx.h"
|
||||
#elif defined(CPU_MODEL_STM32F429ZI)
|
||||
#include "vendor/stm32f429xx.h"
|
||||
#elif defined(CPU_MODEL_STM32F437VG)
|
||||
#include "vendor/stm32f437xx.h"
|
||||
#elif defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F446ZE)
|
||||
#include "vendor/stm32f446xx.h"
|
||||
#endif
|
||||
#include "vendor/stm32f4xx.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -64,27 +36,19 @@ extern "C" {
|
||||
* @{
|
||||
*/
|
||||
#define CPU_DEFAULT_IRQ_PRIO (1U)
|
||||
#if defined(CPU_MODEL_STM32F401RE)
|
||||
#if defined(CPU_LINE_STM32F401xE)
|
||||
#define CPU_IRQ_NUMOF (85U)
|
||||
#elif defined(CPU_MODEL_STM32F407VG) || defined(CPU_MODEL_STM32F415RG)
|
||||
#elif defined(CPU_LINE_STM32F407xx) || defined(CPU_LINE_STM32F415xx)
|
||||
#define CPU_IRQ_NUMOF (82U)
|
||||
#elif defined(CPU_MODEL_STM32F410RB)
|
||||
#elif defined(CPU_LINE_STM32F410Rx)
|
||||
#define CPU_IRQ_NUMOF (98U)
|
||||
#elif defined(CPU_MODEL_STM32F411RE)
|
||||
#elif defined(CPU_LINE_STM32F411xE)
|
||||
#define CPU_IRQ_NUMOF (86U)
|
||||
#elif defined(CPU_MODEL_STM32F412ZG) || defined(CPU_MODEL_STM32F446RE) \
|
||||
|| defined(CPU_MODEL_STM32F446ZE)
|
||||
#elif defined(CPU_LINE_STM32F412Zx) || defined(CPU_LINE_STM32F446xx)
|
||||
#define CPU_IRQ_NUMOF (97U)
|
||||
#elif defined(CPU_MODEL_STM32F413CG) || defined(CPU_MODEL_STM32F413RG) \
|
||||
|| defined(CPU_MODEL_STM32F413MG) || defined(CPU_MODEL_STM32F413VG) \
|
||||
|| defined(CPU_MODEL_STM32F413ZG) || defined(CPU_MODEL_STM32F413CH) \
|
||||
|| defined(CPU_MODEL_STM32F413RH) || defined(CPU_MODEL_STM32F413MH) \
|
||||
|| defined(CPU_MODEL_STM32F413VH) || defined(CPU_MODEL_STM32F413ZH) \
|
||||
|| defined(CPU_MODEL_STM32F423CH) || defined(CPU_MODEL_STM32F423RH) \
|
||||
|| defined(CPU_MODEL_STM32F423MH) || defined(CPU_MODEL_STM32F423VH) \
|
||||
|| defined(CPU_MODEL_STM32F423ZH)
|
||||
#elif defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)
|
||||
#define CPU_IRQ_NUMOF (102U)
|
||||
#elif defined(CPU_MODEL_STM32F429ZI) || defined(CPU_MODEL_STM32F437VG)
|
||||
#elif defined(CPU_LINE_STM32F429xx) || defined(CPU_LINE_STM32F437xx)
|
||||
#define CPU_IRQ_NUMOF (91U)
|
||||
#endif
|
||||
#define CPU_FLASH_BASE FLASH_BASE
|
||||
|
||||
@ -48,20 +48,13 @@ enum {
|
||||
/**
|
||||
* @brief Available number of ADC devices
|
||||
*/
|
||||
#if defined(CPU_MODEL_STM32F401RE) || defined(CPU_MODEL_STM32F410RB) \
|
||||
|| defined(CPU_MODEL_STM32F411RE) || defined(CPU_MODEL_STM32F412ZG) \
|
||||
|| defined(CPU_MODEL_STM32F413CG) || defined(CPU_MODEL_STM32F413RG) \
|
||||
|| defined(CPU_MODEL_STM32F413MG) || defined(CPU_MODEL_STM32F413VG) \
|
||||
|| defined(CPU_MODEL_STM32F413ZG) || defined(CPU_MODEL_STM32F413CH) \
|
||||
|| defined(CPU_MODEL_STM32F413RH) || defined(CPU_MODEL_STM32F413MH) \
|
||||
|| defined(CPU_MODEL_STM32F413VH) || defined(CPU_MODEL_STM32F413ZH) \
|
||||
|| defined(CPU_MODEL_STM32F423CH) || defined(CPU_MODEL_STM32F423RH) \
|
||||
|| defined(CPU_MODEL_STM32F423MH) || defined(CPU_MODEL_STM32F423VH) \
|
||||
|| defined(CPU_MODEL_STM32F423ZH)
|
||||
#if defined(CPU_LINE_STM32F401xE) || defined(CPU_LINE_STM32F410Rx) \
|
||||
|| defined(CPU_LINE_STM32F411xE) || defined(CPU_LINE_STM32F412Zx) \
|
||||
|| defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)
|
||||
#define ADC_DEVS (1U)
|
||||
#elif defined(CPU_MODEL_STM32F407VG) || defined(CPU_MODEL_STM32F415RG) \
|
||||
|| defined(CPU_MODEL_STM32F429ZI) || defined(CPU_MODEL_STM32F437VG) \
|
||||
|| defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F446ZE)
|
||||
#elif defined(CPU_LINE_STM32F407xx) || defined(CPU_LINE_STM32F415xx) \
|
||||
|| defined(CPU_LINE_STM32F429xx) || defined(CPU_LINE_STM32F437xx) \
|
||||
|| defined(CPU_LINE_STM32F446xx)
|
||||
#define ADC_DEVS (3U)
|
||||
#endif
|
||||
|
||||
|
||||
271
cpu/stm32f4/include/vendor/stm32f4xx.h
vendored
Normal file
271
cpu/stm32f4/include/vendor/stm32f4xx.h
vendored
Normal file
@ -0,0 +1,271 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.6.1
|
||||
* @date 14-February-2017
|
||||
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F4xx device used in the target application
|
||||
* - To use or not the peripherals drivers in application code(i.e.
|
||||
* code will be based on direct access to peripherals registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32F4xx_H
|
||||
#define __STM32F4xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32F4)
|
||||
#define STM32F4
|
||||
#endif /* STM32F4 */
|
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
|
||||
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
|
||||
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
|
||||
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
|
||||
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
|
||||
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
|
||||
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
|
||||
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
|
||||
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
|
||||
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
|
||||
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
|
||||
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
|
||||
/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
|
||||
STM32F439NI, STM32F429IG and STM32F429II Devices */
|
||||
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
|
||||
STM32F439NI, STM32F439IG and STM32F439II Devices */
|
||||
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
|
||||
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
|
||||
/* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
|
||||
/* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
|
||||
/* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
|
||||
/* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
|
||||
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
|
||||
and STM32F446ZE Devices */
|
||||
/* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
|
||||
STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
|
||||
/* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
|
||||
and STM32F479NG Devices */
|
||||
/* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
|
||||
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
|
||||
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
|
||||
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
|
||||
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
|
||||
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
|
||||
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
/*#define USE_HAL_DRIVER */
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS version number V2.6.1
|
||||
*/
|
||||
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F4xx_CMSIS_VERSION))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F405xx)
|
||||
#include "stm32f405xx.h"
|
||||
#elif defined(STM32F415xx)
|
||||
#include "stm32f415xx.h"
|
||||
#elif defined(STM32F407xx)
|
||||
#include "stm32f407xx.h"
|
||||
#elif defined(STM32F417xx)
|
||||
#include "stm32f417xx.h"
|
||||
#elif defined(STM32F427xx)
|
||||
#include "stm32f427xx.h"
|
||||
#elif defined(STM32F437xx)
|
||||
#include "stm32f437xx.h"
|
||||
#elif defined(STM32F429xx)
|
||||
#include "stm32f429xx.h"
|
||||
#elif defined(STM32F439xx)
|
||||
#include "stm32f439xx.h"
|
||||
#elif defined(STM32F401xC)
|
||||
#include "stm32f401xc.h"
|
||||
#elif defined(STM32F401xE)
|
||||
#include "stm32f401xe.h"
|
||||
#elif defined(STM32F410Tx)
|
||||
#include "stm32f410tx.h"
|
||||
#elif defined(STM32F410Cx)
|
||||
#include "stm32f410cx.h"
|
||||
#elif defined(STM32F410Rx)
|
||||
#include "stm32f410rx.h"
|
||||
#elif defined(STM32F411xE)
|
||||
#include "stm32f411xe.h"
|
||||
#elif defined(STM32F446xx)
|
||||
#include "stm32f446xx.h"
|
||||
#elif defined(STM32F469xx)
|
||||
#include "stm32f469xx.h"
|
||||
#elif defined(STM32F479xx)
|
||||
#include "stm32f479xx.h"
|
||||
#elif defined(STM32F412Cx)
|
||||
#include "stm32f412cx.h"
|
||||
#elif defined(STM32F412Zx)
|
||||
#include "stm32f412zx.h"
|
||||
#elif defined(STM32F412Rx)
|
||||
#include "stm32f412rx.h"
|
||||
#elif defined(STM32F412Vx)
|
||||
#include "stm32f412vx.h"
|
||||
#elif defined(STM32F413xx)
|
||||
#include "stm32f413xx.h"
|
||||
#elif defined(STM32F423xx)
|
||||
#include "stm32f423xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0U,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0U,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ERROR = 0U,
|
||||
SUCCESS = !ERROR
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32f4xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F4xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
23
cpu/stm32f4/stm32_line.mk
Normal file
23
cpu/stm32f4/stm32_line.mk
Normal file
@ -0,0 +1,23 @@
|
||||
# Compute CPU_LINE
|
||||
LINE := $(shell echo $(CPU_MODEL) | tr 'a-z-' 'A-Z_' | sed -E -e 's/^STM32F([0-9][0-9][0-9])(.)(.)/\1 \2 \3/')
|
||||
TYPE := $(word 1, $(LINE))
|
||||
MODEL1 := $(word 2, $(LINE))
|
||||
MODEL2 := $(word 3, $(LINE))
|
||||
|
||||
ifneq (, $(filter $(TYPE), 401))
|
||||
ifneq (, $(filter $(MODEL2), B C))
|
||||
CPU_LINE = STM32F$(TYPE)xC
|
||||
else ifneq (, $(filter $(MODEL2), D E))
|
||||
CPU_LINE = STM32F$(TYPE)xE
|
||||
endif
|
||||
else ifneq (, $(filter $(TYPE), 410 412))
|
||||
CPU_LINE = STM32F$(TYPE)$(MODEL1)x
|
||||
else ifneq (, $(filter $(TYPE), 411))
|
||||
CPU_LINE = STM32F$(TYPE)xE
|
||||
else
|
||||
CPU_LINE = STM32F$(TYPE)xx
|
||||
endif
|
||||
|
||||
ifeq ($(CPU_LINE), )
|
||||
$(error Unsupported CPU)
|
||||
endif
|
||||
@ -186,7 +186,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[71] = isr_usart6, /* [71] USART6 global interrupt */
|
||||
[81] = isr_fpu, /* [81] FPU global interrupt */
|
||||
|
||||
#if defined(CPU_MODEL_STM32F401RE)
|
||||
#if defined(CPU_LINE_STM32F401xE)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */
|
||||
[28] = isr_tim2, /* [28] TIM2 global Interrupt */
|
||||
@ -199,7 +199,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */
|
||||
[73] = isr_i2c3_er, /* [73] I2C3 error interrupt */
|
||||
[84] = isr_spi4, /* [84] SPI4 global Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F407VG)
|
||||
#elif defined(CPU_LINE_STM32F407xx)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */
|
||||
[20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
|
||||
@ -236,7 +236,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */
|
||||
[77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */
|
||||
[78] = isr_dcmi, /* [78] DCMI global interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F410RB)
|
||||
#elif defined(CPU_LINE_STM32F410Rx)
|
||||
[18] = isr_adc, /* [18] ADC1 global Interrupts */
|
||||
[25] = isr_tim1_up, /* [25] TIM1 Update Interrupt */
|
||||
[54] = isr_tim6_dac, /* [54] TIM6 global Interrupt and DAC Global Interrupt */
|
||||
@ -245,7 +245,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[95] = isr_fmpi2c1_ev, /* [95] FMPI2C1 Event Interrupt */
|
||||
[96] = isr_fmpi2c1_er, /* [96] FMPI2C1 Error Interrupt */
|
||||
[97] = isr_lptim1, /* [97] LPTIM1 interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F411RE)
|
||||
#elif defined(CPU_LINE_STM32F411xE)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */
|
||||
[28] = isr_tim2, /* [28] TIM2 global Interrupt */
|
||||
@ -259,7 +259,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[73] = isr_i2c3_er, /* [73] I2C3 error interrupt */
|
||||
[84] = isr_spi4, /* [84] SPI4 global Interrupt */
|
||||
[85] = isr_spi5, /* [85] SPI5 global Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F412ZG)
|
||||
#elif defined(CPU_LINE_STM32F412Zx)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */
|
||||
[20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
|
||||
@ -294,11 +294,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[92] = isr_quadspi, /* [92] QuadSPI global Interrupt */
|
||||
[95] = isr_fmpi2c1_ev, /* [95] FMPI2C1 Event Interrupt */
|
||||
[96] = isr_fmpi2c1_er, /* [96] FMPI2C1 Error Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F413CG) || defined(CPU_MODEL_STM32F413RG) \
|
||||
|| defined(CPU_MODEL_STM32F413MG) || defined(CPU_MODEL_STM32F413VG) \
|
||||
|| defined(CPU_MODEL_STM32F413ZG) || defined(CPU_MODEL_STM32F413CH) \
|
||||
|| defined(CPU_MODEL_STM32F413RH) || defined(CPU_MODEL_STM32F413MH) \
|
||||
|| defined(CPU_MODEL_STM32F413VH) || defined(CPU_MODEL_STM32F413ZH)
|
||||
#elif defined(CPU_LINE_STM32F413xx)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */
|
||||
[20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
|
||||
@ -349,7 +345,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[99] = isr_dfsdm2_flt1, /* [99] DFSDM2 Filter 1 global Interrupt */
|
||||
[100] = isr_dfsdm2_flt2, /* [100] DFSDM2 Filter 2 global Interrupt */
|
||||
[101] = isr_dfsdm2_flt3, /* [101] DFSDM2 Filter 3 global Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F415RG)
|
||||
#elif defined(CPU_LINE_STM32F415xx)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */
|
||||
[20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
|
||||
@ -385,9 +381,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */
|
||||
[79] = isr_cryp, /* [79] CRYP crypto global interrupt */
|
||||
[80] = isr_hash_rng, /* [80] Hash and Rng global interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F423CH) || defined(CPU_MODEL_STM32F423RH) \
|
||||
|| defined(CPU_MODEL_STM32F423MH) || defined(CPU_MODEL_STM32F423VH) \
|
||||
|| defined(CPU_MODEL_STM32F423ZH)
|
||||
#elif defined(CPU_LINE_STM32F423xx)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */
|
||||
[20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
|
||||
@ -439,7 +433,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[99] = isr_dfsdm2_flt1, /* [99] DFSDM2 Filter 1 global Interrupt */
|
||||
[100] = isr_dfsdm2_flt2, /* [100] DFSDM2 Filter 2 global Interrupt */
|
||||
[101] = isr_dfsdm2_flt3, /* [101] DFSDM2 Filter 3 global Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F429ZI)
|
||||
#elif defined(CPU_LINE_STM32F429xx)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */
|
||||
[20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
|
||||
@ -485,7 +479,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[88] = isr_ltdc, /* [88] LTDC global Interrupt */
|
||||
[89] = isr_ltdc_er, /* [89] LTDC Error global Interrupt */
|
||||
[90] = isr_dma2d, /* [90] DMA2D global Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F437VG)
|
||||
#elif defined(CPU_LINE_STM32F437xx)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */
|
||||
[20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
|
||||
@ -531,7 +525,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||
[86] = isr_spi6, /* [86] SPI6 global Interrupt */
|
||||
[87] = isr_sai1, /* [87] SAI1 global Interrupt */
|
||||
[90] = isr_dma2d, /* [90] DMA2D global Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F446ZE)
|
||||
#elif defined(CPU_LINE_STM32F446xx)
|
||||
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */
|
||||
[20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user