From 7ab1ae1b7617547d9657c02951ef3bcbb2e4e2b6 Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Mon, 25 Mar 2019 12:57:57 +0100 Subject: [PATCH 1/6] boards/common/stm32: Clock for F7 216MHz/8MHz/LSE Added file with clock settings for STM32-F7 CPUs with a core clock of 216MHz, an external high speed clock of 8 MHz and external low speed clock (32.768kHz) enabled. --- .../stm32/include/f7/cfg_clock_216_8_1.h | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 boards/common/stm32/include/f7/cfg_clock_216_8_1.h diff --git a/boards/common/stm32/include/f7/cfg_clock_216_8_1.h b/boards/common/stm32/include/f7/cfg_clock_216_8_1.h new file mode 100644 index 0000000000..84183f9884 --- /dev/null +++ b/boards/common/stm32/include/f7/cfg_clock_216_8_1.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2019 Otto-von-Guericke-Universität Magdeburg + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Configure STM32F7 clock to 216MHz and 8MHz HSE using PLL with + * LSE + * + * @author Marian Buschsieweke + * + * @note This is auto-generated from + * `cpu/stm32_common/dist/clk_conf/clk_conf.c` + * @{ + */ + +#ifndef F7_CFG_CLOCK_216_8_1_H +#define F7_CFG_CLOCK_216_8_1_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* give the target core clock (HCLK) frequency [in Hz], + * maximum: 216MHz */ +#define CLOCK_CORECLOCK (216000000U) +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#define CLOCK_HSE (8000000U) +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#define CLOCK_LSE (1U) +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */ +#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */ +#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) + +/* Main PLL factors */ +#define CLOCK_PLL_M (4) +#define CLOCK_PLL_N (216) +#define CLOCK_PLL_P (2) +#define CLOCK_PLL_Q (9) + +#ifdef __cplusplus +} +#endif + +#endif /* F7_CFG_CLOCK_216_8_1_H */ +/** @} */ From 17fd6941ce5b496fb55fe0b7ad1f041cb6447410 Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Mon, 25 Mar 2019 13:02:11 +0100 Subject: [PATCH 2/6] boards/common/stm32: SPI divtable for 108MHz/54MHz --- .../common/stm32/include/cfg_spi_divtable.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/boards/common/stm32/include/cfg_spi_divtable.h b/boards/common/stm32/include/cfg_spi_divtable.h index 3ced360e94..4d5951cd00 100644 --- a/boards/common/stm32/include/cfg_spi_divtable.h +++ b/boards/common/stm32/include/cfg_spi_divtable.h @@ -111,6 +111,15 @@ extern "C" { 1 /* -> 12500000Hz */ \ }, +#define CFG_SPIDIV_54 \ + { /* for 54000000Hz */ \ + 7, /* -> 210937Hz */ \ + 6, /* -> 421875Hz */ \ + 5, /* -> 843750Hz */ \ + 3, /* -> 3375000Hz */ \ + 2 /* -> 6750000Hz */ \ + }, + #define CFG_SPIDIV_60 \ { /* for 60000000Hz */ \ 7, /* -> 234375Hz */ \ @@ -173,6 +182,15 @@ extern "C" { 3, /* -> 6250000Hz */ \ 2 /* -> 12500000Hz */ \ }, + +#define CFG_SPIDIV_108 \ + { /* for 108000000Hz */ \ + 7, /* -> 421875Hz */ \ + 7, /* -> 421875Hz */ \ + 6, /* -> 843750Hz */ \ + 4, /* -> 3375000Hz */ \ + 3 /* -> 6750000Hz */ \ + }, /** @} */ @@ -203,6 +221,8 @@ static const uint8_t spi_divtable[2][5] = { CFG_SPIDIV_48 #elif (CLOCK_APB1 == 50000000) CFG_SPIDIV_50 +#elif (CLOCK_APB1 == 54000000) + CFG_SPIDIV_54 #elif (CLOCK_APB1 == 72000000) CFG_SPIDIV_72 #elif (CLOCK_APB1 == 60000000) @@ -253,6 +273,8 @@ static const uint8_t spi_divtable[2][5] = { CFG_SPIDIV_96 #elif (CLOCK_APB2 == 100000000) CFG_SPIDIV_100 +#elif (CLOCK_APB2 == 108000000) + CFG_SPIDIV_108 #else #error "CFG_SPI_DIVTABLE: no prescalers for selected APB2 bus clock defined" #endif From d00becbc4bafcdf2ae7486a65fb1641c05bccc72 Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Mon, 25 Mar 2019 13:05:17 +0100 Subject: [PATCH 3/6] boards/nucleo-f767zi: Use shared clock settings Use boards/common/stm32/include/f7/cfg_clock_216_8_1.h for core clock settings --- boards/nucleo-f767zi/include/periph_conf.h | 32 +--------------------- 1 file changed, 1 insertion(+), 31 deletions(-) diff --git a/boards/nucleo-f767zi/include/periph_conf.h b/boards/nucleo-f767zi/include/periph_conf.h index 1da0d7c9d1..1defdc6534 100644 --- a/boards/nucleo-f767zi/include/periph_conf.h +++ b/boards/nucleo-f767zi/include/periph_conf.h @@ -22,43 +22,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f7/cfg_clock_216_8_1.h" #include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 216MHz */ -#define CLOCK_CORECLOCK (216000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) - -/* Main PLL factors */ -#define CLOCK_PLL_M (4) -#define CLOCK_PLL_N (216) -#define CLOCK_PLL_P (2) -#define CLOCK_PLL_Q (9) -/** @} */ - /** * @name DMA streams configuration * @{ From 61e1068eba8fc69f9fdb409d148dc6357bbf5586 Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Mon, 25 Mar 2019 13:06:39 +0100 Subject: [PATCH 4/6] boards/nucleo-f767zi: Add SPI settings --- boards/nucleo-f767zi/Makefile.features | 1 + boards/nucleo-f767zi/include/periph_conf.h | 24 ++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/boards/nucleo-f767zi/Makefile.features b/boards/nucleo-f767zi/Makefile.features index bfff4d4a86..0c6484490e 100644 --- a/boards/nucleo-f767zi/Makefile.features +++ b/boards/nucleo-f767zi/Makefile.features @@ -2,6 +2,7 @@ FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_spi FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_uart diff --git a/boards/nucleo-f767zi/include/periph_conf.h b/boards/nucleo-f767zi/include/periph_conf.h index 1defdc6534..0728ec4990 100644 --- a/boards/nucleo-f767zi/include/periph_conf.h +++ b/boards/nucleo-f767zi/include/periph_conf.h @@ -24,6 +24,7 @@ #include "periph_cpu.h" #include "f7/cfg_clock_216_8_1.h" #include "cfg_i2c1_pb8_pb9.h" +#include "cfg_spi_divtable.h" #ifdef __cplusplus extern "C" { @@ -123,6 +124,29 @@ static const uart_conf_t uart_config[] = { #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) /** @} */ +/** + * @name SPI configuration + * + * @note The spi_divtable is auto-generated from + * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` + * @{ + */ +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_UNDEF, + .af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2 + }, +}; + +#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) +/** @} */ + #ifdef __cplusplus } #endif From 54b621bf3ea98bc23a96691c981c8d7158a67741 Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Mon, 25 Mar 2019 13:08:46 +0100 Subject: [PATCH 5/6] boards/nucleo-f722ze: Use shared clock settings Use boards/common/stm32/include/f7/cfg_clock_216_8_1.h for core clock settings --- boards/nucleo-f722ze/include/periph_conf.h | 32 +--------------------- 1 file changed, 1 insertion(+), 31 deletions(-) diff --git a/boards/nucleo-f722ze/include/periph_conf.h b/boards/nucleo-f722ze/include/periph_conf.h index 0535821b6f..ae076837b5 100644 --- a/boards/nucleo-f722ze/include/periph_conf.h +++ b/boards/nucleo-f722ze/include/periph_conf.h @@ -22,43 +22,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f7/cfg_clock_216_8_1.h" #include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 216MHz */ -#define CLOCK_CORECLOCK (216000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) - -/* Main PLL factors */ -#define CLOCK_PLL_M (4) -#define CLOCK_PLL_N (216) -#define CLOCK_PLL_P (2) -#define CLOCK_PLL_Q (9) -/** @} */ - /** * @name Timer configuration * @{ From ffb6c54d81a4ec3827e9616c48b1ae9e4a1da94a Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Mon, 25 Mar 2019 13:10:04 +0100 Subject: [PATCH 6/6] boards/nucleo-f746zg: Use shared clock settings Use boards/common/stm32/include/f7/cfg_clock_216_8_1.h for core clock settings --- boards/nucleo-f746zg/include/periph_conf.h | 32 +--------------------- 1 file changed, 1 insertion(+), 31 deletions(-) diff --git a/boards/nucleo-f746zg/include/periph_conf.h b/boards/nucleo-f746zg/include/periph_conf.h index 18169713ee..2ab5b09083 100644 --- a/boards/nucleo-f746zg/include/periph_conf.h +++ b/boards/nucleo-f746zg/include/periph_conf.h @@ -22,43 +22,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f7/cfg_clock_216_8_1.h" #include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 216MHz */ -#define CLOCK_CORECLOCK (216000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) - -/* Main PLL factors */ -#define CLOCK_PLL_M (4) -#define CLOCK_PLL_N (216) -#define CLOCK_PLL_P (2) -#define CLOCK_PLL_Q (9) -/** @} */ - /** * @name Timer configuration * @{