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Merge pull request #3334 from kaspar030/remove_old_net

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remove old network stack
This commit is contained in:
Oleg Hahm 2015-08-06 15:10:11 +02:00
commit f90032f94f
347 changed files with 73 additions and 53291 deletions
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107
Makefile.dep
View File

@ -1,53 +1,3 @@
ifneq (,$(filter libcoap,$(USEPKG)))
USEMODULE += pnet
endif
ifneq (,$(filter pnet,$(USEMODULE)))
USEMODULE += posix
USEMODULE += socket_base
USEMODULE += net_help
endif
ifneq (,$(filter transport_layer,$(USEMODULE)))
USEMODULE += tcp
USEMODULE += udp
endif
ifneq (,$(filter udp,$(USEMODULE)))
USEMODULE += socket_base
endif
ifneq (,$(filter tcp,$(USEMODULE)))
USEMODULE += socket_base
endif
ifneq (,$(filter socket_base,$(USEMODULE)))
USEMODULE += sixlowpan
USEMODULE += net_help
USEMODULE += vtimer
endif
ifneq (,$(filter sixlowborder,$(USEMODULE)))
USEMODULE += sixlowpan
endif
ifneq (,$(filter rpl,$(USEMODULE)))
USEMODULE += trickle
USEMODULE += routing
endif
ifneq (,$(filter routing,$(USEMODULE)))
USEMODULE += sixlowpan
endif
ifneq (,$(filter sixlowpan,$(USEMODULE)))
USEMODULE += ieee802154
USEMODULE += net_help
USEMODULE += net_if
USEMODULE += posix
USEMODULE += vtimer
endif
ifneq (,$(filter ng_netif_default,$(USEMODULE)))
USEMODULE += ng_netif
endif
@ -232,14 +182,6 @@ ifneq (,$(filter ng_slip,$(USEMODULE)))
USEMODULE += ng_netbase
endif
ifneq (,$(filter aodvv2,$(USEMODULE)))
USEMODULE += vtimer
USEMODULE += sixlowpan
USEMODULE += oonf_common
USEMODULE += oonf_rfc5444
USEMODULE += fib
endif
ifneq (,$(filter uart0,$(USEMODULE)))
USEMODULE += posix
endif
@ -253,51 +195,10 @@ ifneq (,$(filter cbor,$(USEMODULE)))
USEMODULE += net_help
endif
ifneq (,$(filter cc110x%,$(USEMODULE)))
USEMODULE += protocol_multiplex
USEMODULE += vtimer
endif
ifneq (,$(filter cc110x,$(USEMODULE)))
USEMODULE += transceiver
endif
ifneq (,$(filter cc110x_legacy,$(USEMODULE)))
USEMODULE += transceiver
endif
ifneq (,$(filter cc2420,$(USEMODULE)))
USEMODULE += transceiver
USEMODULE += ieee802154
endif
ifneq (,$(filter at86rf231,$(USEMODULE)))
USEMODULE += netdev_802154
USEMODULE += ieee802154
endif
ifneq (,$(filter l2_ping,$(USEMODULE)))
USEMODULE += vtimer
endif
ifneq (,$(filter vtimer,$(USEMODULE)))
USEMODULE += timex
endif
ifneq (,$(filter net_if,$(USEMODULE)))
USEMODULE += transceiver
USEMODULE += net_help
USEMODULE += hashes
endif
ifneq (,$(filter ccn_lite,$(USEMODULE)))
USEMODULE += crypto
endif
ifneq (,$(filter netdev_802154,$(USEMODULE)))
USEMODULE += netdev_base
endif
ifneq (,$(filter rgbled,$(USEMODULE)))
USEMODULE += color
endif
@ -306,10 +207,6 @@ ifneq (,$(filter libfixmath-unittests,$(USEMODULE)))
USEPKG += libfixmath
endif
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
FEATURES_REQUIRED += transceiver
endif
ifneq (,$(filter nhdp,$(USEMODULE)))
USEMODULE += vtimer
USEMODULE += oonf_common
@ -343,6 +240,10 @@ ifneq (,$(filter newlib,$(USEMODULE)))
USEMODULE += uart_stdio
endif
ifneq (,$(filter ng_netdev_eth,$(USEMODULE)))
USEMODULE += ng_pktbuf
endif
ifneq (,$(filter hih6130,$(USEMODULE)))
USEMODULE += vtimer
endif

2
Makefile.pseudomodules
View File

@ -1,5 +1,3 @@
PSEUDOMODULES += defaulttransceiver
PSEUDOMODULES += transport_layer
PSEUDOMODULES += ng_netif_default
PSEUDOMODULES += ng_ieee802154
PSEUDOMODULES += ng_ipv6_default

9
README.md
View File

@ -40,9 +40,9 @@ Its features comprise
* the native port allows to run RIOT as-is on Linux, BSD, and MacOS. Multiple instances of RIOT running on a single machine can also be interconnected via a simple virtual Ethernet bridge
* Wiselib support (C++ algorithm library, including routing, clustering, timesync, localization, security and more algorithms)
* IPv6
* TCP and UDP
* UDP
* 6LoWPAN
* AODVv2, NHDP, RPL
* NHDP
## GETTING STARTED
* You want to start the RIOT? Just follow our [Getting started documentation](https://github.com/RIOT-OS/RIOT/wiki/Introduction)
@ -58,11 +58,6 @@ There is a shellscript in `RIOT/cpu/native` called `tapsetup.sh` which you can u
To create a bridge and two (or count at your option) tap interfaces:
./tapsetup.sh create [count]
### EXAMPLE APPLICATIONS
In the `examples` directory you can find some example applications. The `default` application demonstrates all available features for the current platform.
For example, you can use it to the test the native networking by running two instances: `make term PORT=tap0` and `make term PORT=tap1`. Now configure two different addresses for both RIOT instances by typing `addr 1` and `addr 2` respectively and send a text message from one "node" to another by typing `txtsnd 2 hello` on the first "node".
## CONTRIBUTE
To contribute something to RIOT, please refer to the [development procedures](https://github.com/RIOT-OS/RIOT/wiki/Development-procedures) and read all notes for best practice.

1
boards/avsextrem/Makefile.features
View File

@ -1,3 +1,2 @@
FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += periph_rtc
FEATURES_MCU_GROUP = arm7

12
boards/avsextrem/Makefile.include
View File

@ -1,12 +1,2 @@
export INCLUDES += -I$(RIOTBOARD)/avsextrem/include
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += cc110x_legacy
USEMODULE += transceiver
endif
ifneq (,$(filter cc110x_legacy_csma,$(USEMODULE)))
INCLUDES += -I$(RIOTBASE)/sys/net/include
endif
export INCLUDES += -I$(RIOTCPU)/$(CPU)/include/ -I$(RIOTBOARD)/$(BOARD)/include/
include $(RIOTBOARD)/msba2-common/Makefile.include

254
boards/avsextrem/drivers/avsextrem-cc1100.c
View File

@ -1,254 +0,0 @@
/*
* avsextrem-cc1100.c - CC100 Transceiver Driver for the AVSEXTREM-BOARD.
* Copyright (C) 2013 Heiko Will <hwill@inf.fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @file
* @ingroup LPC2387
* @brief CC1100 LPC2387 dependend functions
*
* @author Heiko Will <hwill@inf.fu-berlin.de>
* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
*
* @version $Revision: 1781 $
*
* @note $Id: avsextrem-cc1100.c 1781 2013-08-14 13:39:36Z kasmi $
*/
#include <stdio.h>
#include <stddef.h>
// cpu
#include "cpu.h"
// sys
#include "cc110x_legacy.h"
#include "gpioint.h"
#define CC1100_GDO0 (FIO2PIN & BIT6) // read serial I/O (GDO0)
#define CC1100_GDO1 (FIO0PIN & BIT8) // read serial I/O (GDO1)
#define CC1100_GDO2 (FIO0PIN & BIT28) // read serial I/O (GDO2)
#define SPI_TX_EMPTY (SSP1SR & SSPSR_TFE)
#define SPI_BUSY (SSP1SR & SSPSR_BSY)
#define SPI_RX_AVAIL (SSP1SR & SSPSR_RNE)
#define CC1100_GDO1_LOW_RETRY (100) // max. retries for GDO1 to go low
#define CC1100_GDO1_LOW_COUNT (2700) // loop count (timeout ~ 500 us) to wait
// for GDO1 to go low when CS low
//#define DEBUG
#ifdef DEBUG
static unsigned long time_value;
static void set_time(void)
{
time_value = 0;
}
static int test_time(int code)
{
time_value++;
if (time_value > 10000000) {
printf("CC1100 SPI alarm: %d!\n", code);
time_value = 0;
return 1;
}
return 0;
}
#endif
int cc110x_get_gdo0(void)
{
return CC1100_GDO0;
}
int cc110x_get_gdo1(void)
{
return CC1100_GDO1;
}
int cc110x_get_gdo2(void)
{
return CC1100_GDO2;
}
void cc110x_spi_init(void)
{
// configure chip-select
FIO0DIR |= BIT6;
FIO0SET = BIT6;
// Power
PCONP |= PCSSP1; // Enable power for SSP1 (default is on)
// PIN Setup
PINSEL0 |= BIT15; // Set CLK function to SSP1
PINSEL0 &= ~BIT14;
PINSEL0 |= BIT17 ; // Set MISO function to SSP1
PINSEL0 &= ~BIT16;
PINSEL0 |= BIT19; // Set MOSI function to SSP1
PINSEL0 &= ~BIT18;
// Interface Setup
SSP1CR0 = 7;
// Clock Setup
uint32_t pclksel;
uint32_t cpsr;
lpc2387_pclk_scale(F_CPU / 1000, 6000, &pclksel, &cpsr);
PCLKSEL0 &= ~(BIT21 | BIT20); // CCLK to PCLK divider
PCLKSEL0 |= pclksel << 20;
SSP1CPSR = cpsr;
// Enable
SSP1CR1 |= BIT1; // SSP-Enable
int dummy;
// Clear RxFIFO:
while (SPI_RX_AVAIL) { // while RNE (Receive FIFO Not Empty)...
dummy = SSP1DR; // read data
}
/* to suppress unused-but-set-variable */
(void) dummy;
}
uint8_t
cc110x_txrx(uint8_t c)
{
uint8_t result;
SSP1DR = c;
#ifdef DEBUG
set_time();
#endif
while (!SPI_TX_EMPTY) {
#ifdef DEBUG
test_time(0);
#endif
}
#ifdef DEBUG
set_time();
#endif
while (SPI_BUSY) {
#ifdef DEBUG
test_time(1);
#endif
}
#ifdef DEBUG
set_time();
#endif
while (!SPI_RX_AVAIL) {
#ifdef DEBUG
test_time(2);
#endif
}
result = (uint8_t)SSP1DR;
return result;
}
void cc110x_spi_cs(void)
{
FIO0CLR = BIT6;
}
void
cc110x_spi_select(void)
{
volatile int retry_count = 0;
volatile int abort_count;
// Switch to GDO mode input
PINSEL0 &= ~(BIT17 + BIT16); // Set MISO function to GPIO
FIO0DIR &= ~BIT8;
cs_low:
// CS to low
abort_count = 0;
FIO0CLR = BIT6;
// Wait for SO to go low (voltage regulator
// has stabilized and the crystal is running)
loop:
asm volatile("nop");
if (CC1100_GDO1) {
abort_count++;
if (abort_count > CC1100_GDO1_LOW_COUNT) {
retry_count++;
if (retry_count > CC1100_GDO1_LOW_RETRY) {
puts("[CC1100 SPI] fatal error\n");
goto final;
}
FIO0SET = BIT6; // CS to high
goto cs_low; // try again
}
goto loop;
}
final:
// Switch to SPI mode
PINSEL0 |= BIT17; // Set MISO function to SSP1
PINSEL0 &= ~BIT16;
}
void
cc110x_spi_unselect(void)
{
FIO0SET = BIT6;
}
void cc110x_gdo2_disable(void)
{
gpioint_set(0, BIT28, GPIOINT_DISABLE, NULL);
}
void cc110x_gdo2_enable(void)
{
gpioint_set(0, BIT28, GPIOINT_FALLING_EDGE, &cc110x_gdo2_irq);
}
void cc110x_before_send(void)
{
// Disable GDO2 interrupt before sending packet
cc110x_gdo2_disable();
}
void cc110x_after_send(void)
{
// Enable GDO2 interrupt after sending packet
cc110x_gdo2_enable();
}
void cc110x_gdo0_enable(void)
{
gpioint_set(2, BIT6, GPIOINT_RISING_EDGE, &cc110x_gdo0_irq);
}
void cc110x_gdo0_disable(void)
{
gpioint_set(2, BIT6, GPIOINT_DISABLE, NULL);
}
void cc110x_init_interrupts(void)
{
// Enable external interrupt on low edge (for GDO2)
FIO0DIR &= ~BIT28;
cc110x_gdo2_enable();
// Enable external interrupt on low edge (for GDO0)
FIO2DIR &= ~BIT6;
}

2
boards/avsextrem/include/board.h
View File

@ -51,8 +51,6 @@ extern "C" {
void init_clks1(void);
typedef uint8_t radio_packet_length_t;
#ifdef __cplusplus
}
#endif

4
boards/chronos/Makefile.dep
View File

@ -1,4 +0,0 @@
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += cc110x_legacy
USEMODULE += transceiver
endif

1
boards/chronos/Makefile.features
View File

@ -1,3 +1,2 @@
FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += periph_rtc
FEATURES_MCU_GROUP = msp430

112
boards/chronos/drivers/cc430-cc110x.c
View File

@ -1,112 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup chronos
* @{
*/
/**
* @file
* @brief eZ430-chronos radio driver (board dependent part)
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
*
*/
#include <stdint.h>
#include <stdint.h>
#include <cc430f6137.h>
#include "cpu.h"
#include "irq.h"
#include "cc110x_legacy.h"
#define CC1100_GDO0 (RF1AIN & BIT0)
#define CC1100_GDO1 (RF1AIN & BIT1)
#define CC1100_GDO2 (RF1AIN & BIT2)
int cc110x_get_gdo0(void)
{
return CC1100_GDO0;
}
int cc110x_get_gdo1(void)
{
return CC1100_GDO1;
}
int cc110x_get_gdo2(void)
{
return CC1100_GDO2;
}
void cc110x_before_send(void)
{
// Disable GDO2 interrupt before sending packet
cc110x_gdo2_disable();
}
void cc110x_after_send(void)
{
// Enable GDO2 interrupt after sending packet
cc110x_gdo2_enable();
}
void cc110x_gdo0_enable(void)
{
RF1AIFG &= ~BIT0;
RF1AIE |= BIT0;
}
void cc110x_gdo0_disable(void)
{
RF1AIE &= ~BIT0;
RF1AIFG &= ~BIT0;
}
void cc110x_gdo2_disable(void)
{
RF1AIFG &= ~BIT2; // Clear a pending interrupt
RF1AIE &= ~BIT2; // Disable the interrupt
}
void cc110x_gdo2_enable(void)
{
RF1AIFG &= ~BIT2; // Clear a pending interrupt
RF1AIE |= BIT2; // Enable the interrupt
}
void cc110x_init_interrupts(void)
{
uint8_t state = disableIRQ(); /* Disable all interrupts */
cc110x_gdo2_enable();
cc110x_gdo0_disable();
restoreIRQ(state); /* Enable all interrupts */
}
interrupt(CC1101_VECTOR) __attribute__((naked)) cc110x_isr(void)
{
__enter_isr();
/* Check IFG */
if (RF1AIV == RF1AIV_RFIFG2) {
while (RF1AIN & BIT2);
/* discard all further interrupts */
RF1AIV = 0;
cc110x_gdo2_irq();
}
if (RF1AIV == RF1AIV_RFIFG0) {
cc110x_gdo0_irq();
RF1AIE &= ~BIT0;
}
__exit_isr();
}

2
boards/chronos/include/board.h
View File

@ -38,8 +38,6 @@ extern "C" {
#define MSP430_HAS_DCOR 1
#define MSP430_HAS_EXTERNAL_CRYSTAL 1
typedef uint8_t radio_packet_length_t;
#ifdef __cplusplus
}
#endif

6
boards/fox/Makefile.dep
View File

@ -1,6 +0,0 @@
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += at86rf231
ifeq (,$(filter netdev_base,$(USEMODULE)))
USEMODULE += transceiver
endif
endif

1
boards/fox/Makefile.features
View File

@ -1,4 +1,3 @@
FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_spi

5
boards/fox/include/board.h
View File

@ -122,11 +122,6 @@ extern "C" {
#define LED_ORANGE_TOGGLE
/** @} */
/**
* Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

5
boards/frdm-k64f/include/board.h
View File

@ -85,11 +85,6 @@ extern "C"
#define LED_RED_TOGGLE LED_R_TOGGLE
/** @} */
/**
* Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

7
boards/iot-lab_M3/Makefile.dep
View File

@ -1,10 +1,3 @@
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += at86rf231
ifeq (,$(filter netdev_base,$(USEMODULE)))
USEMODULE += transceiver
endif
endif
ifneq (,$(filter ng_netif_default,$(USEMODULE)))
USEMODULE += ng_at86rf231
USEMODULE += ng_nomac

1
boards/iot-lab_M3/Makefile.features
View File

@ -1,4 +1,3 @@
FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_spi

5
boards/iot-lab_M3/include/board.h
View File

@ -151,11 +151,6 @@ extern "C" {
#define LED_ORANGE_TOGGLE (LED_ORANGE_PORT->ODR ^= (1<<LED_ORANGE_PIN))
/** @} */
/**
* Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

5
boards/mbed_lpc1768/include/board.h
View File

@ -88,11 +88,6 @@ extern "C" {
#define LED_RED_TOGGLE LED4_TOGGLE
/** @} */
/**
* @brief define radio packet length
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, include clocks, LEDs and stdio
*/

2
boards/msb-430/include/board.h
View File

@ -61,7 +61,5 @@ extern "C" {
#include "board-conf.h"
typedef uint8_t radio_packet_length_t;
/** @} */
#endif /* MSB_BOARD_H_ */

8
boards/msb-430h/Makefile.dep
View File

@ -1,8 +0,0 @@
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += cc110x_legacy
USEMODULE += transceiver
endif
ifneq (,$(filter cc110x_legacy,$(USEMODULE)))
USEMODULE += cc110x_spi
endif

2
boards/msb-430h/Makefile.features
View File

@ -1,2 +1,2 @@
FEATURES_PROVIDED += transceiver config
FEATURES_PROVIDED += config
FEATURES_MCU_GROUP = msp430

347
boards/msb-430h/driver_cc110x.c
View File

@ -1,347 +0,0 @@
/*
* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "irq.h"
#include "cc110x_legacy.h"
#define CC1100_GDO0 (P2IN & 0x02) // read serial I/O (GDO0)
#define CC1100_GDO1 (P3IN & 0x04) // read serial I/O (GDO1)
#define CC1100_GDO2 (P2IN & 0x01) // read serial I/O (GDO2)
#define CC1100_CS_LOW (P3OUT &= ~0x01)
#define CC1100_CS_HIGH (P3OUT |= 0x01)
#define CC1100_GDO1_LOW_COUNT (2700) // loop count (timeout ~ 500 us) to wait
#define CC1100_GDO1_LOW_RETRY (100) // max. retries for GDO1 to go low
volatile int abort_count;
volatile int retry_count = 0;
void cc110x_gdo0_enable(void)
{
P2IFG &= ~0x02; /* Clear IFG for GDO0 */
P2IE |= 0x02; /* Enable interrupt for GDO0 */
}
void cc110x_gdo0_disable(void)
{
P2IE &= ~0x02; /* Disable interrupt for GDO0 */
P2IFG &= ~0x02; /* Clear IFG for GDO0 */
}
void cc110x_gdo2_enable(void)
{
P2IFG &= ~0x01; /* Clear IFG for GDO2 */
P2IE |= 0x01; /* Enable interrupt for GDO2 */
}
void cc110x_gdo2_disable(void)
{
P2IE &= ~0x01; /* Disable interrupt for GDO2 */
P2IFG &= ~0x01; /* Clear IFG for GDO2 */
}
void cc110x_before_send(void)
{
// Disable GDO2 interrupt before sending packet
cc110x_gdo2_disable();
}
void cc110x_after_send(void)
{
// Enable GDO2 interrupt after sending packet
cc110x_gdo2_enable();
}
int cc110x_get_gdo0(void)
{
return CC1100_GDO0;
}
int cc110x_get_gdo1(void)
{
return CC1100_GDO1;
}
int cc110x_get_gdo2(void)
{
return CC1100_GDO2;
}
void cc110x_spi_cs(void)
{
CC1100_CS_LOW;
}
uint8_t cc110x_txrx(uint8_t data)
{
/* Ensure TX Buf is empty */
long c = 0;
IFG1 &= ~UTXIFG0;
IFG1 &= ~URXIFG0;
TXBUF0 = data;
while (!(IFG1 & UTXIFG0)) {
if (c++ == 1000000) {
puts("cc110x_txrx alarm()");
}
}
/* Wait for Byte received */
c = 0;
while (!(IFG1 & URXIFG0)) {
if (c++ == 1000000) {
puts("cc110x_txrx alarm()");
}
}
return RXBUF0;
}
void cc110x_spi_select(void)
{
// Switch to GDO mode
P3SEL &= ~0x04;
P3DIR &= ~0x04;
cs_low:
// CS to low
abort_count = 0;
CC1100_CS_LOW;
// Wait for SO to go low (voltage regulator
// has stabilized and the crystal is running)
loop:
// asm volatile ("nop");
if (CC1100_GDO1) {
abort_count++;
if (abort_count > CC1100_GDO1_LOW_COUNT) {
retry_count++;
if (retry_count > CC1100_GDO1_LOW_RETRY) {
puts("[CC1100 SPI] fatal error\n");
goto final;
}
CC1100_CS_HIGH;
goto cs_low; // try again
}
goto loop;
}
final:
/* Switch to SPI mode */
P3SEL |= 0x04;
}
void cc110x_spi_unselect(void)
{
CC1100_CS_HIGH;
}
void cc110x_init_interrupts(void)
{
unsigned int state = disableIRQ(); /* Disable all interrupts */
P2SEL = 0x00; /* must be <> 1 to use interrupts */
P2IES |= 0x01; /* Enables external interrupt on low edge (for GDO2) */
P2IE |= 0x01; /* Enable interrupt */
P2IFG &= ~0x01; /* Clears the interrupt flag */
P2IE &= ~0x02; /* Disable interrupt for GDO0 */
P2IFG &= ~0x02; /* Clear IFG for GDO0 */
restoreIRQ(state); /* Enable all interrupts */
}
void cc110x_spi_init(void)
{
// Switch off async UART
while (!(UTCTL0 & TXEPT)); // Wait for empty UxTXBUF register
IE1 &= ~(URXIE0 + UTXIE0); // Disable USART0 receive&transmit interrupt
ME1 &= ~(UTXE0 + URXE0);
P3SEL |= 0x0E; // Set pin as SPI
// Keep peripheral in reset state
UCTL0 = SWRST;
// 8-bit SPI Master 3-pin mode, with SMCLK as clock source
// CKPL works also, but not CKPH+CKPL or none of them!!
UCTL0 |= CHAR + SYNC + MM;
UTCTL0 = CKPH + SSEL1 + SSEL0 + STC;
// Ignore clockrate argument for now, just use clock source/2
// SMCLK = 7,3728 MHz
UBR00 = 0x02; // Ensure baud rate >= 2
UBR10 = 0x00;
UMCTL0 = 0x00; // No modulation
URCTL0 = 0x00; // Reset Receive Control Register
// Enable SPI mode
ME1 |= USPIE0;
// Release for operation
UCTL0 &= ~SWRST;
}
// #include <msp430x16x.h>
// #include <signal.h>
// #include "type.h"
// #include "cc110x_defines.h"
// #include "driver_cc110x.h"
// #include "driver_system.h"
// #include "spi0.h"
//
// static callback_t _paket_cb;
// static callback_t _cs_cb;
//
// //-------------------------------------------------------------------------------------------------------
// // Public CC1100 communication functions (SPI)
// //-------------------------------------------------------------------------------------------------------
//
// //-------------------------------------------------------------------------------------------------------
// // void spiInitTrx(void)
// //
// // DESCRIPTION:
// // This function puts the cc110x into spi mode. You have to call this bevore every spi transaction.
// //
// //-------------------------------------------------------------------------------------------------------
//
//
// void drivercc110x_spiwriteburstreg(uint8_t addr, unsigned char *buffer, uint8_t count)
// {
// uint8_t i;
// long c;
// drivercc110x_spiinittrx();
// drivercc110x_trxspi(addr | CC1100_WRITE_BURST);
// for (i = 0; i < count; i++)
// {
// c = 0;
// IFG1 &= ~UTXIFG0;
// IFG1 &= ~URXIFG0;
// TXBUF0 = buffer[i];
// /* Wait for TX to finish */
// while(!(IFG1 & UTXIFG0))
// {
// if (c++ == 1000000)
// alarm();
// }
// }
// /* Wait for Byte received */
// c = 0;
// while(!(IFG1 & URXIFG0))
// {
// if (c++ == 1000000)
// alarm();
// }
// CC1100_CS_HIGH;
// }
//
// void drivercc110x_spireadburstreg(uint8_t addr, char *buffer, uint8_t count)
// {
// uint8_t i;
// drivercc110x_spiinittrx();
// drivercc110x_trxspi(addr | CC1100_READ_BURST);
// for (i = 0; i < count; i++)
// {
// long c = 0;
// IFG1 &= ~UTXIFG0;
// IFG1 &= ~URXIFG0;
// TXBUF0 = NOBYTE;
// while(!(IFG1 & UTXIFG0))
// {
// if (c++ == 1000000)
// alarm();
// }
// /* Wait for Byte received */
// c = 0;
// while(!(IFG1 & URXIFG0))
// {
// if (c++ == 1000000)
// alarm();
// }
// buffer[i] = RXBUF0;
// }
// CC1100_CS_HIGH;
// }
//
// void drivercc110x_load(callback_t cs_cb,callback_t paket_cb)
// {
// _paket_cb = paket_cb;
// _cs_cb = cs_cb;
// spi0_init(0);
// }
//
// void drivercc110x_aftersend(void)
// {
// CLEAR(P2IFG, 0x01);
// SET(P2IE, 0x01); /* Enable interrupts on port 2 pin 0 */
// CLEAR(P4OUT, 0x08); /* Turn off Sending Led*/
// }
//
// void drivercc110x_initinterrupts(void)
// {
// _DINT(); /* Disable all interrupts */
// P2SEL = 0x00; /* must be <> 1 to use interrupts */
// SET(P2IES, 0x01); /* Enables external interrupt on low edge (for GDO2) */
// SET(P2IE, 0x01); /* Enable interrupt */
// CLEAR(P2IFG, 0x01); /* Clears the interrupt flag */
// CLEAR(P2IE, 0x02); /* Disable interrupt for GDO0 */
// CLEAR(P2IFG, 0x02); /* Clear IFG for GDO0 */
// _EINT(); /* Enable all interrupts */
// }
//
// void drivercc110x_beforesend(void)
// {
// /* Turn on Led while sending paket for debug reasons */
// SET(P4OUT, 0x08);
// /* Disable interrupts on port 2 pin 0 */
// CLEAR(P2IE, 0x01);
// }
//
//
// /*
// * Private functions
// */
//
//
/*
* CC1100 receive interrupt
*/
interrupt(PORT2_VECTOR) __attribute__((naked)) cc110x_isr(void)
{
__enter_isr();
// if (system_state.POWERDOWN) SPI_INIT; /* Initialize SPI after wakeup */
/* Check IFG */
if ((P2IFG & 0x01) != 0) {
P2IFG &= ~0x01;
cc110x_gdo2_irq();
}
else if ((P2IFG & 0x02) != 0) {
cc110x_gdo0_irq();
P2IE &= ~0x02; // Disable interrupt for GDO0
P2IFG &= ~0x02; // Clear IFG for GDO0
}
else {
puts("cc110x_isr(): unexpected IFG!");
/* Should not occur - only Port 2 Pin 0 interrupts are enabled */
// CLEAR(P2IFG, 0xFF); /* Clear all flags */
}
// if (system_state.POWERDOWN != 0) END_LPM3;
__exit_isr();
}

2
boards/msb-430h/include/board.h
View File

@ -54,7 +54,5 @@ extern "C" {
#include "board-conf.h"
typedef uint8_t radio_packet_length_t;
/** @} */
#endif /* MSB_BOARD_H_ */

9
boards/msba2-common/Makefile.dep
View File

@ -1,12 +1,3 @@
ifneq (,$(filter cc110x_legacy_csma,$(USEMODULE)))
USEMODULE += gpioint
endif
ifneq (,$(filter cc110x_legacy,$(USEMODULE)))
USEMODULE += cc110x_spi
USEMODULE += gpioint
endif
ifneq (,$(filter ltc4150,$(USEMODULE)))
USEMODULE += gpioint
endif

1
boards/msba2/Makefile
View File

@ -1,5 +1,4 @@
MODULE =$(BOARD)_base
INCLUDES += -I$(RIOTBASE)/drivers/cc110x_legacy_csma
DIRS = $(RIOTBOARD)/msba2-common

1
boards/msba2/Makefile.features
View File

@ -1,4 +1,3 @@
FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += cpp

5
boards/msba2/Makefile.include
View File

@ -1,8 +1,3 @@
export INCLUDES += -I$(RIOTBOARD)/msba2/include
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += cc110x_legacy
USEMODULE += transceiver
endif
include $(RIOTBOARD)/msba2-common/Makefile.include

2
boards/msba2/include/board.h
View File

@ -41,8 +41,6 @@ extern "C" {
void init_clks1(void);
typedef uint8_t radio_packet_length_t;
#ifdef __cplusplus
}
#endif

249
boards/msba2/msba2-cc110x.c
View File

@ -1,249 +0,0 @@
/*
* Copyright (C) 2008, Freie Universitaet Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @file
* @ingroup LPC2387
* @brief CC1100 LPC2387 dependend functions
*
* @author Heiko Will <hwill@inf.fu-berlin.de>
* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
* @version $Revision: 1781 $
*
* @note $Id: msba2-cc110x.c 1781 2010-01-26 13:39:36Z hillebra $
*/
#include <stdio.h>
#include <stddef.h>
/* core */
#include "irq.h"
/* cpu */
#include "cpu.h"
/* drivers */
#include "cc110x_legacy.h"
#include "gpioint.h"
#define CC1100_GDO0 (FIO0PIN & BIT27) // read serial I/O (GDO0)
#define CC1100_GDO1 (FIO1PIN & BIT23) // read serial I/O (GDO1)
#define CC1100_GDO2 (FIO0PIN & BIT28) // read serial I/O (GDO2)
#define SPI_TX_EMPTY (SSP0SR & SSPSR_TFE)
#define SPI_BUSY (SSP0SR & SSPSR_BSY)
#define SPI_RX_AVAIL (SSP0SR & SSPSR_RNE)
#define CC1100_GDO1_LOW_RETRY (100) // max. retries for GDO1 to go low
#define CC1100_GDO1_LOW_COUNT (2700) // loop count (timeout ~ 500 us) to wait
// for GDO1 to go low when CS low
//#define DEBUG
#ifdef DEBUG
static unsigned long time_value;
static void set_time(void)
{
time_value = 0;
}
static int test_time(int code)
{
time_value++;
if (time_value > 10000000) {
printf("CC1100 SPI alarm: %d!\n", code);
time_value = 0;
return 1;
}
return 0;
}
#endif
int cc110x_get_gdo0(void)
{
return CC1100_GDO0;
}
int cc110x_get_gdo1(void)
{
return CC1100_GDO1;
}
int cc110x_get_gdo2(void)
{
return CC1100_GDO2;
}
void cc110x_spi_init(void)
{
// configure chip-select
FIO1DIR |= BIT21;
FIO1SET = BIT21;
// Power
PCONP |= PCSSP0; // Enable power for SSP0 (default is on)
// PIN Setup
PINSEL3 |= BIT8 + BIT9; // Set CLK function to SPI
PINSEL3 |= BIT14 + BIT15; // Set MISO function to SPI
PINSEL3 |= BIT16 + BIT17; // Set MOSI function to SPI
// Interface Setup
SSP0CR0 = 7;
// Clock Setup
uint32_t pclksel;
uint32_t cpsr;
lpc2387_pclk_scale(F_CPU / 1000, 6000, &pclksel, &cpsr);
PCLKSEL1 &= ~(BIT10 | BIT11); // CCLK to PCLK divider
PCLKSEL1 |= pclksel << 10;
SSP0CPSR = cpsr;
// Enable
SSP0CR1 |= BIT1; // SSP-Enable
int dummy;
// Clear RxFIFO:
while (SPI_RX_AVAIL) { // while RNE (Receive FIFO Not Empty)...
dummy = SSP0DR; // read data
}
/* to suppress unused-but-set-variable */
(void) dummy;
}
uint8_t cc110x_txrx(uint8_t c)
{
uint8_t result;
SSP0DR = c;
#ifdef DEBUG
set_time();
#endif
while (!SPI_TX_EMPTY) {
#ifdef DEBUG
test_time(0);
#endif
}
#ifdef DEBUG
set_time();
#endif
while (SPI_BUSY) {
#ifdef DEBUG
test_time(1);
#endif
}
#ifdef DEBUG
set_time();
#endif
while (!SPI_RX_AVAIL) {
#ifdef DEBUG
test_time(2);
#endif
}
result = (uint8_t)SSP0DR;
return result;
}
void cc110x_spi_cs(void)
{
FIO1CLR = BIT21;
}
void
cc110x_spi_select(void)
{
volatile int retry_count = 0;
volatile int abort_count;
// Switch to GDO mode input
PINSEL3 &= ~(BIT14 + BIT15);// Set MISO function to GPIO
FIO1DIR &= ~BIT23;
cs_low:
// CS to low
abort_count = 0;
FIO1CLR = BIT21;
// Wait for SO to go low (voltage regulator
// has stabilized and the crystal is running)
loop:
asm volatile("nop");
if (CC1100_GDO1) {
abort_count++;
if (abort_count > CC1100_GDO1_LOW_COUNT) {
retry_count++;
if (retry_count > CC1100_GDO1_LOW_RETRY) {
puts("[CC1100 SPI] fatal error\n");
goto final;
}
FIO1SET = BIT21; // CS to high
goto cs_low; // try again
}
goto loop;
}
final:
// Switch to SPI mode
PINSEL3 |= (BIT14 + BIT15); // Set MISO function to SPI
}
void
cc110x_spi_unselect(void)
{
FIO1SET = BIT21;
}
void cc110x_before_send(void)
{
// Disable GDO2 interrupt before sending packet
cc110x_gdo2_disable();
}
void cc110x_after_send(void)
{
// Enable GDO2 interrupt after sending packet
cc110x_gdo2_enable();
}
void cc110x_gdo0_enable(void)
{
gpioint_set(0, BIT27, GPIOINT_RISING_EDGE, &cc110x_gdo0_irq);
}
void cc110x_gdo0_disable(void)
{
gpioint_set(0, BIT27, GPIOINT_DISABLE, NULL);
}
void cc110x_gdo2_disable(void)
{
gpioint_set(0, BIT28, GPIOINT_DISABLE, NULL);
}
void cc110x_gdo2_enable(void)
{
gpioint_set(0, BIT28, GPIOINT_FALLING_EDGE, &cc110x_gdo2_irq);
}
void cc110x_init_interrupts(void)
{
// Enable external interrupt on low edge (for GDO2)
FIO0DIR &= ~BIT28;
cc110x_gdo2_enable();
// Enable external interrupt on low edge (for GDO0)
FIO0DIR &= ~BIT27;
}

1
boards/msbiot/Makefile
View File

@ -1,5 +1,4 @@
# tell the Makefile.base which module to build
MODULE = $(BOARD)_base
INCLUDES += -I$(RIOTBASE)/drivers/cc110x
include $(RIOTBASE)/Makefile.base

1
boards/msbiot/Makefile.features
View File

@ -7,5 +7,4 @@ FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_dac
FEATURES_PROVIDED += transceiver
FEATURES_MCU_GROUP = cortex_m4

7
boards/msbiot/Makefile.include
View File

@ -2,13 +2,6 @@
export CPU = stm32f4
export CPU_MODEL = stm32f415rg
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += cc110x
ifeq (,$(filter netdev_base,$(USEMODULE)))
USEMODULE += transceiver
endif
endif
#define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1)

2
boards/msbiot/include/board.h
View File

@ -49,8 +49,6 @@ extern "C" {
#define CC110X_GDO0 GPIO(PORT_C, 4)
#define CC110X_GDO1 GPIO(PORT_A, 6)
#define CC110X_GDO2 GPIO(PORT_C, 5)
typedef uint8_t radio_packet_length_t;
/** @} */
/**

7
boards/mulle/Makefile.dep
View File

@ -1,10 +1,3 @@
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += at86rf231
ifeq (,$(filter netdev_base,$(USEMODULE)))
USEMODULE += transceiver
endif
endif
ifneq (,$(filter ng_netif_default,$(USEMODULE)))
USEMODULE += ng_at86rf212b
USEMODULE += ng_nomac

1
boards/mulle/Makefile.features
View File

@ -9,5 +9,4 @@ FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += transceiver
FEATURES_MCU_GROUP = cortex_m4

5
boards/mulle/include/board.h
View File

@ -94,11 +94,6 @@ extern "C" {
*/
void board_init(void);
/**
* Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
#ifdef __cplusplus
}
#endif

7
boards/native/Makefile.dep
View File

@ -1,10 +1,3 @@
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += nativenet
ifeq (,$(filter netdev_base,$(USEMODULE)))
USEMODULE += transceiver
endif
endif
ifneq (,$(filter ng_netif_default,$(USEMODULE)))
USEMODULE += ng_nativenet
USEMODULE += ng_netdev_eth

1
boards/native/Makefile.features
View File

@ -1,5 +1,4 @@
FEATURES_PROVIDED += ethernet
FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += config
FEATURES_PROVIDED += cpp

8
boards/native/board_config.c
View File

@ -22,10 +22,6 @@
#include "config.h"
#ifdef MODULE_NATIVENET
#include "nativenet.h"
#include "nativenet_internal.h"
#endif
#include "native_internal.h"
#define ENABLE_DEBUG (0)
@ -40,10 +36,6 @@ void config_load(void)
sysconfig.id = _native_id;
#ifdef MODULE_NATIVENET
_nativenet_default_dev_more._radio_addr = _native_id;
#endif
return;
}

2
boards/native/include/board.h
View File

@ -45,8 +45,6 @@ void _native_LED_RED_ON(void);
void _native_LED_RED_TOGGLE(void);
#define LED_RED_TOGGLE (_native_LED_RED_TOGGLE())
typedef uint16_t radio_packet_length_t;
#ifdef __cplusplus
}
#endif

5
boards/nucleo-f091/include/board.h
View File

@ -74,11 +74,6 @@ extern "C" {
#define LED_ORANGE_TOGGLE
/** @} */
/**
* @name Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

5
boards/nucleo-f303/include/board.h
View File

@ -76,11 +76,6 @@ extern "C" {
#define LED_ORANGE_TOGGLE
/** @} */
/**
* @name Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

5
boards/nucleo-f334/include/board.h
View File

@ -74,11 +74,6 @@ extern "C" {
#define LED_ORANGE_TOGGLE
/** @} */
/**
* @name Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

5
boards/nucleo-l1/include/board.h
View File

@ -74,11 +74,6 @@ extern "C" {
#define LED_ORANGE_TOGGLE
/** @} */
/**
* @name Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

5
boards/pba-d-01-kw2x/include/board.h
View File

@ -85,11 +85,6 @@ extern "C"
#define LED_RED_TOGGLE LED_R_TOGGLE
/** @} */
/**
* Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
@name KW2XRF configuration
@{

1
boards/pttu/Makefile
View File

@ -1,5 +1,4 @@
MODULE =$(BOARD)_base
INCLUDES += -I$(RIOTBASE)/drivers/cc110x_legacy_csma
DIRS = $(RIOTBOARD)/msba2-common

2
boards/pttu/Makefile.features
View File

@ -1,4 +1,2 @@
# Enable this after fixing https://github.com/RIOT-OS/RIOT/issues/659
#FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += periph_rtc
FEATURES_MCU_GROUP = arm7

6
boards/pttu/Makefile.include
View File

@ -1,9 +1,3 @@
export INCLUDES += -I$(RIOTBOARD)/pttu/include
# Enable this after fixing https://github.com/RIOT-OS/RIOT/issues/659
#ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
# USEMODULE += cc110x_legacy_csma
# USEMODULE += transceiver
#endif
include $(RIOTBOARD)/msba2-common/Makefile.include

5
boards/pttu/include/board.h
View File

@ -50,11 +50,6 @@ void init_clks2(void);
*/
void bl_init_clks(void);
/**
* @brief Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
#ifdef __cplusplus
}
#endif

1
boards/redbee-econotag/Makefile.features
View File

@ -1,2 +1 @@
FEATURES_PROVIDED += transceiver
FEATURES_MCU_GROUP = arm7

6
boards/redbee-econotag/Makefile.include
View File

@ -31,11 +31,5 @@ export TERMFLAGS += -p "$(PORT)"
export INCLUDES += -I$(RIOTCPU)/$(CPU)/include/ -I$(RIOTBOARD)/$(BOARD)/include/
export INCLUDES += -I$(RIOTCPU)/$(CPU)/maca/include
export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/drivers/include
export INCLUDES += -I$(RIOTBASE)/sys/net/include
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += mc1322x
USEMODULE += transceiver
endif
export UNDEF += $(BINDIR)cpu/startup.o

2
boards/redbee-econotag/include/board.h
View File

@ -33,8 +33,6 @@ extern "C" {
#define IBIAS 0x1f
#define FTUNE 0x7
typedef uint8_t radio_packet_length_t;
#ifdef __cplusplus
}
#endif

7
boards/samr21-xpro/Makefile.dep
View File

@ -1,10 +1,3 @@
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += at86rf231
ifeq (,$(filter netdev_base,$(USEMODULE)))
USEMODULE += transceiver
endif
endif
ifneq (,$(filter ng_netif_default,$(USEMODULE)))
USEMODULE += ng_at86rf233
USEMODULE += ng_nomac

2
boards/samr21-xpro/Makefile.features
View File

@ -1,5 +1,3 @@
FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += periph_gpio

5
boards/samr21-xpro/include/board.h
View File

@ -102,11 +102,6 @@ extern "C" {
#define LED_RED_TOGGLE LED_TOGGLE
/** @} */
/**
* @brief Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

3
boards/spark-core/Makefile.include
View File

@ -16,8 +16,7 @@ export OFLAGS = -O binary
export FFLAGS = -d 1d50:607f -a 0 -s 0x08005000:leave -D "$(HEXFILE)"
export TERMFLAGS = -p $(PORT)
# export board specific includes to the global includes-listing
export INCLUDES += -I$(RIOTBASE)/drivers/at86rf231/include -I$(RIOTBASE)/sys/net/include
export INCLUDES += -I$(RIOTCPU)/$(CPU)/include/ -I$(RIOTBOARD)/$(BOARD)/include/
# setup serial terminal
include $(RIOTBOARD)/Makefile.include.serial

5
boards/spark-core/include/board.h
View File

@ -106,11 +106,6 @@
#define EXTFLASH GPIO(PORT_B,9)
/** @} */
/**
* Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

1
boards/telosb/Makefile.features
View File

@ -1,2 +1 @@
FEATURES_PROVIDED += transceiver
FEATURES_MCU_GROUP = msp430

8
boards/telosb/Makefile.include
View File

@ -22,12 +22,8 @@ endif
export FFLAGS = --telosb -c $(PORT) -r -e -I -p $(HEXFILE)
export TERMFLAGS += -p "$(PORT)"
export INCLUDES += -I$(RIOTCPU)/msp430-common/include -I$(RIOTBOARD)/$(BOARD)/include -I$(RIOTBASE)/drivers/cc2420/include -I$(RIOTBASE)/sys/net/include
export INCLUDES += -I$(RIOTCPU)/$(CPU)/include/ -I$(RIOTBOARD)/$(BOARD)/include/
export INCLUDES += -I$(RIOTCPU)/msp430-common/include
export OFLAGS = -O ihex
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += cc2420
USEMODULE += transceiver
endif
export UNDEF += $(BINDIR)msp430_common/startup.o

245
boards/telosb/driver_cc2420.c
View File

@ -1,245 +0,0 @@
/*
* driver_cc2420.c - Implementation of the board dependent cc2420 functions.
* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "irq.h"
#include "hwtimer.h"
#include "panic.h"
#include "cc2420.h"
#include "cc2420_arch.h"
#include "cc2420_spi.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#define CC2420_RESETn_PIN 0x40
#define CC2420_VREGEN_PIN 0x20
#define CC2420_FIFOP_PIN 0x01
#define CC2420_GIO0_PIN 0x08
#define CC2420_GIO1_PIN 0x10
#define CC2420_CCA_PIN 0x40
#define CC2420_SFD_PIN 0x02
#define CC2420_FIFOP (P1IN & CC2420_FIFOP_PIN) /* FIFOP <-> packet interrupt (P1.0) */
#define CC2420_GIO0 (P1IN & CC2420_GIO0_PIN) /* FIFO <-> GIO0 - RX data available (P1.3) */
#define CC2420_GIO1 (P1IN & CC2420_GIO1_PIN) /* CCA <-> GIO1 - clear channel (P1.4) */
#define CC2420_SFD (P4IN & CC2420_SFD_PIN) /* SFD <-> TBL - start frame delimiter (P4.1) */
#define CC2420_CS_LOW (P4OUT &= ~0x04) /* P4.2 */
#define CC2420_CS_HIGH (P4OUT |= 0x04)
volatile int abort_count;
volatile int retry_count = 0;
void cc2420_reset(void)
{
P4OUT |= CC2420_VREGEN_PIN;
P4OUT &= ~CC2420_RESETn_PIN;
hwtimer_wait(500);
P4OUT |= CC2420_RESETn_PIN;
}
void cc2420_gio0_enable(void)
{
P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
P1IE |= CC2420_GIO0_PIN; /* Enable interrupt for GIO0 */
}
void cc2420_gio0_disable(void)
{
P1IE &= ~CC2420_GIO0_PIN; /* Disable interrupt for GIO0 */
P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
}
void cc2420_gio1_enable(void)
{
P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
P1IE |= CC2420_GIO1_PIN; /* Enable interrupt for GIO1 */
}
void cc2420_gio1_disable(void)
{
P1IE &= ~CC2420_GIO1_PIN; /* Disable interrupt for GIO1 */
P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
}
void cc2420_before_send(void)
{
/* Disable SFD interrupt before sending packet */
/* However this is not used atm */
}
void cc2420_after_send(void)
{
/* Enable SFD interrupt after sending packet */
/* However this is not used atm */
}
int cc2420_get_gio0(void)
{
return CC2420_GIO0;
}
int cc2420_get_gio1(void)
{
return CC2420_GIO1;
}
uint8_t cc2420_get_fifop(void)
{
return CC2420_FIFOP;
}
uint8_t cc2420_get_sfd(void)
{
return CC2420_SFD;
}
#define MAX_RSSI_WAIT 1000
uint8_t cc2420_get_cca(void)
{
uint8_t status;
long count = 0;
do {
unsigned int sr = disableIRQ();
cc2420_spi_select();
status = cc2420_txrx(NOBYTE);
cc2420_spi_unselect();
restoreIRQ(sr);
count++;
if (count >= MAX_RSSI_WAIT) {
core_panic(0x2420, "cc2420_get_cca(): RSSI never valid!");
}
} while (!(status & CC2420_STATUS_RSSI_VALID));
return CC2420_GIO1;
}
void cc2420_spi_cs(void)
{
CC2420_CS_LOW;
}
uint8_t cc2420_txrx(uint8_t data)
{
/* Ensure TX Buf is empty */
long c = 0;
IFG1 &= ~UTXIFG0;
IFG1 &= ~URXIFG0;
U0TXBUF = data;
while(!(IFG1 & UTXIFG0)) {
if (c++ == 1000000) {
core_panic(0x2420, "cc2420_txrx() alarm");
}
}
/* Wait for Byte received */
c = 0;
while(!(IFG1 & URXIFG0)) {
if (c++ == 1000000) {
core_panic(0x2420, "cc2420_txrx() alarm");
}
}
return U0RXBUF;
}
void cc2420_spi_select(void)
{
CC2420_CS_LOW;
}
void cc2420_spi_unselect(void) {
CC2420_CS_HIGH;
}
void cc2420_init_interrupts(void)
{
unsigned int state = disableIRQ(); /* Disable all interrupts */
P1SEL &= ~CC2420_FIFOP_PIN; /* must be <> 1 to use interrupts */
P1SEL &= ~CC2420_GIO0_PIN; /* must be <> 1 to use interrupts */
/* FIFO <-> GIO0 interrupt */
P1IES |= CC2420_GIO0_PIN; /* Enables external interrupt on falling edge (for GIO0/FIFO) */
P1IE |= CC2420_GIO0_PIN; /* Enable interrupt */
P1IFG &= ~CC2420_GIO0_PIN; /* Clears the interrupt flag */
/* FIFOP <-> Packet interrupt */
P1IE |= CC2420_FIFOP_PIN; /* Enable interrupt for FIFOP */
P1IFG &= ~CC2420_FIFOP_PIN; /* Clear IFG for FIFOP */
restoreIRQ(state); /* Enable all interrupts */
}
void cc2420_spi_init(void)
{
/* Switch off async UART */
while(!(U0TCTL & TXEPT)); /* Wait for empty UxTXBUF register */
IE1 &= ~(URXIE0 + UTXIE0); /* Disable USART0 receive&transmit interrupt */
ME1 &= ~(UTXE0 + URXE0);
/* configure SPI-related pins */
P3SEL |= 0x0E; /* P3.1 - SIMO mode, P3.2 - SOMI mode, P3.3 - SCL mode */
P3DIR |= 0x0A; /* P3.1 and P3.3 as output */
P3DIR &= ~(0x04); /* P3.2 as input for SOMI */
P4OUT |= 0x04; /* P4.2 radio CS, hold high */
P4DIR |= 0x04; /* P4.2 radio CS, output */
/* Keep peripheral in reset state */
U0CTL = SWRST;
/* 8-bit SPI Master 3-pin mode, with SMCLK as clock source */
/* CKPL works also, but not CKPH+CKPL or none of them!! */
U0CTL |= CHAR + SYNC + MM;
U0TCTL = CKPH + SSEL1 + SSEL0 + STC + TXEPT;;
/* Ignore clockrate argument for now, just use clock source/2 */
/* SMCLK = 8 MHz */
U0BR0 = 0x02; /* Ensure baud rate >= 2 */
U0BR1 = 0x00;
U0MCTL = 0x00; /* No modulation */
U0RCTL = 0x00; /* Reset Receive Control Register */
/* Enable SPI mode */
ME1 |= USPIE0;
/* Release for operation */
U0CTL &= ~SWRST;
}
/*
* CC2420 receive interrupt
*/
interrupt (PORT1_VECTOR) __attribute__ ((naked)) cc2420_isr(void)
{
__enter_isr();
/* Check IFG */
if ((P1IFG & CC2420_FIFOP_PIN) != 0) {
P1IFG &= ~CC2420_FIFOP_PIN;
cc2420_rx_irq();
DEBUG("rx interrupt");
}
/* GIO0 is falling => check if FIFOP is high, indicating an RXFIFO overflow */
else if ((P1IFG & CC2420_GIO0_PIN) != 0) {
P1IFG &= ~CC2420_GIO0_PIN;
if (cc2420_get_fifop()) {
cc2420_rxoverflow_irq();
DEBUG("[CC2420] rxfifo overflow");
}
}
else {
puts("cc2420_isr(): unexpected IFG!");
/* Should not occur - only GDO1 and GIO1 interrupts are enabled */
}
__exit_isr();
}

2
boards/telosb/include/board.h
View File

@ -67,7 +67,5 @@ extern "C" {
#include <stdint.h>
typedef uint8_t radio_packet_length_t;
/** @} */
#endif /* TELOSB_BOARD_H_ */

9
boards/wsn430-v1_3b/Makefile.dep
View File

@ -1,10 +1 @@
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += cc110x_legacy
USEMODULE += transceiver
endif
ifneq (,$(filter cc110x_legacy,$(USEMODULE)))
USEMODULE += cc110x_spi
endif
USEMODULE += msp430_common

1
boards/wsn430-v1_3b/Makefile.features
View File

@ -1,3 +1,2 @@
FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += config
FEATURES_MCU_GROUP = msp430

208
boards/wsn430-v1_3b/driver_cc110x.c
View File

@ -1,208 +0,0 @@
/*
* driver_cc110x.c - Implementation of the board dependent cc1100 functions.
* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will
* Copyright (C) 2013 Milan Babel <babel@inf.fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "irq.h"
#include "cc110x_legacy.h"
#define CC1100_GDO0 (P1IN & 0x08) // read serial I/O (GDO0)
#define CC1100_GDO1 (P5IN & 0x04) // read serial I/O (GDO1)
#define CC1100_GDO2 (P1IN & 0x10) // read serial I/O (GDO2)
#define CC1100_CS_LOW (P4OUT &= ~0x04)
#define CC1100_CS_HIGH (P4OUT |= 0x04)
#define CC1100_GDO1_LOW_COUNT (2700) // loop count (timeout ~ 500 us) to wait
#define CC1100_GDO1_LOW_RETRY (100) // max. retries for GDO1 to go low
volatile int abort_count;
volatile int retry_count = 0;
void cc110x_gdo0_enable(void)
{
P1IFG &= ~0x08; /* Clear IFG for GDO0 */
P1IE |= 0x08; /* Enable interrupt for GDO0 */
}
void cc110x_gdo0_disable(void)
{
P1IE &= ~0x08; /* Disable interrupt for GDO0 */
P1IFG &= ~0x08; /* Clear IFG for GDO0 */
}
void cc110x_gdo2_enable(void)
{
P1IFG &= ~0x10; /* Clear IFG for GDO2 */
P1IE |= 0x10; /* Enable interrupt for GDO2 */
}
void cc110x_gdo2_disable(void)
{
P1IE &= ~0x10; /* Disable interrupt for GDO2 */
P1IFG &= ~0x10; /* Clear IFG for GDO2 */
}
void cc110x_before_send(void)
{
// Disable GDO2 interrupt before sending packet
cc110x_gdo2_disable();
}
void cc110x_after_send(void)
{
// Enable GDO2 interrupt after sending packet
cc110x_gdo2_enable();
}
int cc110x_get_gdo0(void) {
return CC1100_GDO0;
}
int cc110x_get_gdo1(void) {
return CC1100_GDO1;
}
int cc110x_get_gdo2(void) {
return CC1100_GDO2;
}
void cc110x_spi_cs(void)
{
CC1100_CS_LOW;
}
uint8_t cc110x_txrx(uint8_t data)
{
/* Ensure TX Buf is empty */
long c = 0;
IFG2 &= ~UTXIFG1;
IFG2 &= ~URXIFG1;
U1TXBUF = data;
while(!(IFG2 & UTXIFG1)) {
if (c++ == 1000000) {
puts("cc110x_txrx alarm()");
}
}
/* Wait for Byte received */
c = 0;
while(!(IFG2 & URXIFG1)) {
if (c++ == 1000000) {
puts("cc110x_txrx alarm()");
}
}
return U1RXBUF;
}
void cc110x_spi_select(void)
{
// Switch to GDO mode
P5SEL &= ~0x04;
P5DIR &= ~0x04;
cs_low:
// CS to low
abort_count = 0;
CC1100_CS_LOW;
// Wait for SO to go low (voltage regulator
// has stabilized and the crystal is running)
loop:
// asm volatile ("nop");
if (CC1100_GDO1) {
abort_count++;
if (abort_count > CC1100_GDO1_LOW_COUNT) {
retry_count++;
if (retry_count > CC1100_GDO1_LOW_RETRY) {
puts("[CC1100 SPI] fatal error\n");
goto final;
}
CC1100_CS_HIGH;
goto cs_low; // try again
}
goto loop;
}
final:
/* Switch to SPI mode */
P5SEL |= 0x04;
}
void cc110x_spi_unselect(void) {
CC1100_CS_HIGH;
}
void cc110x_init_interrupts(void)
{
unsigned int state = disableIRQ(); /* Disable all interrupts */
P1SEL = 0x00; /* must be <> 1 to use interrupts */
P1IES |= 0x10; /* Enables external interrupt on low edge (for GDO2) */
P1IE |= 0x10; /* Enable interrupt */
P1IFG &= ~0x10; /* Clears the interrupt flag */
P1IE &= ~0x08; /* Disable interrupt for GDO0 */
P1IFG &= ~0x08; /* Clear IFG for GDO0 */
restoreIRQ(state); /* Enable all interrupts */
}
void cc110x_spi_init(void)
{
// Switch off async UART
while(!(U1TCTL & TXEPT)); // Wait for empty UxTXBUF register
IE2 &= ~(URXIE1 + UTXIE1); // Disable USART1 receive&transmit interrupt
ME2 &= ~(UTXE1 + URXE1);
P5DIR |= 0x0A; // output for CLK and SIMO
P5DIR &= ~(0x04); // input for SOMI
P5SEL |= 0x0E; // Set pins as SPI
// Keep peripheral in reset state
U1CTL = SWRST;
// 8-bit SPI Master 3-pin mode, with SMCLK as clock source
// CKPL works also, but not CKPH+CKPL or none of them!!
U1CTL |= CHAR + SYNC + MM;
U1TCTL = CKPH + SSEL1 + SSEL0 + STC;
// Ignore clockrate argument for now, just use clock source/2
// SMCLK = 8 MHz
U1BR0 = 0x02; // Ensure baud rate >= 2
U1BR1 = 0x00;
U1MCTL = 0x00; // No modulation
U1RCTL = 0x00; // Reset Receive Control Register
// Enable SPI mode
ME2 |= USPIE1;
// Release for operation
U1CTL &= ~SWRST;
}
/*
* CC1100 receive interrupt
*/
interrupt (PORT1_VECTOR) __attribute__ ((naked)) cc110x_isr(void){
__enter_isr();
/* Check IFG */
if ((P1IFG & 0x10) != 0) {
P1IFG &= ~0x10;
cc110x_gdo2_irq();
}
else if ((P2IFG & 0x08) != 0) {
cc110x_gdo0_irq();
P1IE &= ~0x08; // Disable interrupt for GDO0
P1IFG &= ~0x08; // Clear IFG for GDO0
}
else {
puts("cc110x_isr(): unexpected IFG!");
/* Should not occur - only GDO1 and GDO2 interrupts are enabled */
}
__exit_isr();
}

2
boards/wsn430-v1_3b/include/board.h
View File

@ -69,7 +69,5 @@ extern "C" {
#include <msp430x16x.h>
typedef uint8_t radio_packet_length_t;
/** @} */
#endif /* WSN_BOARD_H_ */

3
boards/wsn430-v1_4/Makefile
View File

@ -2,7 +2,4 @@ MODULE = $(BOARD)_base
DIRS = $(RIOTBOARD)/wsn430-common
INCLUDES += -I$(RIOTBASE)/drivers/cc2420/include \
-I$(RIOTBASE)/sys/net/include
include $(RIOTBASE)/Makefile.base

5
boards/wsn430-v1_4/Makefile.dep
View File

@ -1,6 +1 @@
USEMODULE += msp430_common
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += cc2420
USEMODULE += transceiver
endif

1
boards/wsn430-v1_4/Makefile.features
View File

@ -1,3 +1,2 @@
FEATURES_PROVIDED += transceiver
FEATURES_PROVIDED += config
FEATURES_MCU_GROUP = msp430

247
boards/wsn430-v1_4/driver_cc2420.c
View File

@ -1,247 +0,0 @@
/*
* driver_cc2420.c - Implementation of the board dependent cc2420 functions.
* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will
* Copyright (C) 2013 Milan Babel <babel@inf.fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "irq.h"
#include "hwtimer.h"
#include "panic.h"
#include "cc2420.h"
#include "cc2420_arch.h"
#include "cc2420_spi.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#define CC2420_RESETn_PIN 0x80
#define CC2420_VREGEN_PIN 0x01
#define CC2420_GDO0_PIN 0x08
#define CC2420_GDO2_PIN 0x10
#define CC2420_SFD_PIN 0x20
#define CC2420_CCA_PIN 0x40
#define CC2420_GDO0 (P1IN & CC2420_GDO0_PIN) // read serial I/O (GDO0)
#define CC2420_GDO2 (P1IN & CC2420_GDO2_PIN) // read serial I/O (GDO2)
#define CC2420_SFD (P1IN & CC2420_SFD_PIN) // read serial I/0 (SFD)
#define CC2420_CCA (P1IN & CC2420_CCA_PIN) // read serial I/O (CCA)
#define CC2420_CS_LOW (P4OUT &= ~0x04)
#define CC2420_CS_HIGH (P4OUT |= 0x04)
#define CC2420_GDO1_LOW_COUNT (2700) // loop count (timeout ~ 500 us) to wait
#define CC2420_GDO1_LOW_RETRY (100) // max. retries for GDO1 to go low
volatile int abort_count;
volatile int retry_count = 0;
void cc2420_reset(void)
{
P3OUT |= CC2420_VREGEN_PIN;
P1OUT &= ~CC2420_RESETn_PIN;
hwtimer_wait(500);
P1OUT |= CC2420_RESETn_PIN;
}
void cc2420_gdo0_enable(void)
{
P1IFG &= ~CC2420_GDO0_PIN; /* Clear IFG for GDO0 */
P1IE |= CC2420_GDO0_PIN; /* Enable interrupt for GDO0 */
}
void cc2420_gdo0_disable(void)
{
P1IE &= ~CC2420_GDO0_PIN; /* Disable interrupt for GDO0 */
P1IFG &= ~CC2420_GDO0_PIN; /* Clear IFG for GDO0 */
}
void cc2420_gdo2_enable(void)
{
P1IFG &= ~CC2420_GDO2_PIN; /* Clear IFG for GDO2 */
P1IE |= CC2420_GDO2_PIN; /* Enable interrupt for GDO2 */
}
void cc2420_gdo2_disable(void)
{
P1IE &= ~CC2420_GDO2_PIN; /* Disable interrupt for GDO2 */
P1IFG &= ~CC2420_GDO2_PIN; /* Clear IFG for GDO2 */
}
void cc2420_before_send(void)
{
// Disable SFD interrupt before sending packet
// However this is not used atm
}
void cc2420_after_send(void)
{
// Enable SFD interrupt after sending packet
// However this is not used atm
}
int cc2420_get_gdo0(void)
{
return CC2420_GDO0;
}
int cc2420_get_gdo2(void)
{
return CC2420_GDO2;
}
uint8_t cc2420_get_sfd(void)
{
return CC2420_SFD;
}
uint8_t cc2420_get_fifop(void)
{
return CC2420_GDO2;
}
#define MAX_RSSI_WAIT 1000
uint8_t cc2420_get_cca(void)
{
uint8_t status;
long count = 0;
do {
unsigned int sr = disableIRQ();
cc2420_spi_select();
status = cc2420_txrx(NOBYTE);
cc2420_spi_unselect();
restoreIRQ(sr);
count++;
if (count >= MAX_RSSI_WAIT) {
core_panic(0x2420, "cc2420_get_cca(): RSSI never valid!");
}
} while (!(status & CC2420_STATUS_RSSI_VALID));
return CC2420_CCA;
}
void cc2420_spi_cs(void)
{
CC2420_CS_LOW;
}
uint8_t cc2420_txrx(uint8_t data)
{
/* Ensure TX Buf is empty */
long c = 0;
IFG2 &= ~UTXIFG1;
IFG2 &= ~URXIFG1;
U1TXBUF = data;
while(!(IFG2 & UTXIFG1)) {
if (c++ == 1000000) {
core_panic(0x2420, "cc2420_txrx() alarm");
}
}
/* Wait for Byte received */
c = 0;
while(!(IFG2 & URXIFG1)) {
if (c++ == 1000000) {
core_panic(0x2420, "cc2420_txrx() alarm");
}
}
return U1RXBUF;
}
void cc2420_spi_select(void)
{
CC2420_CS_LOW;
}
void cc2420_spi_unselect(void) {
CC2420_CS_HIGH;
}
void cc2420_init_interrupts(void)
{
unsigned int state = disableIRQ(); /* Disable all interrupts */
P1SEL = 0x00; /* must be <> 1 to use interrupts */
P1IES |= CC2420_GDO2_PIN; /* Enables external interrupt on falling edge (for GDO2) */
P1IE |= CC2420_GDO2_PIN; /* Enable interrupt */
P1IFG &= ~CC2420_GDO2_PIN; /* Clears the interrupt flag */
P1IES |= CC2420_SFD_PIN; /* Enables external interrupt on falling edge (for GDO2) */
P1IE |= CC2420_SFD_PIN; /* Enable interrupt */
P1IFG &= ~CC2420_SFD_PIN; /* Clears the interrupt flag */
P1IE &= ~CC2420_GDO0_PIN; /* Disable interrupt for GDO0 */
P1IFG &= ~CC2420_GDO0_PIN; /* Clear IFG for GDO0 */
restoreIRQ(state); /* Enable all interrupts */
}
void cc2420_spi_init(void)
{
// Switch off async UART
while(!(U1TCTL & TXEPT)); // Wait for empty UxTXBUF register
IE2 &= ~(URXIE1 + UTXIE1); // Disable USART1 receive&transmit interrupt
ME2 &= ~(UTXE1 + URXE1);
P5DIR |= 0x0A; // output for CLK and SIMO
P5DIR &= ~(0x04); // input for SOMI
P5SEL |= 0x0E; // Set pins as SPI
// Keep peripheral in reset state
U1CTL = SWRST;
// 8-bit SPI Master 3-pin mode, with SMCLK as clock source
// CKPL works also, but not CKPH+CKPL or none of them!!
U1CTL |= CHAR + SYNC + MM;
U1TCTL = CKPH + SSEL1 + SSEL0 + STC;
// Ignore clockrate argument for now, just use clock source/2
// SMCLK = 8 MHz
U1BR0 = 0x02; // Ensure baud rate >= 2
U1BR1 = 0x00;
U1MCTL = 0x00; // No modulation
U1RCTL = 0x00; // Reset Receive Control Register
// Enable SPI mode
ME2 |= USPIE1;
// Release for operation
U1CTL &= ~SWRST;
}
/*
* CC2420 receive interrupt
*/
interrupt (PORT1_VECTOR) __attribute__ ((naked)) cc2420_isr(void){
__enter_isr();
/* Check IFG */
if ((P1IFG & CC2420_GDO2_PIN) != 0) {
DEBUG("rx interrupt");
P1IFG &= ~CC2420_GDO2_PIN;
cc2420_rx_irq();
}
else if ((P1IFG & CC2420_GDO0_PIN) != 0) {
if (cc2420_get_gdo2()) {
cc2420_rxoverflow_irq();
DEBUG("[CC2420] rxfifo overflow");
}
P1IFG &= ~CC2420_GDO0_PIN; /* Clear IFG for GDO0 */
}
else if ((P1IFG & CC2420_SFD_PIN) != 0) {
DEBUG("sfd interrupt");
P1IFG &= ~CC2420_SFD_PIN;
cc2420_switch_to_rx();
}
else {
puts("cc2420_isr(): unexpected IFG!");
/* Should not occur - only GDO1 and GDO2 interrupts are enabled */
}
__exit_isr();
}

2
boards/wsn430-v1_4/include/board.h
View File

@ -69,7 +69,5 @@ extern "C" {
#include <msp430x16x.h>
typedef uint8_t radio_packet_length_t;
/** @} */
#endif /* WSN_BOARD_H_ */

1
boards/z1/Makefile.features
View File

@ -1,2 +1 @@
FEATURES_PROVIDED += transceiver
FEATURES_MCU_GROUP = msp430

12
boards/z1/Makefile.include
View File

@ -23,15 +23,7 @@ export FFLAGS = --z1 -I -c $(PORT) -r -e -p $(HEXFILE)
export OFLAGS = -O ihex
export TERMFLAGS += -p "$(PORT)"
export INCLUDES += -I $(RIOTCPU)/msp430-common/include -I$(RIOTBOARD)/$(BOARD)/include -I$(RIOTBASE)/drivers/cc2420/include -I$(RIOTBASE)/sys/net/include
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
ifeq (,$(filter cc2240,$(USEMODULE)))
USEMODULE += cc2420
endif
ifeq (,$(filter transceiver,$(USEMODULE)))
USEMODULE += transceiver
endif
endif
export INCLUDES += -I$(RIOTCPU)/$(CPU)/include/ -I$(RIOTBOARD)/$(BOARD)/include/
export INCLUDES += -I $(RIOTCPU)/msp430-common/include
export UNDEF += $(BINDIR)msp430_common/startup.o

272
boards/z1/driver_cc2420.c
View File

@ -1,272 +0,0 @@
/*
* driver_cc2420.c - Implementation of the board dependent cc2420 functions
* for Zolertia Z1.
* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
* Copyright (C) 2014 Kévin Roussel <Kevin.Roussel@inria.fr>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_z1
* @{
*
* @file
* @brief Board specific CC2420 driver HAL for the Zolertia Z1
*
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
*
* @}
*/
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "irq.h"
#include "hwtimer.h"
#include "panic.h"
#include "cc2420.h"
#include "cc2420_arch.h"
#include "cc2420_spi.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#define CC2420_RESETn_PIN 0x40 /* RADIO_RESET <-> P4.6 */
#define CC2420_VREGEN_PIN 0x20 /* RADIO_VREG_EN <-> P4.5 */
#define CC2420_FIFOP_PIN 0x04
#define CC2420_GIO0_PIN 0x08
#define CC2420_GIO1_PIN 0x10
#define CC2420_SFD_PIN 0x02
#define CC2420_FIFOP (P1IN & CC2420_FIFOP_PIN) /* FIFOP <-> packet interrupt (P1.2) */
#define CC2420_GIO0 (P1IN & CC2420_GIO0_PIN) /* FIFO <-> GIO0 - RX data available (P1.3) */
#define CC2420_GIO1 (P1IN & CC2420_GIO1_PIN) /* CCA <-> GIO1 - clear channel (P1.4) */
#define CC2420_SFD (P4IN & CC2420_SFD_PIN) /* SFD <-> TBL - start frame delimiter (P4.1) */
#define CC2420_CS_LOW (P3OUT &= ~0x01) /* RADIO_CS <-> P3.0 */
#define CC2420_CS_HIGH (P3OUT |= 0x01)
volatile int abort_count;
volatile int retry_count = 0;
void cc2420_reset(void)
{
P4OUT |= CC2420_VREGEN_PIN;
P4OUT &= ~CC2420_RESETn_PIN;
hwtimer_wait(500);
P4OUT |= CC2420_RESETn_PIN;
}
void cc2420_gio0_enable(void)
{
P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
P1IE |= CC2420_GIO0_PIN; /* Enable interrupt for GIO0 */
}
void cc2420_gio0_disable(void)
{
P1IE &= ~CC2420_GIO0_PIN; /* Disable interrupt for GIO0 */
P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
}
void cc2420_gio1_enable(void)
{
P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
P1IE |= CC2420_GIO1_PIN; /* Enable interrupt for GIO1 */
}
void cc2420_gio1_disable(void)
{
P1IE &= ~CC2420_GIO1_PIN; /* Disable interrupt for GIO1 */
P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
}
void cc2420_before_send(void)
{
/* Disable SFD interrupt before sending packet */
/* However there is no interrupt on MSP430F2617 port 4 */
}
void cc2420_after_send(void)
{
/* Enable SFD interrupt after sending packet */
/* However there is no interrupt on MSP430F2617 port 4 */
}
int cc2420_get_gio0(void)
{
return CC2420_GIO0;
}
int cc2420_get_gio1(void)
{
return CC2420_GIO1;
}
uint8_t cc2420_get_fifop(void)
{
return CC2420_FIFOP;
}
uint8_t cc2420_get_sfd(void)
{
return CC2420_SFD;
}
#define MAX_RSSI_WAIT 1000
uint8_t cc2420_get_cca(void)
{
uint8_t status;
long count = 0;
do {
unsigned int sr = disableIRQ();
cc2420_spi_select();
status = cc2420_txrx(NOBYTE);
cc2420_spi_unselect();
restoreIRQ(sr);
count++;
if (count >= MAX_RSSI_WAIT) {
core_panic(0x2420, "cc2420_get_cca(): RSSI never valid!");
}
} while (!(status & CC2420_STATUS_RSSI_VALID));
return CC2420_GIO1;
}
void cc2420_spi_cs(void)
{
CC2420_CS_LOW; /* Chip Select line is active-low */
}
#define MAX_SPI_WAIT 1000
uint8_t cc2420_txrx(uint8_t data)
{
/* Wait for SPI to be ready for transmission */
long count = 0;
do {
count++;
if (count >= MAX_SPI_WAIT) {
core_panic(0x2420, "cc2420_txrx(): SPI never ready for TX!");
}
} while (!(IFG2 & UCB0TXIFG));
/* Transmit data byte to CC2420, and wait for end of transmission */
IFG2 &= ~UCB0RXIFG;
UCB0TXBUF = data;
count = 0;
do {
count++;
if (count >= MAX_SPI_WAIT) {
core_panic(0x2420, "cc2420_txrx(): couldn't send byte!");
}
} while (UCB0STAT & UCBUSY);
/* Read the byte that CC2420 has (normally, during TX) returned */
count = 0;
do {
count++;
if (count >= MAX_SPI_WAIT) {
core_panic(0x2420, "cc2420_txrx(): couldn't receive byte!");
}
} while (!(IFG2 & UCB0RXIFG));
/* Return received byte */
return UCB0RXBUF;
}
void cc2420_spi_select(void)
{
CC2420_CS_LOW;
}
void cc2420_spi_unselect(void) {
CC2420_CS_HIGH;
}
void cc2420_init_interrupts(void)
{
unsigned int state = disableIRQ(); /* Disable all interrupts */
/* done in board.c : function z1_ports_init()
P1SEL &= ~CC2420_FIFOP_PIN; // must be <> 1 to use interrupts
P1SEL &= ~CC2420_GIO0_PIN; // must be <> 1 to use interrupts
*/
/* FIFO <-> GIO0 interrupt */
P1IES |= CC2420_GIO0_PIN; /* Enable external interrupt on falling edge for GIO0/FIFO */
P1IE |= CC2420_GIO0_PIN;
P1IFG &= ~CC2420_GIO0_PIN; /* Clear the interrupt flag */
/* FIFOP <-> Packet interrupt */
P1IES &= ~CC2420_FIFOP_PIN; /* Enable external interrupt on rising edge for FIFOP */
P1IE |= CC2420_FIFOP_PIN;
P1IFG &= ~CC2420_FIFOP_PIN; /* Clear IFG for FIFOP */
restoreIRQ(state); /* Enable all interrupts */
}
void cc2420_spi_init(void)
{
/*
* NOTES :
* - we will use SPI mode using block B of the USCI0,
* so as to avoid disturbing UART0 which is managed by USCI0 block A
* - MCU pin (GPIO port) initialisation is done in board.c,
* function z1_ports_init().
*/
/* Keep peripheral in reset state during configuration */
UCB0CTL1 = UCSWRST;
/* 8-bit SPI Master 3-pin mode, MSB first,
with SMCLK as clock source */
UCB0CTL0 = UCSYNC + UCMST + UCMODE_0 + UCMSB;
UCB0CTL1 |= UCSSEL_3;
UCB0CTL0 |= UCCKPH; /* Data captured on rising edge, changed on falling */
UCB0CTL0 &= ~UCCKPL; /* SPI data lines are active-high/inactive-low */
/* Ignore clockrate argument for now, just use clock source/2 */
UCB0BR0 = 0x02; /* Ensure baud rate <= SMCLK/2 */
UCB0BR1 = 0x00;
/* Release for operation */
UCB0CTL1 &= ~UCSWRST;
}
/*
* CC2420 receive interrupt
*/
interrupt (PORT1_VECTOR) __attribute__ ((naked)) cc2420_isr(void)
{
__enter_isr();
/* Check if FIFOP signal is raising => RX interrupt */
if ((P1IFG & CC2420_FIFOP_PIN) != 0) {
P1IFG &= ~CC2420_FIFOP_PIN;
cc2420_rx_irq();
DEBUG("rx interrupt");
}
/* GIO0 is falling => check if FIFOP is high, indicating an RXFIFO overflow */
else if ((P1IFG & CC2420_GIO0_PIN) != 0) {
P1IFG &= ~CC2420_GIO0_PIN;
if (cc2420_get_fifop()) {
cc2420_rxoverflow_irq();
DEBUG("[CC2420] rxfifo overflow");
}
}
else {
puts("cc2420_isr(): unexpected IFG!");
/* Should not occur - only FIFOP and GIO0 interrupts are enabled */
}
__exit_isr();
}

2
boards/z1/include/board.h
View File

@ -76,8 +76,6 @@ extern "C" {
#define USER_BTN_PRESSED ((USER_BTN_PxIN & USER_BTN_MASK) == 0)
#define USER_BTN_RELEASED ((USER_BTN_PxIN & USER_BTN_MASK) != 0)
typedef uint8_t radio_packet_length_t;
#ifdef __cplusplus
}
#endif

225
cpu/cc430/cc110x_cc430.c
View File

@ -1,225 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cc430
* @{
*/
/**
* @file
* @brief eZ430 radio driver (cpu dependent part)
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
*
*/
#include <stdint.h>
#include "irq.h"
#include "cc110x_legacy.h"
#include "board.h"
#include "hwtimer.h"
/**************************************************************************************************
* @fn Strobe
* @brief Send command to radio.
* @param none
* @return none
*************************************************************************************************/
uint8_t cc110x_strobe(uint8_t c)
{
uint8_t statusByte = 0;
/* Check for valid strobe command */
if ((c == 0xBD) || ((c > RF_SRES) && (c < RF_SNOP))) {
uint16_t int_state = disableIRQ();
/* Clear the Status read flag */
RF1AIFCTL1 &= ~(RFSTATIFG);
/* Wait for radio to be ready for next instruction */
while (!(RF1AIFCTL1 & RFINSTRIFG));
/* Write the strobe instruction */
if ((c > RF_SRES) && (c < RF_SNOP)) {
uint16_t gdo_state = cc110x_read_reg(IOCFG2); /* buffer IOCFG2 state */
cc110x_write_reg(IOCFG2, 0x29); /* c-ready to GDO2 */
RF1AINSTRB = c;
if ((RF1AIN & 0x04) == 0x04) { /* chip at sleep mode */
if ((c == RF_SXOFF) || (c == RF_SPWD) || (c == RF_SWOR)) { }
else {
while ((RF1AIN & 0x04) == 0x04); /* c-ready ? */
hwtimer_wait(RTIMER_TICKS(9800)); /* Delay for ~810usec at 12MHz CPU clock */
}
}
cc110x_write_reg(IOCFG2, gdo_state); /* restore IOCFG2 setting */
}
else { /* chip active mode */
RF1AINSTRB = c;
}
statusByte = RF1ASTATB;
while (!(RF1AIFCTL1 & RFSTATIFG));
restoreIRQ(int_state);
}
return statusByte;
}
/***************************************************************************************************
* @fn cc110x_read_reg
* @brief Read byte from register.
* @param none
* @return none
***************************************************************************************************/
uint8_t cc110x_read_reg(uint8_t addr)
{
unsigned char x;
uint16_t int_state;
int_state = disableIRQ();
RF1AINSTR1B = (addr | RF_REGRD);
x = RF1ADOUT1B;
restoreIRQ(int_state);
return x;
}
/**************************************************************************************************
* @fn cc110x_write_reg
* @brief Write byte to register.
* @param none
* @return none
**************************************************************************************************/
void cc110x_write_reg(uint8_t addr, uint8_t value)
{
volatile unsigned int i;
uint16_t int_state;
int_state = disableIRQ();
while (!(RF1AIFCTL1 & RFINSTRIFG)); /* Wait for the Radio to be ready for the next instruction */
RF1AINSTRW = ((addr | RF_REGWR) << 8) + value; /* Send address + Instruction */
while (!(RFDINIFG & RF1AIFCTL1));
/* cppcheck: need to force a read to RF1ADOUTB to trigger reset */
/* cppcheck-suppress unreadVariable */
i = RF1ADOUTB; /* Reset RFDOUTIFG flag which contains status byte */
(void)i; /* Ignore variable 'i' set but not used [-Werror=unused-but-set-variable] */
restoreIRQ(int_state);
}
uint8_t cc110x_read_status(uint8_t addr)
{
unsigned char x;
uint16_t int_state;
int_state = disableIRQ();
RF1AINSTR1B = (addr | RF_STATREGRD);
x = RF1ADOUT1B;
restoreIRQ(int_state);
return x;
}
/****************************************************************************************************
* @fn cc110x_readburst_reg
* @brief Read sequence of bytes from register.
* @param none
* @return none
***************************************************************************************************/
void cc110x_readburst_reg(uint8_t addr, char *buffer, uint8_t count)
{
unsigned int i;
uint16_t int_state;
int_state = disableIRQ();
while (!(RF1AIFCTL1 & RFINSTRIFG)); /* Wait for the Radio to be ready for next instruction */
RF1AINSTR1B = (addr | RF_REGRD); /* Send address + Instruction */
for (i = 0; i < (count - 1); i++) {
while (!(RFDOUTIFG & RF1AIFCTL1)); /* Wait for the Radio Core to update the RF1ADOUTB reg */
buffer[i] = RF1ADOUT1B; /* Read DOUT from Radio Core + clears RFDOUTIFG */
/* Also initiates auo-read for next DOUT byte */
}
buffer[count - 1] = RF1ADOUT0B; /* Store the last DOUT from Radio Core */
restoreIRQ(int_state);
}
void cc110x_read_fifo(char *buffer, uint8_t count)
{
unsigned int i;
uint16_t int_state;
int_state = disableIRQ();
while (!(RF1AIFCTL1 & RFINSTRIFG)); /* Wait for the Radio to be ready for next instruction */
RF1AINSTR1B = (RF_RXFIFORD); /* Send address + Instruction */
for (i = 0; i < (count - 1); i++) {
while (!(RFDOUTIFG & RF1AIFCTL1)); /* Wait for the Radio Core to update the RF1ADOUTB reg */
buffer[i] = RF1ADOUT1B; /* Read DOUT from Radio Core + clears RFDOUTIFG */
/* Also initiates auo-read for next DOUT byte */
}
buffer[count - 1] = RF1ADOUT0B; /* Store the last DOUT from Radio Core */
restoreIRQ(int_state);
}
/***************************************************************************************************
* @fn cc110x_writeburst_reg
* @brief Write sequence of bytes to register.
* @param none
* @return none
**************************************************************************************************/
uint8_t cc110x_writeburst_reg(uint8_t addr, char *buffer, uint8_t count)
{
/* Write Burst works wordwise not bytewise - bug known already */
unsigned char i;
uint16_t int_state;
int_state = disableIRQ();
while (!(RF1AIFCTL1 & RFINSTRIFG)); /* Wait for the Radio to be ready for next instruction */
RF1AINSTRW = ((addr | RF_REGWR) << 8) + buffer[0]; /* Send address + Instruction */
for (i = 1; i < count; i++) {
RF1ADINB = buffer[i]; /* Send data */
while (!(RFDINIFG & RF1AIFCTL1)); /* Wait for TX to finish */
}
/* cppcheck: need to force a read to RF1ADOUTB to trigger reset */
/* cppcheck-suppress unreadVariable */
i = RF1ADOUTB; /* Reset RFDOUTIFG flag which contains status byte */
restoreIRQ(int_state);
return count;
}

3
cpu/k60/include/cpu_conf.h
View File

@ -254,9 +254,6 @@ typedef enum llwu_wakeup_pin {
#define ISR_PORT_E isr_porte_pin_detect
/** @} */
/** @brief Number of packets in transceiver queue */
#define TRANSCEIVER_BUFFER_SIZE (3)
/**
* @name Bit band macros
* @{

2
cpu/kw2x/include/cpu_conf.h
View File

@ -61,8 +61,6 @@ extern "C"
*/
#define CPUID_ID_PTR ((void *)(&(SIM_UIDH)))
#define TRANSCEIVER_BUFFER_SIZE (3) /**< Buffer Size for Transceiver Module */
/**
* @brief MCU specific Low Power Timer settings.
*/

8
cpu/lpc2387/include/cpu_conf.h
View File

@ -63,14 +63,6 @@ extern "C" {
#define CC_CONF_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
/** @} */
/**
* @name Transceiver configuration
* @{
*/
#define TRANSCEIVER_BUFFER_SIZE (10)
#define RX_BUF_SIZE (10)
/** @} */
/**
* @name UART0 buffer size definition for compatibility reasons
*

8
cpu/mc1322x/include/cpu_conf.h
View File

@ -60,14 +60,6 @@ extern "C" {
#define CC_CONF_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
/** @} */
/**
* @brief Transceiver configuration
* @{
*/
#define TRANSCEIVER_BUFFER_SIZE (10)
#define RX_BUF_SIZE (10)
/** @} */
/**
* @name UART0 buffer size definition for compatibility reasons
*

3
cpu/msp430-common/include/cpu_conf.h
View File

@ -27,9 +27,6 @@ extern "C" {
#define THREAD_STACKSIZE_IDLE (96)
#define MSP430_ISR_STACK_SIZE (256)
#define RX_BUF_SIZE (3)
#define TRANSCEIVER_BUFFER_SIZE (3)
#ifndef UART0_BUFSIZE
#define UART0_BUFSIZE (32)
#endif

4
cpu/native/Makefile
View File

@ -1,9 +1,7 @@
MODULE = cpu
DIRS += periph
ifneq (,$(filter nativenet,$(USEMODULE)))
DIRS += net
endif
ifneq (,$(filter ng_nativenet,$(USEMODULE)))
DIRS += ng_net
endif

10
cpu/native/include/cpu_conf.h
View File

@ -34,11 +34,6 @@ extern "C" {
#define THREAD_EXTRA_STACKSIZE_PRINTF_FLOAT (163840)
/* for core/include/thread.h */
#define THREAD_STACKSIZE_MINIMUM (163840)
/* undefine the TRANSCEIVER_STACK_SIZE (2048 or 512) defined in transceiver.h */
#ifdef TRANSCEIVER_STACK_SIZE
#undef TRANSCEIVER_STACK_SIZE
#endif
#define TRANSCEIVER_STACK_SIZE (163840)
/* native internal */
#define THREAD_STACKSIZE_MINIMUM (163840)
#define NATIVE_ISR_STACKSIZE (163840)
@ -50,11 +45,6 @@ extern "C" {
#define THREAD_EXTRA_STACKSIZE_PRINTF_FLOAT (8192)
/* for core/include/thread.h */
#define THREAD_STACKSIZE_MINIMUM (8192)
/* undefine the TRANSCEIVER_STACK_SIZE (2048 or 512) defined in transceiver.h */
#ifdef TRANSCEIVER_STACK_SIZE
#undef TRANSCEIVER_STACK_SIZE
#endif
#define TRANSCEIVER_STACK_SIZE (16384)
/* native internal */
#define NATIVE_ISR_STACKSIZE (8192)
#endif /* OS */

182
cpu/native/include/nativenet.h
View File

@ -1,182 +0,0 @@
/*
* nativenet transceiver interface
*
* A configurable transceiver for the native port.
*
* At the moment only the tap interface is supported, but more network
* layers are intended. So the "configurable" part is a lie for now ;-)
* The effect of calls like nativenet_set_channel depend on the
* network layer.
*
* Copyright (C) 2013, 2014 Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup native_net Native network interface
* @ingroup native_cpu
* @{
* @author Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
*/
#ifndef NATIVENET_H
#define NATIVENET_H
#if defined(__FreeBSD__)
#include <sys/types.h>
#endif
#include <net/ethernet.h>
#include "radio/types.h"
#include "kernel_types.h"
#include "netdev/base.h"
#ifndef RX_BUF_SIZE
#define RX_BUF_SIZE (10)
#endif
#ifndef TRANSCEIVER_BUFFER_SIZE
#define TRANSCEIVER_BUFFER_SIZE (10)
#endif
/**
* @brief Number of registrable netdev_rcv_data_cb_t callbacks per nativenet
* device
*/
#define NATIVENET_DEV_CB_MAX (128)
/**
* @brief Broadcast address
*/
#define NATIVE_BROADCAST_ADDRESS (0)
#ifndef NATIVE_MAX_DATA_LENGTH
#include "tap.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef MODULE_SIXLOWPAN
#define NATIVE_MAX_DATA_LENGTH (127)
#else
#define NATIVE_MAX_DATA_LENGTH (TAP_MAX_DATA)
#endif
#else
#warning be careful not to exceed (TAP_MAX_DATA) with NATIVE_MAX_DATA_LENGTH
#endif /* NATIVE_MAX_DATA_LENGTH */
/**
* @brief Implementation of netdev_driver_t for nativenet
*/
extern const netdev_driver_t nativenet_driver;
/**
* @brief Default @ref netdev API device
*/
extern netdev_t nativenet_default_dev;
/**
* Initialize @ref sys_transceiver and @ref nativenet_default_dev
*
* @param transceiver_pid the pid of the transceiver thread
*/
void nativenet_init(kernel_pid_t transceiver_pid);
/**
* Shutdown transceiver
*/
void nativenet_powerdown(void);
/**
* Enable/disable monitor mode
*
* @param mode 0 off, 1 on
*/
void nativenet_set_monitor(uint8_t mode);
/**
* Send a packet
*
* @param packet a radio packet
* @return -1 if the operation failed, the number of transmitted bytes
* up to INT8_MAX otherwise
*/
int8_t nativenet_send(radio_packet_t *packet);
/**
* Set transceiver address
*
* @param address the address
* @return the address
*/
radio_address_t nativenet_set_address(radio_address_t address);
/**
* Get transceiver address
*
* @return the address
*/
radio_address_t nativenet_get_address(void);
/**
* @brief Sets the IEEE long address of the nativenet transceiver.
*
* @param[in] addr The desired address.
*
* @return The set address after calling.
*/
uint64_t nativenet_set_address_long(uint64_t addr);
/**
* @brief Gets the current IEEE long address of the nativenet
* transceiver.
*
* @return The current IEEE long address.
*/
uint64_t nativenet_get_address_long(void);
/**
* Set transceiver channel
*
* @param channel the channel
* @return the channel
*/
int16_t nativenet_set_channel(uint8_t channel);
/**
* Get transceiver channel
*
* @return the channel
*/
int16_t nativenet_get_channel(void);
/**
* Set transceiver pan
*
* @param pan the pan
* @return the pan
*/
uint16_t nativenet_set_pan(uint16_t pan);
/**
* Get transceiver pan
*
* @return the pan
*/
uint16_t nativenet_get_pan(void);
/**
* Enable transceiver rx mode
*/
void nativenet_switch_to_rx(void);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* NATIVENET_H */

109
cpu/native/include/nativenet_internal.h
View File

@ -1,109 +0,0 @@
/**
* internal nativenet transceiver interface
*
* Copyright (C) 2013 Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @{
* @author Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
* @}
*/
#ifndef NATIVENET_INTERNAL_H
#define NATIVENET_INTERNAL_H
#include "tap.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NNEV_PWRDWN 0x01
#define NNEV_PWRUP 0x02
#define NNEV_MONITOR 0x03
#define NNEV_GETCHAN 0x04
#define NNEV_SETCHAN 0x05
#define NNEV_GETADDR 0x06
#define NNEV_SETADDR 0x07
#define NNEV_GETPAN 0x08
#define NNEV_SETPAN 0x09
#define NNEV_SEND 0x0a
#define NNEV_SWTRX 0x0b
#define NNEV_MAXEV 0x0b
#define _NATIVENET_DEV_MORE(dev) ((_nativenet_netdev_more_t *)dev->more)
struct rx_buffer_s {
radio_packet_t packet;
char data[NATIVE_MAX_DATA_LENGTH];
};
extern struct rx_buffer_s _nativenet_rx_buffer[RX_BUF_SIZE];
/**
* @brief Definition of network device data.
*/
typedef struct {
/**
* @brief The channel assigned to this device
*
* @note For internal use only, do not change externally!
*
* @internal
*/
uint8_t _channel;
/**
* @brief The PAN ID assigned to this device
*
* @note For internal use only, do not change externally!
* @internal
*/
uint16_t _pan_id;
/**
* @brief The short address assigned to this device
*
* @note For internal use only, do not change externally!
* @internal
*/
radio_address_t _radio_addr;
/**
* @brief The long address assigned to this device
*
* @note For internal use only, do not change externally!
* @internal
*/
uint64_t _long_addr;
/**
* @brief Flag to determine if device is in promiscuous mode
*
* @note For internal use only, do not change externally!
* @internal
*/
uint8_t _is_monitoring;
/**
* @brief Receive data callbacks for this device
*/
netdev_rcv_data_cb_t _callbacks[NATIVENET_DEV_CB_MAX];
} _nativenet_netdev_more_t;
/* internal counterpart to nativenet_default_dev */
extern _nativenet_netdev_more_t _nativenet_default_dev_more;
void _nativenet_handle_packet(radio_packet_t *packet);
int8_t send_buf(radio_packet_t *packet);
#ifdef __cplusplus
}
#endif
#endif /* NATIVENET_INTERNAL_H */

70
cpu/native/include/tap.h
View File

@ -1,70 +0,0 @@
/**
* internal nativenet tap network layer interface
*
* Copyright (C) 2013 Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @{
* @author Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
* @}
*/
#ifndef _TAP_H
#define _TAP_H
#include <net/ethernet.h>
#include "board.h"
#include "radio/types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* create and/or open tap device "name"
*
* if "name" is an empty string, the kernel chooses a name
* if "name" is an existing device, that device is used
* otherwise a device named "name" is created
*
* On OSX a name has to be provided.
*/
int tap_init(char *name);
/**
* Close tap device
*/
void tap_cleanup(void);
extern unsigned char _native_tap_mac[ETHER_ADDR_LEN];
struct nativenet_header {
radio_packet_length_t length;
radio_address_t dst;
radio_address_t src;
} __attribute__((packed));
#define TAP_MAX_DATA ((ETHERMTU) - 6) /* XXX: this is suboptimal */
struct nativenet_packet {
struct nativenet_header nn_header;
uint8_t data[ETHERMTU - sizeof(struct nativenet_header)];
} __attribute__((packed));
union eth_frame {
struct {
struct ether_header header;
struct nativenet_packet payload;
} field;
unsigned char buffer[ETHER_MAX_LEN];
} __attribute__((packed));
#ifdef __cplusplus
}
#endif
#endif /* _TAP_H */

8
cpu/native/native_cpu.c
View File

@ -48,9 +48,7 @@
#include "cpu.h"
#include "cpu_conf.h"
#ifdef MODULE_NATIVENET
#include "tap.h"
#endif
#ifdef MODULE_NG_NATIVENET
#include "dev_eth_tap.h"
extern dev_eth_tap_t dev_eth_tap;
@ -76,9 +74,7 @@ int reboot_arch(int mode)
#ifdef MODULE_UART0
/* TODO: close stdio fds */
#endif
#ifdef MODULE_NATIVENET
tap_cleanup();
#endif
#ifdef MODULE_NG_NATIVENET
dev_eth_tap_cleanup(&dev_eth_tap);
#endif

5
cpu/native/net/Makefile
View File

@ -1,5 +0,0 @@
MODULE = nativenet
include $(RIOTBASE)/Makefile.base
INCLUDES = $(NATIVEINCLUDES)

618
cpu/native/net/interface.c
View File

@ -1,618 +0,0 @@
/**
* nativenet.h implementation
*
* Copyright (C) 2013 Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
* @ingroup native_cpu
* @ingroup net
* @{
* @file
* @author Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
*/
#include <stdio.h>
#include <err.h>
#include <stdint.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <inttypes.h>
#include <arpa/inet.h>
#define ENABLE_DEBUG (0)
#include "debug.h"
#include "transceiver.h"
#include "msg.h"
#include "native_internal.h"
#include "tap.h"
#include "nativenet.h"
#include "nativenet_internal.h"
#include "cpu.h"
static _native_callback_t _nativenet_callbacks[255];
struct rx_buffer_s _nativenet_rx_buffer[RX_BUF_SIZE];
static volatile uint8_t rx_buffer_next;
static kernel_pid_t _native_net_tpid = KERNEL_PID_UNDEF;
/************************************************************************/
/* nativenet.h **********************************************************/
/************************************************************************/
int _nativenet_init(netdev_t *dev)
{
if ((dev->type != NETDEV_TYPE_BASE) || (dev->more == NULL)) {
return -ENODEV;
}
_NATIVENET_DEV_MORE(dev)->_channel = 0;
_NATIVENET_DEV_MORE(dev)->_pan_id = 0;
_NATIVENET_DEV_MORE(dev)->_is_monitoring = 0;
memset(_NATIVENET_DEV_MORE(dev)->_callbacks, 0,
sizeof((_NATIVENET_DEV_MORE(dev)->_callbacks)));
return 0;
}
void nativenet_init(kernel_pid_t transceiver_pid)
{
DEBUG("nativenet_init(transceiver_pid=%" PRIkernel_pid ")\n", transceiver_pid);
rx_buffer_next = 0;
_nativenet_init((netdev_t *)(&nativenet_default_dev));
_native_net_tpid = transceiver_pid;
}
void nativenet_powerdown(void)
{
return;
}
void nativenet_set_monitor(uint8_t mode)
{
DEBUG("nativenet_set_monitor(mode=%d)\n", mode);
_nativenet_default_dev_more._is_monitoring = mode;
}
int16_t nativenet_set_channel(uint8_t channel)
{
_nativenet_default_dev_more._channel = channel;
return _nativenet_default_dev_more._channel;
}
int16_t nativenet_get_channel(void)
{
return _nativenet_default_dev_more._channel;
}
uint16_t nativenet_set_pan(uint16_t pan)
{
_nativenet_default_dev_more._pan_id = pan;
return _nativenet_default_dev_more._pan_id;
}
uint16_t nativenet_get_pan(void)
{
return _nativenet_default_dev_more._pan_id;
}
radio_address_t nativenet_set_address(radio_address_t address)
{
DEBUG("nativenet_set_address(address=%d)\n", address);
_nativenet_default_dev_more._radio_addr = address;
return _nativenet_default_dev_more._radio_addr;
}
radio_address_t nativenet_get_address(void)
{
DEBUG("nativenet_get_address -> address = %d\n",
_nativenet_default_dev_more._radio_addr);
return _nativenet_default_dev_more._radio_addr;
}
uint64_t nativenet_get_address_long(void)
{
DEBUG("nativenet_get_address_long -> address = %" PRIx64 "\n",
_nativenet_default_dev_more._long_addr);
return _nativenet_default_dev_more._long_addr;
}
uint64_t nativenet_set_address_long(uint64_t address)
{
DEBUG("nativenet_set_address_long(address=%" PRIx64 ")\n", address);
warnx("nativenet_set_address_long: this does not actually change the interfaces address");
_nativenet_default_dev_more._long_addr = address;
return _nativenet_default_dev_more._long_addr;
}
int8_t nativenet_send(radio_packet_t *packet)
{
packet->src = _nativenet_default_dev_more._radio_addr;
DEBUG("nativenet_send: Sending packet of length %" PRIu16 " from %" PRIu16 " to %" PRIu16 "\n",
packet->length, packet->src, packet->dst);
return send_buf(packet);
}
void nativenet_switch_to_rx(void)
{
return;
}
/************************************************************************/
/* nativenet_internal.h *************************************************/
/************************************************************************/
int _nativenet_register_cb(int event, _native_callback_t func)
{
if (event > NNEV_MAXEV) {
DEBUG("_nativenet_register_cb: event > NNEV_MAXEV\n");
return -1;
}
_nativenet_callbacks[event] = func;
return 0;
}
int _nativenet_unregister_cb(int event)
{
if (event > NNEV_MAXEV) {
DEBUG("_nativenet_unregister_cb: event > NNEV_MAXEV\n");
return -1;
}
_nativenet_callbacks[event] = NULL;
return 0;
}
void do_cb(int event)
{
if (event > NNEV_MAXEV) {
DEBUG("do_cb: event > NNEV_MAXEV\n");
return;
}
if (_nativenet_callbacks[event] != NULL) {
_nativenet_callbacks[event]();
}
}
void _nativenet_handle_packet(radio_packet_t *packet)
{
radio_address_t dst_addr = packet->dst;
int notified = 0;
/* TODO: find way to demultiplex reception from several taps and map them
* to devices. */
netdev_t *dev = &nativenet_default_dev;
/* address filter / monitor mode */
if (_nativenet_default_dev_more._is_monitoring == 1) {
DEBUG("_nativenet_handle_packet: monitoring, not filtering address \n");
}
else {
/* own addr check */
if (dst_addr == _nativenet_default_dev_more._radio_addr) {
DEBUG("_nativenet_handle_packet: accept packet, addressed to us\n");
}
else if (dst_addr == NATIVE_BROADCAST_ADDRESS) {
DEBUG("_nativenet_handle_packet: accept packet, broadcast\n");
}
else {
DEBUG("_nativenet_handle_packet: discard packet addressed to someone else\n");
return;
}
}
/* copy packet to rx buffer */
DEBUG("\n\t\trx_buffer_next: %i\n\n", rx_buffer_next);
memcpy(&_nativenet_rx_buffer[rx_buffer_next].data, packet->data, packet->length);
memcpy(&_nativenet_rx_buffer[rx_buffer_next].packet, packet, sizeof(radio_packet_t));
_nativenet_rx_buffer[rx_buffer_next].packet.data = (uint8_t *)
&_nativenet_rx_buffer[rx_buffer_next].data;
/* notify transceiver thread if any */
if (_native_net_tpid != KERNEL_PID_UNDEF) {
DEBUG("_nativenet_handle_packet: notifying transceiver thread!\n");
msg_t m;
m.type = (uint16_t) RCV_PKT_NATIVE;
m.content.value = rx_buffer_next;
msg_send_int(&m, _native_net_tpid);
notified = 1;
}
for (int i = 0; i < NATIVENET_DEV_CB_MAX; i++) {
if (_NATIVENET_DEV_MORE(dev)->_callbacks[i]) {
_NATIVENET_DEV_MORE(dev)->_callbacks[i]((netdev_t *)dev,
&(_nativenet_rx_buffer[rx_buffer_next].packet.src),
sizeof(uint16_t),
&(_nativenet_rx_buffer[rx_buffer_next].packet.dst),
sizeof(uint16_t),
&(_nativenet_rx_buffer[rx_buffer_next].data),
(size_t)_nativenet_rx_buffer[rx_buffer_next].packet.length);
notified = 1;
}
}
if (!notified) {
DEBUG("_nativenet_handle_packet: no one to notify =(\n");
}
/* shift to next buffer element */
if (++rx_buffer_next == RX_BUF_SIZE) {
rx_buffer_next = 0;
}
}
/***************************************************************
* netdev_base wrapper
***************************************************************/
#ifdef MODULE_NETDEV_BASE
int _nativenet_send_data(netdev_t *dev, void *dest, size_t dest_len,
netdev_hlist_t *upper_layer_hdrs, void *data,
size_t data_len)
{
netdev_hlist_t *ptr = upper_layer_hdrs;
uint8_t tx_buffer[data_len + netdev_get_hlist_len(upper_layer_hdrs)];
size_t tx_ptr = 0;
radio_packet_t pkt = {0, 0, 0, 0, 0, {0, 0}, sizeof(tx_buffer), tx_buffer};
if (dev->type != NETDEV_TYPE_BASE) {
return -ENODEV;
}
if (dest_len > sizeof(uint16_t)) {
return -EAFNOSUPPORT;
}
if (sizeof(tx_buffer) > NATIVE_MAX_DATA_LENGTH) {
return -EMSGSIZE;
}
if (upper_layer_hdrs) {
do {
memcpy(&(tx_buffer[tx_ptr]), ptr->header, ptr->header_len);
tx_ptr += ptr->header_len;
netdev_hlist_advance(&ptr);
} while (ptr != upper_layer_hdrs);
}
memcpy(&(tx_buffer[tx_ptr]), data, data_len);
if (dest_len == sizeof(uint16_t)) {
pkt.dst = *((uint16_t *)dest);
}
else {
pkt.dst = (uint16_t)(*((uint8_t *)dest));
}
return nativenet_send(&pkt);
}
int _nativenet_add_rcv_data_cb(netdev_t *dev, netdev_rcv_data_cb_t cb)
{
int i = 0;
if (dev->type != NETDEV_TYPE_BASE) {
return -ENODEV;
}
for (i = 0; i < NATIVENET_DEV_CB_MAX; i++) {
if (_NATIVENET_DEV_MORE(dev)->_callbacks[i] == NULL ||
_NATIVENET_DEV_MORE(dev)->_callbacks[i] == cb) {
break;
}
}
if (i >= NATIVENET_DEV_CB_MAX) {
return -ENOBUFS;
}
_NATIVENET_DEV_MORE(dev)->_callbacks[i] = cb;
return 0;
}
int _nativenet_rem_rcv_data_cb(netdev_t *dev, netdev_rcv_data_cb_t cb)
{
int i = 0;
if (dev->type != NETDEV_TYPE_BASE) {
return -ENODEV;
}
for (i = 0; i < NATIVENET_DEV_CB_MAX; i++) {
if (_NATIVENET_DEV_MORE(dev)->_callbacks[i] == cb) {
_NATIVENET_DEV_MORE(dev)->_callbacks[i] = NULL;
}
}
return 0;
}
int _nativenet_get_option(netdev_t *dev, netdev_opt_t opt, void *value,
size_t *value_len)
{
if (dev->type != NETDEV_TYPE_BASE) {
return -ENODEV;
}
switch (opt) {
case NETDEV_OPT_CHANNEL:
if (*value_len == 0) {
return -EOVERFLOW;
}
if (*value_len > sizeof(uint8_t)) {
*value_len = sizeof(uint8_t);
}
*((uint8_t *)value) = _NATIVENET_DEV_MORE(dev)->_channel;
break;
case NETDEV_OPT_ADDRESS:
if (*value_len < sizeof(radio_address_t)) {
return -EOVERFLOW;
}
if (*value_len > sizeof(radio_address_t)) {
*value_len = sizeof(radio_address_t);
}
*((radio_address_t *)value) = _NATIVENET_DEV_MORE(dev)->_radio_addr;
break;
case NETDEV_OPT_NID:
if (*value_len < sizeof(uint16_t)) {
return -EOVERFLOW;
}
if (*value_len > sizeof(uint16_t)) {
*value_len = sizeof(uint16_t);
}
*((uint16_t *)value) = _NATIVENET_DEV_MORE(dev)->_pan_id;
break;
case NETDEV_OPT_ADDRESS_LONG:
if (*value_len < sizeof(uint64_t)) {
return -EOVERFLOW;
}
if (*value_len > sizeof(uint64_t)) {
*value_len = sizeof(uint64_t);
}
*((uint64_t *)value) = _NATIVENET_DEV_MORE(dev)->_long_addr;
break;
case NETDEV_OPT_MAX_PACKET_SIZE:
if (*value_len < sizeof(NATIVE_MAX_DATA_LENGTH)) {
return -EOVERFLOW;
}
if (*value_len > sizeof(NATIVE_MAX_DATA_LENGTH)) {
*value_len = sizeof(NATIVE_MAX_DATA_LENGTH);
}
*((netdev_proto_t *)value) = NATIVE_MAX_DATA_LENGTH;
break;
case NETDEV_OPT_PROTO:
if (*value_len < sizeof(netdev_proto_t)) {
return -EOVERFLOW;
}
if (*value_len > sizeof(netdev_proto_t)) {
*value_len = sizeof(netdev_proto_t);
}
*((netdev_proto_t *)value) = NETDEV_PROTO_RADIO;
break;
default:
return -ENOTSUP;
}
return 0;
}
static int _type_pun_up(void *value_out, size_t desired_len,
void *value_in, size_t given_len)
{
if (given_len > desired_len) {
return -EOVERFLOW;
}
/* XXX this is ugly, but bear with me */
switch (given_len) {
case 8:
switch (desired_len) {
case 8:
*((uint64_t *)value_out) = (*((uint64_t *)value_in));
return 0;
default:
return -EINVAL;
}
case 4:
switch (desired_len) {
case 8:
*((uint64_t *)value_out) = (uint64_t)(*((uint32_t *)value_in));
return 0;
case 4:
*((uint32_t *)value_out) = (*((uint32_t *)value_in));
return 0;
default:
return -EINVAL;
}
case 2:
switch (desired_len) {
case 8:
*((uint64_t *)value_out) = (uint64_t)(*((uint16_t *)value_in));
return 0;
case 4:
*((uint32_t *)value_out) = (uint32_t)(*((uint16_t *)value_in));
return 0;
case 2:
*((uint16_t *)value_out) = (*((uint16_t *)value_in));
return 0;
default:
return -EINVAL;
}
case 1:
switch (desired_len) {
case 8:
*((uint64_t *)value_out) = (uint64_t)(*((uint8_t *)value_in));
return 0;
case 4:
*((uint32_t *)value_out) = (uint32_t)(*((uint8_t *)value_in));
return 0;
case 2:
*((uint16_t *)value_out) = (uint16_t)(*((uint8_t *)value_in));
return 0;
case 1:
*((uint8_t *)value_out) = (*((uint8_t *)value_in));
return 0;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
int _nativenet_set_option(netdev_t *dev, netdev_opt_t opt, void *value,
size_t value_len)
{
uint8_t set_value[sizeof(uint64_t)];
int res = 0;
if (dev->type != NETDEV_TYPE_BASE) {
return -ENODEV;
}
switch (opt) {
case NETDEV_OPT_CHANNEL:
if ((res = _type_pun_up(set_value, sizeof(uint8_t),
value, value_len)) == 0) {
_NATIVENET_DEV_MORE(dev)->_channel = *((uint8_t *)set_value);
}
break;
case NETDEV_OPT_ADDRESS:
if ((res = _type_pun_up(set_value, sizeof(radio_address_t),
value, value_len)) == 0) {
_NATIVENET_DEV_MORE(dev)->_radio_addr = *((radio_address_t *)set_value);
}
break;
case NETDEV_OPT_NID:
if ((res = _type_pun_up(set_value, sizeof(uint16_t),
value, value_len)) == 0) {
_NATIVENET_DEV_MORE(dev)->_pan_id = *((uint16_t *)set_value);
}
break;
case NETDEV_OPT_PROTO:
/* TODO: wouldn't this be awesome */
return -ENOTSUP;
default:
return -ENOTSUP;
}
return res;
}
int _nativenet_get_state(netdev_t *dev, netdev_state_t *state)
{
if (dev->type != NETDEV_TYPE_BASE) {
return -ENODEV;
}
if (_NATIVENET_DEV_MORE(dev)->_is_monitoring) {
*state = NETDEV_STATE_PROMISCUOUS_MODE;
}
else {
*state = NETDEV_STATE_RX_MODE;
}
return 0;
}
int _nativenet_set_state(netdev_t *dev, netdev_state_t state)
{
if (state != NETDEV_STATE_PROMISCUOUS_MODE && _NATIVENET_DEV_MORE(dev)->_is_monitoring) {
_NATIVENET_DEV_MORE(dev)->_is_monitoring = 0;
}
switch (state) {
case NETDEV_STATE_RX_MODE:
nativenet_switch_to_rx();
break;
case NETDEV_STATE_PROMISCUOUS_MODE:
_NATIVENET_DEV_MORE(dev)->_is_monitoring = 1;
break;
default:
return -ENOTSUP;
}
return 0;
}
void _nativenet_event(netdev_t *dev, uint32_t event_type)
{
(void)dev;
(void)event_type;
}
const netdev_driver_t nativenet_driver = {
_nativenet_init,
_nativenet_send_data,
_nativenet_add_rcv_data_cb,
_nativenet_rem_rcv_data_cb,
_nativenet_get_option,
_nativenet_set_option,
_nativenet_get_state,
_nativenet_set_state,
_nativenet_event,
};
_nativenet_netdev_more_t _nativenet_default_dev_more;
netdev_t nativenet_default_dev = {NETDEV_TYPE_BASE, &nativenet_driver,
&_nativenet_default_dev_more
};
#else
_nativenet_netdev_more_t _nativenet_default_dev_more;
netdev_t nativenet_default_dev = {NETDEV_TYPE_BASE, NULL,
&_nativenet_default_dev_more
};
#endif /* MODULE_NETDEV_BASE */
/** @} */

370
cpu/native/net/tap.c
View File

@ -1,370 +0,0 @@
/**
* tap.h implementation
*
* Copyright (C) 2013 Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
* @ingroup native_cpu
* @{
* @file
* @author Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <stdint.h>
#include <err.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <arpa/inet.h>
#include <inttypes.h>
#include <errno.h>
#ifdef __MACH__
#define _POSIX_C_SOURCE
#include <net/if.h>
#undef _POSIX_C_SOURCE
#include <ifaddrs.h>
#include <net/if_dl.h>
#elif defined(__FreeBSD__)
#include <sys/socket.h>
#include <net/if.h>
#include <ifaddrs.h>
#include <net/if_dl.h>
#else
#include <net/if.h>
#include <linux/if_tun.h>
#include <linux/if_ether.h>
#endif
#define ENABLE_DEBUG (0)
#include "debug.h"
#include "cpu.h"
#include "cpu_conf.h"
#include "tap.h"
#include "nativenet.h"
#include "nativenet_internal.h"
#include "native_internal.h"
#include "hwtimer.h"
#include "timex.h"
#define TAP_BUFFER_LENGTH (ETHER_MAX_LEN)
int _native_marshall_ethernet(uint8_t *framebuf, radio_packet_t *packet);
int _native_tap_fd = -1;
unsigned char _native_tap_mac[ETHER_ADDR_LEN];
#ifdef __MACH__
pid_t sigio_child_pid;
#endif
void _native_handle_tap_input(void)
{
int nread;
union eth_frame frame;
radio_packet_t p;
DEBUG("_native_handle_tap_input\n");
/* TODO: check whether this is an input or an output event
TODO: refactor this into general io-signal multiplexer */
nread = real_read(_native_tap_fd, &frame, sizeof(union eth_frame));
DEBUG("_native_handle_tap_input - read %d bytes\n", nread);
if (nread > 0) {
if (ntohs(frame.field.header.ether_type) == NATIVE_ETH_PROTO) {
nread = nread - ETHER_HDR_LEN;
if ((nread - 1) <= 0) {
DEBUG("_native_handle_tap_input: no payload\n");
}
else {
unsigned long t = hwtimer_now();
p.processing = 0;
p.src = ntohs(frame.field.payload.nn_header.src);
p.dst = ntohs(frame.field.payload.nn_header.dst);
p.rssi = 0;
p.lqi = 0;
p.toa.seconds = HWTIMER_TICKS_TO_US(t) / 1000000;
p.toa.microseconds = HWTIMER_TICKS_TO_US(t) % 1000000;
/* XXX: check overflow */
p.length = ntohs(frame.field.payload.nn_header.length);
p.data = frame.field.payload.data;
if (p.length > (nread - sizeof(struct nativenet_header))) {
warnx("_native_handle_tap_input: packet with malicious length field received, discarding");
}
else {
DEBUG("_native_handle_tap_input: received packet of length %" PRIu16 " for %" PRIu16 " from %"
PRIu16 "\n", p.length, p.dst, p.src);
_nativenet_handle_packet(&p);
}
}
}
else {
DEBUG("ignoring non-native frame\n");
}
/* work around lost signals */
fd_set rfds;
struct timeval t;
memset(&t, 0, sizeof(t));
FD_ZERO(&rfds);
FD_SET(_native_tap_fd, &rfds);
_native_in_syscall++; // no switching here
if (real_select(_native_tap_fd + 1, &rfds, NULL, NULL, &t) == 1) {
int sig = SIGIO;
extern int _sig_pipefd[2];
extern ssize_t (*real_write)(int fd, const void *buf, size_t count);
real_write(_sig_pipefd[1], &sig, sizeof(int));
_native_sigpend++;
DEBUG("_native_handle_tap_input: sigpend++\n");
}
else {
DEBUG("_native_handle_tap_input: no more pending tap data\n");
#ifdef __MACH__
kill(sigio_child_pid, SIGCONT);
#endif
}
_native_in_syscall--;
}
else if (nread == -1) {
if ((errno == EAGAIN) || (errno == EWOULDBLOCK)) {
//warn("read");
}
else {
err(EXIT_FAILURE, "_native_handle_tap_input: read");
}
}
else if (nread == 0) {
DEBUG("_native_handle_tap_input: ignoring null-event\n");
}
else {
errx(EXIT_FAILURE, "internal error _native_handle_tap_input");
}
}
#ifdef __MACH__
void sigio_child(void)
{
pid_t parent = _native_pid;
if ((sigio_child_pid = real_fork()) == -1) {
err(EXIT_FAILURE, "sigio_child: fork");
}
if (sigio_child_pid > 0) {
/* return in parent process */
return;
}
/* watch tap interface and signal parent process if data is
* available */
fd_set rfds;
while (1) {
FD_ZERO(&rfds);
FD_SET(_native_tap_fd, &rfds);
if (real_select(_native_tap_fd + 1, &rfds, NULL, NULL, NULL) == 1) {
kill(parent, SIGIO);
}
else {
kill(parent, SIGKILL);
err(EXIT_FAILURE, "osx_sigio_child: select");
}
pause();
}
}
#endif
int _native_marshall_ethernet(uint8_t *framebuf, radio_packet_t *packet)
{
int data_len;
union eth_frame *f;
unsigned char addr[ETHER_ADDR_LEN];
f = (union eth_frame *)framebuf;
addr[0] = addr[1] = addr[2] = addr[3] = addr[4] = addr[5] = 0xFF;
memcpy(f->field.header.ether_dhost, addr, ETHER_ADDR_LEN);
memcpy(f->field.header.ether_shost, _native_tap_mac, ETHER_ADDR_LEN);
f->field.header.ether_type = htons(NATIVE_ETH_PROTO);
/* XXX: check overflow */
memcpy(f->field.payload.data, packet->data, packet->length);
f->field.payload.nn_header.length = htons(packet->length);
f->field.payload.nn_header.dst = htons(packet->dst);
f->field.payload.nn_header.src = htons(packet->src);
data_len = packet->length + sizeof(struct nativenet_header);
/* Pad to minimum payload size.
* Linux does this on its own, but it doesn't hurt to do it here.
* As of now only tuntaposx needs this. */
if (data_len < ETHERMIN) {
DEBUG("padding data! (%d -> ", data_len);
data_len = ETHERMIN;
DEBUG("%d)\n", data_len);
}
return data_len + ETHER_HDR_LEN;
}
int8_t send_buf(radio_packet_t *packet)
{
uint8_t buf[TAP_BUFFER_LENGTH];
int nsent, to_send;
memset(buf, 0, sizeof(buf));
DEBUG("send_buf: Sending packet of length %" PRIu16 " from %" PRIu16 " to %" PRIu16 "\n",
packet->length, packet->src, packet->dst);
to_send = _native_marshall_ethernet(buf, packet);
DEBUG("send_buf: trying to send %d bytes\n", to_send);
if ((nsent = _native_write(_native_tap_fd, buf, to_send)) == -1) {
warn("write");
return -1;
}
return (nsent > INT8_MAX ? INT8_MAX : nsent);
}
int tap_init(char *name)
{
#ifdef __MACH__ /* OSX */
char clonedev[255] = "/dev/"; /* XXX bad size */
strncpy(clonedev + 5, name, 250);
#elif defined(__FreeBSD__)
char clonedev[255] = "/dev/"; /* XXX bad size */
strncpy(clonedev + 5, name, 250);
#else /* Linux */
struct ifreq ifr;
const char *clonedev = "/dev/net/tun";
#endif
/* implicitly create the tap interface */
if ((_native_tap_fd = real_open(clonedev , O_RDWR)) == -1) {
err(EXIT_FAILURE, "open(%s)", clonedev);
}
#if (defined(__MACH__) || defined(__FreeBSD__)) /* OSX/FreeBSD */
struct ifaddrs *iflist;
if (real_getifaddrs(&iflist) == 0) {
for (struct ifaddrs *cur = iflist; cur; cur = cur->ifa_next) {
if ((cur->ifa_addr->sa_family == AF_LINK) && (strcmp(cur->ifa_name, name) == 0) && cur->ifa_addr) {
struct sockaddr_dl *sdl = (struct sockaddr_dl *)cur->ifa_addr;
memcpy(_native_tap_mac, LLADDR(sdl), sdl->sdl_alen);
break;
}
}
real_freeifaddrs(iflist);
}
#else /* Linux */
memset(&ifr, 0, sizeof(ifr));
ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
strncpy(ifr.ifr_name, name, IFNAMSIZ);
if (real_ioctl(_native_tap_fd, TUNSETIFF, (void *)&ifr) == -1) {
_native_in_syscall++;
warn("ioctl TUNSETIFF");
warnx("probably the tap interface (%s) does not exist or is already in use", name);
real_exit(EXIT_FAILURE);
}
/* TODO: use strncpy */
strcpy(name, ifr.ifr_name);
/* get MAC address */
memset(&ifr, 0, sizeof(ifr));
snprintf(ifr.ifr_name, sizeof(ifr.ifr_name), "%s", name);
if (real_ioctl(_native_tap_fd, SIOCGIFHWADDR, &ifr) == -1) {
_native_in_syscall++;
warn("ioctl SIOCGIFHWADDR");
if (real_close(_native_tap_fd) == -1) {
warn("close");
}
real_exit(EXIT_FAILURE);
}
memcpy(_native_tap_mac, ifr.ifr_hwaddr.sa_data, ETHER_ADDR_LEN);
#endif
DEBUG("_native_tap_mac: %02x:%02x:%02x:%02x:%02x:%02x\n", _native_tap_mac[0], _native_tap_mac[1],
_native_tap_mac[2], _native_tap_mac[3], _native_tap_mac[4], _native_tap_mac[5]);
unsigned char *eui_64 = (unsigned char *)(&(_nativenet_default_dev_more._long_addr));
eui_64[0] = _native_tap_mac[0];
eui_64[1] = _native_tap_mac[1];
eui_64[2] = _native_tap_mac[2];
eui_64[3] = 0xff;
eui_64[4] = 0xfe;
eui_64[5] = _native_tap_mac[3];
eui_64[6] = _native_tap_mac[4];
eui_64[7] = _native_tap_mac[5];
/* configure signal handler for fds */
register_interrupt(SIGIO, _native_handle_tap_input);
#ifdef __MACH__
/* tuntap signalled IO is not working in OSX,
* check http://sourceforge.net/p/tuntaposx/bugs/17/ */
sigio_child();
#else
/* configure fds to send signals on io */
if (fcntl(_native_tap_fd, F_SETOWN, _native_pid) == -1) {
err(EXIT_FAILURE, "tap_init(): fcntl(F_SETOWN)");
}
/* set file access mode to non-blocking */
if (fcntl(_native_tap_fd, F_SETFL, O_NONBLOCK | O_ASYNC) == -1) {
err(EXIT_FAILURE, "tap_init(): fcntl(F_SETFL)");
}
#endif /* not OSX */
DEBUG("RIOT native tap initialized.\n");
return _native_tap_fd;
}
void tap_cleanup(void)
{
unregister_interrupt(SIGIO);
#ifdef __MACH__
kill(sigio_child_pid, SIGKILL);
#endif
if (_native_tap_fd == -1) {
return;
}
real_close(_native_tap_fd);
_native_tap_fd = -1;
}
/** @} */

11
cpu/native/startup.c
View File

@ -35,7 +35,6 @@
#include "board_internal.h"
#include "native_internal.h"
#include "tap.h"
int _native_null_in_pipe[2];
int _native_null_out_file;
@ -197,7 +196,7 @@ void usage_exit(void)
{
real_printf("usage: %s", _progname);
#if defined(MODULE_NATIVENET) || defined(MODULE_NG_NATIVENET)
#if defined(MODULE_NG_NATIVENET)
real_printf(" <tap interface>");
#endif
@ -257,7 +256,7 @@ __attribute__((constructor)) static void startup(int argc, char **argv)
int replay = 0;
#endif
#if defined(MODULE_NATIVENET) || defined(MODULE_NG_NATIVENET)
#if defined(MODULE_NG_NATIVENET)
if (
(argc < 2)
|| (
@ -368,13 +367,7 @@ __attribute__((constructor)) static void startup(int argc, char **argv)
native_cpu_init();
native_interrupt_init();
#ifdef MODULE_NATIVENET
tap_init(argv[1]);
#endif
#ifdef MODULE_NG_NATIVENET
# ifdef MODULE_NATIVENET
# error "Modules nativenet and ng_nativenet are mutually exclusive."
# endif
dev_eth_tap_setup(&dev_eth_tap, argv[1]);
#endif

5
cpu/samd21/include/cpu_conf.h
View File

@ -33,11 +33,6 @@ extern "C" {
#define CPU_FLASH_BASE FLASH_ADDR
/** @} */
/**
* @brief Buffer size to use by the transceiver
*/
#define TRANSCEIVER_BUFFER_SIZE (3)
/**
* @brief CPUID_ID_LEN length of cpuid in bytes
*/

2
cpu/stm32f1/include/cpu_conf.h
View File

@ -43,8 +43,6 @@ extern "C" {
*/
#define CPUID_ID_LEN (12)
#define TRANSCEIVER_BUFFER_SIZE (3)
/**
* @brief Configure the CPU's clock system
*

10
cpu/stm32f4/include/cpu_conf.h
View File

@ -45,16 +45,6 @@ extern "C" {
*/
#define CPUID_ID_LEN (12)
/**
* @name CC110X buffer size definitions for the stm32f4
* @{
*/
#ifdef MODULE_CC110X
#define TRANSCEIVER_BUFFER_SIZE (10)
#define RX_BUF_SIZE (10)
#endif
/** @} */
#ifdef __cplusplus
}
#endif

2
cpu/stm32l1/include/cpu_conf.h
View File

@ -41,8 +41,6 @@ extern "C" {
*/
#define CPUID_ID_LEN (12)
#define TRANSCEIVER_BUFFER_SIZE (3)
#ifdef __cplusplus
}
#endif

2
dist/Makefile vendored
View File

@ -36,8 +36,6 @@ QUIET ?= 1
#USEMODULE += uart0
#USEMODULE += posix
#USEMODULE += vtimer
#USEMODULE += defaulttransceiver
#USEMODULE += sixlowpan
#export INCLUDES += -Iapplication_include

12
doc/doxygen/src/mainpage.txt
View File

@ -180,18 +180,6 @@
* to your Makefile. Auto-init calls all module initialization functions with a
* `void` parameter just before the main thread gets executed.
*
* ####The transceiver module
*
* The transceiver module is an abstraction layer and multiplexer between the
* network stack and the radio driver. It runs in a single thread with the PID
* `transceiver_pid`. It provides an IPC interface that enables to configure and
* use available radio drivers, e.g. setting the radio channel or sending a packet.
* A thread may also register at the transceiver module, in order to get notified
* whenever a packet for a particular radio transceiver is received. The
* notification message contains a pointer to the packet struct. After processing
* the packet, the registered thread needs to decrease this struct's member
* `processing` which acts as a semaphore for the packet's memory buffer.
*
* \section info_sec Community
*
* Whether you are looking for help with writing an application for RIOT, want to learn more about it, or just stay in the loop you are invited to join the RIOT-users mailing list. For developers who want to participate and contribute to the kernel development or integrate new MCU and platform support the [RIOT-devel mailing list](http://lists.riot-os.org/mailman/listinfo/devel) is the right place.

6
drivers/Makefile
View File

@ -1,9 +1,3 @@
ifneq (,$(filter netdev_base,$(USEMODULE)))
DIRS += netdev/base
endif
ifneq (,$(filter netdev_802154,$(USEMODULE)))
DIRS += netdev/802154
endif
ifneq (,$(filter nrf24l01p,$(USEMODULE)))
DIRS += nrf24l01p
endif

15
drivers/Makefile.include
View File

@ -1,21 +1,6 @@
ifneq (,$(filter cc2420,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/cc2420/include
endif
ifneq (,$(filter cc110x,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/cc110x/include
endif
ifneq (,$(filter cc110x_legacy_csma,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/cc110x_legacy_csma/include
endif
ifneq (,$(filter cc110x_legacy,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/cc110x_legacy/include
endif
ifneq (,$(filter dht,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/dht/include
endif
ifneq (,$(filter at86rf231,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/at86rf231/include
endif
ifneq (,$(filter ng_at86rf2xx,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/ng_at86rf2xx/include
endif

1
drivers/at86rf231/Makefile
View File

@ -1 +0,0 @@
include $(RIOTBASE)/Makefile.base

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