diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/dsu.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/dsu.h index 6c04828294..ca004671a6 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/dsu.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/dsu.h @@ -104,6 +104,6 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for DSU peripheral ========== */ -#define DSU_CLK_AHB_ID 5 +#define DSU_CLK_AHB_ID 5 #endif /* _SAML21_DSU_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/eic_100.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/eic_100.h index 9d268616b9..e18ecb2cb5 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/eic_100.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/eic_100.h @@ -70,8 +70,8 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for EIC peripheral ========== */ -#define EIC_GCLK_ID 3 -#define EIC_NUMBER_OF_CONFIG_REGS 2 -#define EIC_NUMBER_OF_INTERRUPTS 16 +#define EIC_GCLK_ID 3 +#define EIC_NUMBER_OF_CONFIG_REGS 2 +#define EIC_NUMBER_OF_INTERRUPTS 16 #endif /* _SAML21_EIC_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/gclk_100.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/gclk_100.h index 7e1b30eba8..33a8f974e6 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/gclk_100.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/gclk_100.h @@ -144,20 +144,20 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 +#define GCLK_GENDIV_BITS 16 #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 #define GCLK_NUM 36 // Number of Generic Clock Users -#define GCLK_SOURCE_DFLL48M 7 -#define GCLK_SOURCE_FDPLL 8 -#define GCLK_SOURCE_GCLKGEN1 2 -#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_DFLL48M 7 +#define GCLK_SOURCE_FDPLL 8 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 -#define GCLK_SOURCE_OSC16M 6 -#define GCLK_SOURCE_OSC32K 4 -#define GCLK_SOURCE_XOSC 0 -#define GCLK_SOURCE_XOSC32K 5 +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC16M 6 +#define GCLK_SOURCE_OSC32K 4 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 5 #endif /* _SAML21_GCLK_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/mclk_100.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/mclk_100.h index 4102e5a02a..15afe1d831 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/mclk_100.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/mclk_100.h @@ -76,9 +76,9 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for MCLK peripheral ========== */ -#define MCLK_CTRLA_MCSEL_GCLK 1 -#define MCLK_CTRLA_MCSEL_OSC8M 0 -#define MCLK_MCLK_CLK_APB_NUM 5 +#define MCLK_CTRLA_MCSEL_GCLK 1 +#define MCLK_CTRLA_MCSEL_OSC8M 0 +#define MCLK_MCLK_CLK_APB_NUM 5 #define MCLK_SYSTEM_CLOCK 1000000 // System Clock Frequency at Reset #endif /* _SAML21_MCLK_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/nvmctrl_301.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/nvmctrl_301.h index fb07eaccd1..70e9d9d9ba 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/nvmctrl_301.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/nvmctrl_301.h @@ -75,20 +75,20 @@ #define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register #define NVMCTRL_CLK_AHB_ID_PICACHU 15 // Index of PICACHU AHB Clock #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_FLASH_SIZE 262144 #define NVMCTRL_GCLK_ID 35 // Index of Generic Clock for test #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 #define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF -#define NVMCTRL_RWWEE_PAGES 128 +#define NVMCTRL_RWWEE_PAGES 128 #define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area #endif /* _SAML21_NVMCTRL_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/osc32kctrl.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/osc32kctrl.h index f95ac52526..c14dff153e 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/osc32kctrl.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/osc32kctrl.h @@ -66,6 +66,6 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for OSC32KCTRL peripheral ========== */ -#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 #endif /* _SAML21_OSC32KCTRL_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/oscctrl.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/oscctrl.h index 6571b4e88c..a2241bd530 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/oscctrl.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/oscctrl.h @@ -82,14 +82,14 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for OSCCTRL peripheral ========== */ -#define OSCCTRL_DFLL48M_COARSE_MSB 5 -#define OSCCTRL_DFLL48M_FINE_MSB 9 +#define OSCCTRL_DFLL48M_COARSE_MSB 5 +#define OSCCTRL_DFLL48M_FINE_MSB 9 #define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 #define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL #define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define OSCCTRL_DFLL48M_VERSION 0x310 -#define OSCCTRL_FDPLL_VERSION 0x200 -#define OSCCTRL_OSC16M_VERSION 0x100 -#define OSCCTRL_XOSC_VERSION 0x120 +#define OSCCTRL_DFLL48M_VERSION 0x310 +#define OSCCTRL_FDPLL_VERSION 0x200 +#define OSCCTRL_OSC16M_VERSION 0x100 +#define OSCCTRL_XOSC_VERSION 0x120 #endif /* _SAML21_OSCCTRL_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/port.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/port.h index 34464f4b7f..795f79afb3 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/port.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/port.h @@ -106,14 +106,14 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for PORT peripheral ========== */ -#define PORT_BITS 84 +#define PORT_BITS 84 #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } #define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } #define PORT_DRVSTR 1 // DRVSTR supported? #define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } #define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000D0000 } #define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF, 0x00000000 } -#define PORT_EV_NUM 4 +#define PORT_EV_NUM 4 #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } #define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } #define PORT_ODRAIN 0 // ODRAIN supported? diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom0.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom0.h index 9b0793c144..3ef714ac18 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom0.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom0.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM0 peripheral ========== */ #define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger #define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger -#define SERCOM0_GCLK_ID_CORE 18 -#define SERCOM0_GCLK_ID_SLOW 17 -#define SERCOM0_INT_MSB 6 -#define SERCOM0_PMSB 3 +#define SERCOM0_GCLK_ID_CORE 18 +#define SERCOM0_GCLK_ID_SLOW 17 +#define SERCOM0_INT_MSB 6 +#define SERCOM0_PMSB 3 #endif /* _SAML21_SERCOM0_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom1.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom1.h index 978357ffb8..32c956ab31 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom1.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom1.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM1 peripheral ========== */ #define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger #define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger -#define SERCOM1_GCLK_ID_CORE 19 -#define SERCOM1_GCLK_ID_SLOW 17 -#define SERCOM1_INT_MSB 6 -#define SERCOM1_PMSB 3 +#define SERCOM1_GCLK_ID_CORE 19 +#define SERCOM1_GCLK_ID_SLOW 17 +#define SERCOM1_INT_MSB 6 +#define SERCOM1_PMSB 3 #endif /* _SAML21_SERCOM1_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom2.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom2.h index 084c7acd69..8ce1b4ec89 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom2.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom2.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM2 peripheral ========== */ #define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger #define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger -#define SERCOM2_GCLK_ID_CORE 20 -#define SERCOM2_GCLK_ID_SLOW 17 -#define SERCOM2_INT_MSB 6 -#define SERCOM2_PMSB 3 +#define SERCOM2_GCLK_ID_CORE 20 +#define SERCOM2_GCLK_ID_SLOW 17 +#define SERCOM2_INT_MSB 6 +#define SERCOM2_PMSB 3 #endif /* _SAML21_SERCOM2_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom3.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom3.h index 3a3ba77cc0..0ee15e81fd 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom3.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom3.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM3 peripheral ========== */ #define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger #define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger -#define SERCOM3_GCLK_ID_CORE 21 -#define SERCOM3_GCLK_ID_SLOW 17 -#define SERCOM3_INT_MSB 6 -#define SERCOM3_PMSB 3 +#define SERCOM3_GCLK_ID_CORE 21 +#define SERCOM3_GCLK_ID_SLOW 17 +#define SERCOM3_INT_MSB 6 +#define SERCOM3_PMSB 3 #endif /* _SAML21_SERCOM3_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom4.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom4.h index e7f85a6459..a1cb613416 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom4.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom4.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM4 peripheral ========== */ #define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger #define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger -#define SERCOM4_GCLK_ID_CORE 22 -#define SERCOM4_GCLK_ID_SLOW 17 -#define SERCOM4_INT_MSB 6 -#define SERCOM4_PMSB 3 +#define SERCOM4_GCLK_ID_CORE 22 +#define SERCOM4_GCLK_ID_SLOW 17 +#define SERCOM4_INT_MSB 6 +#define SERCOM4_PMSB 3 #endif /* _SAML21_SERCOM4_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom5.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom5.h index 37e58d3907..96ae0cc126 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom5.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/sercom5.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM5 peripheral ========== */ #define SERCOM5_DMAC_ID_RX // Index of DMA RX trigger #define SERCOM5_DMAC_ID_TX // Index of DMA TX trigger -#define SERCOM5_GCLK_ID_CORE 24 -#define SERCOM5_GCLK_ID_SLOW 23 -#define SERCOM5_INT_MSB 3 -#define SERCOM5_PMSB 3 +#define SERCOM5_GCLK_ID_CORE 24 +#define SERCOM5_GCLK_ID_SLOW 23 +#define SERCOM5_INT_MSB 3 +#define SERCOM5_PMSB 3 #endif /* _SAML21_SERCOM5_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/supc_100.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/supc_100.h index 34d846c324..4dfffdd9b4 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/supc_100.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/supc_100.h @@ -72,8 +72,8 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SUPC peripheral ========== */ -#define SUPC_BOD12_CALIB_MSB 5 -#define SUPC_BOD33_CALIB_MSB 5 +#define SUPC_BOD12_CALIB_MSB 5 +#define SUPC_BOD33_CALIB_MSB 5 #define SUPC_SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number #endif /* _SAML21_SUPC_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc0_100.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc0_100.h index 9aab6f3c19..d5194730d6 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc0_100.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc0_100.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC0 peripheral ========== */ -#define TC0_CC_NUM 2 +#define TC0_CC_NUM 2 #define TC0_DMAC_ID_MC_0 23 #define TC0_DMAC_ID_MC_1 24 #define TC0_DMAC_ID_MC_LSB 23 #define TC0_DMAC_ID_MC_MSB 24 #define TC0_DMAC_ID_MC_SIZE 2 #define TC0_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger -#define TC0_EXT 0 -#define TC0_GCLK_ID 27 -#define TC0_MASTER 1 -#define TC0_OW_NUM 2 +#define TC0_EXT 0 +#define TC0_GCLK_ID 27 +#define TC0_MASTER 1 +#define TC0_OW_NUM 2 #endif /* _SAML21_TC0_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc1_100.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc1_100.h index d00882d78b..9e1f515cb3 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc1_100.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc1_100.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC1 peripheral ========== */ -#define TC1_CC_NUM 2 +#define TC1_CC_NUM 2 #define TC1_DMAC_ID_MC_0 26 #define TC1_DMAC_ID_MC_1 27 #define TC1_DMAC_ID_MC_LSB 26 #define TC1_DMAC_ID_MC_MSB 27 #define TC1_DMAC_ID_MC_SIZE 2 #define TC1_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger -#define TC1_EXT 0 -#define TC1_GCLK_ID 27 -#define TC1_MASTER 0 -#define TC1_OW_NUM 2 +#define TC1_EXT 0 +#define TC1_GCLK_ID 27 +#define TC1_MASTER 0 +#define TC1_OW_NUM 2 #endif /* _SAML21_TC1_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc2_100.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc2_100.h index fbace2b044..967769c1a2 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc2_100.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc2_100.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC2 peripheral ========== */ -#define TC2_CC_NUM 2 +#define TC2_CC_NUM 2 #define TC2_DMAC_ID_MC_0 29 #define TC2_DMAC_ID_MC_1 30 #define TC2_DMAC_ID_MC_LSB 29 #define TC2_DMAC_ID_MC_MSB 30 #define TC2_DMAC_ID_MC_SIZE 2 #define TC2_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger -#define TC2_EXT 0 -#define TC2_GCLK_ID 28 -#define TC2_MASTER 1 -#define TC2_OW_NUM 2 +#define TC2_EXT 0 +#define TC2_GCLK_ID 28 +#define TC2_MASTER 1 +#define TC2_OW_NUM 2 #endif /* _SAML21_TC2_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc3_100.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc3_100.h index 587dc32ea6..e92d612659 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc3_100.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc3_100.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC3 peripheral ========== */ -#define TC3_CC_NUM 2 +#define TC3_CC_NUM 2 #define TC3_DMAC_ID_MC_0 32 #define TC3_DMAC_ID_MC_1 33 #define TC3_DMAC_ID_MC_LSB 32 #define TC3_DMAC_ID_MC_MSB 33 #define TC3_DMAC_ID_MC_SIZE 2 #define TC3_DMAC_ID_OVF 31 // Indexes of DMA Overflow trigger -#define TC3_EXT 0 -#define TC3_GCLK_ID 28 -#define TC3_MASTER 0 -#define TC3_OW_NUM 2 +#define TC3_EXT 0 +#define TC3_GCLK_ID 28 +#define TC3_MASTER 0 +#define TC3_OW_NUM 2 #endif /* _SAML21_TC3_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc4_100.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc4_100.h index 9c27c8a89e..c671f10c18 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/tc4_100.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/tc4_100.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC4 peripheral ========== */ -#define TC4_CC_NUM 2 +#define TC4_CC_NUM 2 #define TC4_DMAC_ID_MC_0 35 #define TC4_DMAC_ID_MC_1 36 #define TC4_DMAC_ID_MC_LSB 35 #define TC4_DMAC_ID_MC_MSB 36 #define TC4_DMAC_ID_MC_SIZE 2 #define TC4_DMAC_ID_OVF 34 // Indexes of DMA Overflow trigger -#define TC4_EXT 0 -#define TC4_GCLK_ID 29 -#define TC4_MASTER 0 -#define TC4_OW_NUM 2 +#define TC4_EXT 0 +#define TC4_GCLK_ID 29 +#define TC4_MASTER 0 +#define TC4_OW_NUM 2 #endif /* _SAML21_TC4_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc0_200.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc0_200.h index 646090feae..b34bcad72d 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc0_200.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc0_200.h @@ -124,7 +124,7 @@ #define TCC0_OTMX 1 // Output Matrix feature implemented #define TCC0_OW_NUM 8 // Number of Output Waveforms #define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 +#define TCC0_SIZE 24 #define TCC0_SWAP 1 // DTI outputs swap feature implemented #define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc1_200.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc1_200.h index dfc7d0e2a3..96f3bff712 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc1_200.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc1_200.h @@ -112,7 +112,7 @@ #define TCC1_OTMX 0 // Output Matrix feature implemented #define TCC1_OW_NUM 4 // Number of Output Waveforms #define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 +#define TCC1_SIZE 24 #define TCC1_SWAP 0 // DTI outputs swap feature implemented #define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc2_200.h b/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc2_200.h index a8d19c4084..02b56bba87 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc2_200.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/instance/tcc2_200.h @@ -108,7 +108,7 @@ #define TCC2_OTMX 0 // Output Matrix feature implemented #define TCC2_OW_NUM 2 // Number of Output Waveforms #define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 +#define TCC2_SIZE 16 #define TCC2_SWAP 0 // DTI outputs swap feature implemented #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/cpu/sam0_common/include/cmsis/saml21/include/saml21e18a.h b/cpu/sam0_common/include/cmsis/saml21/include/saml21e18a.h index 59c60892b3..7fbaaae68a 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/saml21e18a.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/saml21e18a.h @@ -226,7 +226,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/saml21g18a.h b/cpu/sam0_common/include/cmsis/saml21/include/saml21g18a.h index a62c35edf3..b5d7b4cfbb 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/saml21g18a.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/saml21g18a.h @@ -230,7 +230,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include/saml21j18a.h b/cpu/sam0_common/include/cmsis/saml21/include/saml21j18a.h index 961d135761..b847e6d117 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include/saml21j18a.h +++ b/cpu/sam0_common/include/cmsis/saml21/include/saml21j18a.h @@ -234,7 +234,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/dsu.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/dsu.h index 6c04828294..ca004671a6 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/dsu.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/dsu.h @@ -104,6 +104,6 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for DSU peripheral ========== */ -#define DSU_CLK_AHB_ID 5 +#define DSU_CLK_AHB_ID 5 #endif /* _SAML21_DSU_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/eic.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/eic.h index 0c0b27eaf5..23ff191a2b 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/eic.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/eic.h @@ -72,9 +72,9 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for EIC peripheral ========== */ -#define EIC_EXTINT_NUM 16 -#define EIC_GCLK_ID 3 -#define EIC_NUMBER_OF_CONFIG_REGS 2 -#define EIC_NUMBER_OF_INTERRUPTS 16 +#define EIC_EXTINT_NUM 16 +#define EIC_GCLK_ID 3 +#define EIC_NUMBER_OF_CONFIG_REGS 2 +#define EIC_NUMBER_OF_INTERRUPTS 16 #endif /* _SAML21_EIC_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/gclk.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/gclk.h index f66d4f9285..6e8efea09a 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/gclk.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/gclk.h @@ -144,22 +144,22 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 -#define GCLK_GEN_BITS 4 +#define GCLK_GENDIV_BITS 16 +#define GCLK_GEN_BITS 4 #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 #define GCLK_NUM 36 // Number of Generic Clock Users -#define GCLK_SOURCE_BITS 4 -#define GCLK_SOURCE_DFLL48M 7 -#define GCLK_SOURCE_FDPLL 8 -#define GCLK_SOURCE_GCLKGEN1 2 -#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_BITS 4 +#define GCLK_SOURCE_DFLL48M 7 +#define GCLK_SOURCE_FDPLL 8 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 -#define GCLK_SOURCE_OSC16M 6 -#define GCLK_SOURCE_OSC32K 4 -#define GCLK_SOURCE_XOSC 0 -#define GCLK_SOURCE_XOSC32K 5 +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC16M 6 +#define GCLK_SOURCE_OSC32K 4 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 5 #endif /* _SAML21_GCLK_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/mclk.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/mclk.h index 5909e0a63f..8a75815213 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/mclk.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/mclk.h @@ -76,9 +76,9 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for MCLK peripheral ========== */ -#define MCLK_CTRLA_MCSEL_GCLK 1 -#define MCLK_CTRLA_MCSEL_OSC8M 0 -#define MCLK_MCLK_CLK_APB_NUM 5 +#define MCLK_CTRLA_MCSEL_GCLK 1 +#define MCLK_CTRLA_MCSEL_OSC8M 0 +#define MCLK_MCLK_CLK_APB_NUM 5 #define MCLK_SYSTEM_CLOCK 4000000 // System Clock Frequency at Reset #endif /* _SAML21_MCLK_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/nvmctrl.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/nvmctrl.h index fb07eaccd1..70e9d9d9ba 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/nvmctrl.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/nvmctrl.h @@ -75,20 +75,20 @@ #define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register #define NVMCTRL_CLK_AHB_ID_PICACHU 15 // Index of PICACHU AHB Clock #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_FLASH_SIZE 262144 #define NVMCTRL_GCLK_ID 35 // Index of Generic Clock for test #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 #define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF -#define NVMCTRL_RWWEE_PAGES 128 +#define NVMCTRL_RWWEE_PAGES 128 #define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area #endif /* _SAML21_NVMCTRL_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/osc32kctrl.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/osc32kctrl.h index f95ac52526..c14dff153e 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/osc32kctrl.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/osc32kctrl.h @@ -66,6 +66,6 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for OSC32KCTRL peripheral ========== */ -#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 #endif /* _SAML21_OSC32KCTRL_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/oscctrl.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/oscctrl.h index 511156baa2..83ff8eef14 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/oscctrl.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/oscctrl.h @@ -82,14 +82,14 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for OSCCTRL peripheral ========== */ -#define OSCCTRL_DFLL48M_COARSE_MSB 5 -#define OSCCTRL_DFLL48M_FINE_MSB 9 +#define OSCCTRL_DFLL48M_COARSE_MSB 5 +#define OSCCTRL_DFLL48M_FINE_MSB 9 #define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 #define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL #define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define OSCCTRL_DFLL48M_VERSION 0x320 -#define OSCCTRL_FDPLL_VERSION 0x200 -#define OSCCTRL_OSC16M_VERSION 0x100 -#define OSCCTRL_XOSC_VERSION 0x120 +#define OSCCTRL_DFLL48M_VERSION 0x320 +#define OSCCTRL_FDPLL_VERSION 0x200 +#define OSCCTRL_OSC16M_VERSION 0x100 +#define OSCCTRL_XOSC_VERSION 0x120 #endif /* _SAML21_OSCCTRL_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/port.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/port.h index 34464f4b7f..795f79afb3 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/port.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/port.h @@ -106,14 +106,14 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for PORT peripheral ========== */ -#define PORT_BITS 84 +#define PORT_BITS 84 #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } #define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } #define PORT_DRVSTR 1 // DRVSTR supported? #define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } #define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000D0000 } #define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF, 0x00000000 } -#define PORT_EV_NUM 4 +#define PORT_EV_NUM 4 #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } #define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } #define PORT_ODRAIN 0 // ODRAIN supported? diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom0.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom0.h index 9b0793c144..3ef714ac18 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom0.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom0.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM0 peripheral ========== */ #define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger #define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger -#define SERCOM0_GCLK_ID_CORE 18 -#define SERCOM0_GCLK_ID_SLOW 17 -#define SERCOM0_INT_MSB 6 -#define SERCOM0_PMSB 3 +#define SERCOM0_GCLK_ID_CORE 18 +#define SERCOM0_GCLK_ID_SLOW 17 +#define SERCOM0_INT_MSB 6 +#define SERCOM0_PMSB 3 #endif /* _SAML21_SERCOM0_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom1.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom1.h index 978357ffb8..32c956ab31 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom1.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom1.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM1 peripheral ========== */ #define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger #define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger -#define SERCOM1_GCLK_ID_CORE 19 -#define SERCOM1_GCLK_ID_SLOW 17 -#define SERCOM1_INT_MSB 6 -#define SERCOM1_PMSB 3 +#define SERCOM1_GCLK_ID_CORE 19 +#define SERCOM1_GCLK_ID_SLOW 17 +#define SERCOM1_INT_MSB 6 +#define SERCOM1_PMSB 3 #endif /* _SAML21_SERCOM1_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom2.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom2.h index 084c7acd69..8ce1b4ec89 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom2.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom2.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM2 peripheral ========== */ #define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger #define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger -#define SERCOM2_GCLK_ID_CORE 20 -#define SERCOM2_GCLK_ID_SLOW 17 -#define SERCOM2_INT_MSB 6 -#define SERCOM2_PMSB 3 +#define SERCOM2_GCLK_ID_CORE 20 +#define SERCOM2_GCLK_ID_SLOW 17 +#define SERCOM2_INT_MSB 6 +#define SERCOM2_PMSB 3 #endif /* _SAML21_SERCOM2_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom3.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom3.h index 3a3ba77cc0..0ee15e81fd 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom3.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom3.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM3 peripheral ========== */ #define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger #define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger -#define SERCOM3_GCLK_ID_CORE 21 -#define SERCOM3_GCLK_ID_SLOW 17 -#define SERCOM3_INT_MSB 6 -#define SERCOM3_PMSB 3 +#define SERCOM3_GCLK_ID_CORE 21 +#define SERCOM3_GCLK_ID_SLOW 17 +#define SERCOM3_INT_MSB 6 +#define SERCOM3_PMSB 3 #endif /* _SAML21_SERCOM3_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom4.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom4.h index e7f85a6459..a1cb613416 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom4.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom4.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM4 peripheral ========== */ #define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger #define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger -#define SERCOM4_GCLK_ID_CORE 22 -#define SERCOM4_GCLK_ID_SLOW 17 -#define SERCOM4_INT_MSB 6 -#define SERCOM4_PMSB 3 +#define SERCOM4_GCLK_ID_CORE 22 +#define SERCOM4_GCLK_ID_SLOW 17 +#define SERCOM4_INT_MSB 6 +#define SERCOM4_PMSB 3 #endif /* _SAML21_SERCOM4_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom5.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom5.h index 37e58d3907..96ae0cc126 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom5.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/sercom5.h @@ -136,9 +136,9 @@ /* ========== Instance parameters for SERCOM5 peripheral ========== */ #define SERCOM5_DMAC_ID_RX // Index of DMA RX trigger #define SERCOM5_DMAC_ID_TX // Index of DMA TX trigger -#define SERCOM5_GCLK_ID_CORE 24 -#define SERCOM5_GCLK_ID_SLOW 23 -#define SERCOM5_INT_MSB 3 -#define SERCOM5_PMSB 3 +#define SERCOM5_GCLK_ID_CORE 24 +#define SERCOM5_GCLK_ID_SLOW 23 +#define SERCOM5_INT_MSB 3 +#define SERCOM5_PMSB 3 #endif /* _SAML21_SERCOM5_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/supc.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/supc.h index 34d846c324..4dfffdd9b4 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/supc.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/supc.h @@ -72,8 +72,8 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SUPC peripheral ========== */ -#define SUPC_BOD12_CALIB_MSB 5 -#define SUPC_BOD33_CALIB_MSB 5 +#define SUPC_BOD12_CALIB_MSB 5 +#define SUPC_BOD33_CALIB_MSB 5 #define SUPC_SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number #endif /* _SAML21_SUPC_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc0.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc0.h index 9aab6f3c19..d5194730d6 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc0.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc0.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC0 peripheral ========== */ -#define TC0_CC_NUM 2 +#define TC0_CC_NUM 2 #define TC0_DMAC_ID_MC_0 23 #define TC0_DMAC_ID_MC_1 24 #define TC0_DMAC_ID_MC_LSB 23 #define TC0_DMAC_ID_MC_MSB 24 #define TC0_DMAC_ID_MC_SIZE 2 #define TC0_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger -#define TC0_EXT 0 -#define TC0_GCLK_ID 27 -#define TC0_MASTER 1 -#define TC0_OW_NUM 2 +#define TC0_EXT 0 +#define TC0_GCLK_ID 27 +#define TC0_MASTER 1 +#define TC0_OW_NUM 2 #endif /* _SAML21_TC0_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc1.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc1.h index d00882d78b..9e1f515cb3 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc1.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc1.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC1 peripheral ========== */ -#define TC1_CC_NUM 2 +#define TC1_CC_NUM 2 #define TC1_DMAC_ID_MC_0 26 #define TC1_DMAC_ID_MC_1 27 #define TC1_DMAC_ID_MC_LSB 26 #define TC1_DMAC_ID_MC_MSB 27 #define TC1_DMAC_ID_MC_SIZE 2 #define TC1_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger -#define TC1_EXT 0 -#define TC1_GCLK_ID 27 -#define TC1_MASTER 0 -#define TC1_OW_NUM 2 +#define TC1_EXT 0 +#define TC1_GCLK_ID 27 +#define TC1_MASTER 0 +#define TC1_OW_NUM 2 #endif /* _SAML21_TC1_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc2.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc2.h index fbace2b044..967769c1a2 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc2.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc2.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC2 peripheral ========== */ -#define TC2_CC_NUM 2 +#define TC2_CC_NUM 2 #define TC2_DMAC_ID_MC_0 29 #define TC2_DMAC_ID_MC_1 30 #define TC2_DMAC_ID_MC_LSB 29 #define TC2_DMAC_ID_MC_MSB 30 #define TC2_DMAC_ID_MC_SIZE 2 #define TC2_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger -#define TC2_EXT 0 -#define TC2_GCLK_ID 28 -#define TC2_MASTER 1 -#define TC2_OW_NUM 2 +#define TC2_EXT 0 +#define TC2_GCLK_ID 28 +#define TC2_MASTER 1 +#define TC2_OW_NUM 2 #endif /* _SAML21_TC2_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc3.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc3.h index 587dc32ea6..e92d612659 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc3.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc3.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC3 peripheral ========== */ -#define TC3_CC_NUM 2 +#define TC3_CC_NUM 2 #define TC3_DMAC_ID_MC_0 32 #define TC3_DMAC_ID_MC_1 33 #define TC3_DMAC_ID_MC_LSB 32 #define TC3_DMAC_ID_MC_MSB 33 #define TC3_DMAC_ID_MC_SIZE 2 #define TC3_DMAC_ID_OVF 31 // Indexes of DMA Overflow trigger -#define TC3_EXT 0 -#define TC3_GCLK_ID 28 -#define TC3_MASTER 0 -#define TC3_OW_NUM 2 +#define TC3_EXT 0 +#define TC3_GCLK_ID 28 +#define TC3_MASTER 0 +#define TC3_OW_NUM 2 #endif /* _SAML21_TC3_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc4.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc4.h index 9c27c8a89e..c671f10c18 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc4.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tc4.h @@ -108,16 +108,16 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC4 peripheral ========== */ -#define TC4_CC_NUM 2 +#define TC4_CC_NUM 2 #define TC4_DMAC_ID_MC_0 35 #define TC4_DMAC_ID_MC_1 36 #define TC4_DMAC_ID_MC_LSB 35 #define TC4_DMAC_ID_MC_MSB 36 #define TC4_DMAC_ID_MC_SIZE 2 #define TC4_DMAC_ID_OVF 34 // Indexes of DMA Overflow trigger -#define TC4_EXT 0 -#define TC4_GCLK_ID 29 -#define TC4_MASTER 0 -#define TC4_OW_NUM 2 +#define TC4_EXT 0 +#define TC4_GCLK_ID 29 +#define TC4_MASTER 0 +#define TC4_OW_NUM 2 #endif /* _SAML21_TC4_INSTANCE_ */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc0.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc0.h index 3f4b810b20..9f78e1a875 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc0.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc0.h @@ -122,7 +122,7 @@ #define TCC0_OTMX 1 // Output Matrix feature implemented #define TCC0_OW_NUM 8 // Number of Output Waveforms #define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 +#define TCC0_SIZE 24 #define TCC0_SWAP 1 // DTI outputs swap feature implemented #define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc1.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc1.h index aabd5fbb3e..cb2d1519cf 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc1.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc1.h @@ -110,7 +110,7 @@ #define TCC1_OTMX 0 // Output Matrix feature implemented #define TCC1_OW_NUM 4 // Number of Output Waveforms #define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 +#define TCC1_SIZE 24 #define TCC1_SWAP 0 // DTI outputs swap feature implemented #define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc2.h b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc2.h index 3bd9db3133..70dc4294c9 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc2.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/instance/tcc2.h @@ -106,7 +106,7 @@ #define TCC2_OTMX 0 // Output Matrix feature implemented #define TCC2_OW_NUM 2 // Number of Output Waveforms #define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 +#define TCC2_SIZE 16 #define TCC2_SWAP 0 // DTI outputs swap feature implemented #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e15b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e15b.h index 7e057fbec7..569a65846f 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e15b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e15b.h @@ -230,7 +230,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e16b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e16b.h index 5b2093b617..49c16fa1a4 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e16b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e16b.h @@ -230,7 +230,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e17b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e17b.h index 4c204c2d0e..64489c65de 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e17b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e17b.h @@ -230,7 +230,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e18b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e18b.h index 17e3504275..6d3b3446e4 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e18b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21e18b.h @@ -230,7 +230,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g16b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g16b.h index 320ef4ba02..db767ab70c 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g16b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g16b.h @@ -230,7 +230,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g17b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g17b.h index 394f0d20e6..a9b0d4bb1b 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g17b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g17b.h @@ -230,7 +230,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g18b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g18b.h index 8083d0977f..ea203b5681 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g18b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21g18b.h @@ -230,7 +230,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j16b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j16b.h index 6d14deaf88..9ddc657f84 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j16b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j16b.h @@ -234,7 +234,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j17b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j17b.h index f953da4fa3..70e28bc1dd 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j17b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j17b.h @@ -234,7 +234,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j18b.h b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j18b.h index be6fd9960c..c6fd99980c 100644 --- a/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j18b.h +++ b/cpu/sam0_common/include/cmsis/saml21/include_b/saml21j18b.h @@ -234,7 +234,6 @@ void TRNG_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */