diff --git a/boards/nucleo144-f722/Makefile b/boards/nucleo144-f722/Makefile new file mode 100644 index 0000000000..f8fcbb53a0 --- /dev/null +++ b/boards/nucleo144-f722/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nucleo144-f722/Makefile.dep b/boards/nucleo144-f722/Makefile.dep new file mode 100644 index 0000000000..76e2dc17b4 --- /dev/null +++ b/boards/nucleo144-f722/Makefile.dep @@ -0,0 +1 @@ +include $(RIOTBOARD)/nucleo-common/Makefile.dep diff --git a/boards/nucleo144-f722/Makefile.features b/boards/nucleo144-f722/Makefile.features new file mode 100644 index 0000000000..f8982039ed --- /dev/null +++ b/boards/nucleo144-f722/Makefile.features @@ -0,0 +1,12 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_cpuid +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_hwrng +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# load the common Makefile.features for Nucleo144 boards +include $(RIOTBOARD)/nucleo144-common/Makefile.features + +# The board MPU family (used for grouping by the CI system) +FEATURES_MCU_GROUP = cortex_m7 diff --git a/boards/nucleo144-f722/Makefile.include b/boards/nucleo144-f722/Makefile.include new file mode 100644 index 0000000000..495043d0c3 --- /dev/null +++ b/boards/nucleo144-f722/Makefile.include @@ -0,0 +1,6 @@ +## the cpu to build for +export CPU = stm32f7 +export CPU_MODEL = stm32f722ze + +# load the common Makefile.include for Nucleo144 boards +include $(RIOTBOARD)/nucleo144-common/Makefile.include diff --git a/boards/nucleo144-f722/board.c b/boards/nucleo144-f722/board.c new file mode 100644 index 0000000000..ad2fc960a2 --- /dev/null +++ b/boards/nucleo144-f722/board.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo144-f722 + * @{ + * + * @file + * @brief Board specific implementations for the nucleo144-f722 board + * + * @author Alexandre Abadie + * + * @} + */ + +#include "board.h" +#include "periph/gpio.h" + +void board_init(void) +{ + /* initialize the CPU */ + cpu_init(); + + gpio_init(LED0_PIN, GPIO_OUT); + gpio_init(LED1_PIN, GPIO_OUT); + gpio_init(LED2_PIN, GPIO_OUT); +} diff --git a/boards/nucleo144-f722/dist/openocd.cfg b/boards/nucleo144-f722/dist/openocd.cfg new file mode 100644 index 0000000000..d028c19968 --- /dev/null +++ b/boards/nucleo144-f722/dist/openocd.cfg @@ -0,0 +1,5 @@ +source [find interface/stlink-v2-1.cfg] + +transport select hla_swd + +source [find target/stm32f7x.cfg] diff --git a/boards/nucleo144-f722/include/board.h b/boards/nucleo144-f722/include/board.h new file mode 100644 index 0000000000..a87d63c4e8 --- /dev/null +++ b/boards/nucleo144-f722/include/board.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup boards_nucleo144-f722 Nucleo144-F722 + * @ingroup boards + * @brief Board specific files for the nucleo144-f722 board + * @{ + * + * @file + * @brief Board specific definitions for the nucleo144-f722 board + * + * @author Alexandre Abadie + */ + +#ifndef BOARD_H +#define BOARD_H + +#include "board_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/nucleo144-f722/include/periph_conf.h b/boards/nucleo144-f722/include/periph_conf.h new file mode 100644 index 0000000000..e93c86811a --- /dev/null +++ b/boards/nucleo144-f722/include/periph_conf.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo144-f722 + * @{ + * + * @file + * @brief Peripheral MCU configuration for the nucleo144-f722 board + * + * @author Alexandre Abadie + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock system configuration + * @{ + */ +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#define CLOCK_HSE (8000000U) +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#define CLOCK_LSE (1) +/* give the target core clock (HCLK) frequency [in Hz], + * maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */ +#define CLOCK_CORECLOCK (216000000U) +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */ +#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */ +#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) +/** @} */ + +/** + * @name Timer configuration + * @{ + */ +static const timer_conf_t timer_config[] = { + { + .dev = TIM2, + .max = 0xffffffff, + .rcc_mask = RCC_APB1ENR_TIM2EN, + .bus = APB1, + .irqn = TIM2_IRQn + } +}; + +#define TIMER_0_ISR isr_tim2 + +#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) +/** @} */ + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = USART3, + .rcc_mask = RCC_APB1ENR_USART3EN, + .rx_pin = GPIO_PIN(PORT_D, 9), + .tx_pin = GPIO_PIN(PORT_D, 8), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART3_IRQn, +#ifdef UART_USE_DMA + .dma_stream = 6, + .dma_chan = 4 +#endif + }, + { + .dev = USART6, + .rcc_mask = RCC_APB2ENR_USART6EN, + .rx_pin = GPIO_PIN(PORT_G, 9), + .tx_pin = GPIO_PIN(PORT_G, 14), + .rx_af = GPIO_AF8, + .tx_af = GPIO_AF8, + .bus = APB2, + .irqn = USART6_IRQn, +#ifdef UART_USE_DMA + .dma_stream = 5, + .dma_chan = 4 +#endif + }, + { + .dev = USART2, + .rcc_mask = RCC_APB1ENR_USART2EN, + .rx_pin = GPIO_PIN(PORT_D, 6), + .tx_pin = GPIO_PIN(PORT_D, 5), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART2_IRQn, +#ifdef UART_USE_DMA + .dma_stream = 4, + .dma_chan = 4 +#endif + } +}; + +#define UART_0_ISR (isr_usart3) +#define UART_0_DMA_ISR (isr_dma1_stream6) +#define UART_1_ISR (isr_usart6) +#define UART_1_DMA_ISR (isr_dma1_stream5) +#define UART_2_ISR (isr_usart2) +#define UART_2_DMA_ISR (isr_dma1_stream4) + +#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) +/** @} */ + +/** + * @name ADC configuration + * @{ + */ +#define ADC_NUMOF (0) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */