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cpu/samd5x: rename GCLK defines

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Now that the GCLK defines are not always at a fixed frequency, rename
them to better reflect this.
This commit is contained in:
Benjamin Valentin 2020-06-16 17:41:59 +02:00 committed by Benjamin Valentin
parent 17304d390c
commit fba3aab2f3
2 changed files with 21 additions and 13 deletions
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18
cpu/samd5x/cpu.c
View File

@ -223,27 +223,27 @@ void sam0_gclk_enable(uint8_t id)
/* clocks 0 & 1 are always running */
switch (id) {
case SAM0_GCLK_8MHZ:
case SAM0_GCLK_TIMER:
/* 8 MHz clock used by xtimer */
if (USE_DPLL) {
gclk_connect(SAM0_GCLK_8MHZ,
gclk_connect(SAM0_GCLK_TIMER,
GCLK_SOURCE_DPLL0,
GCLK_GENCTRL_DIV(DPLL_DIV * CLOCK_CORECLOCK / MHZ(8)));
} else if (USE_DFLL) {
gclk_connect(SAM0_GCLK_8MHZ,
gclk_connect(SAM0_GCLK_TIMER,
GCLK_SOURCE_DFLL,
GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / MHZ(8)));
} else if (USE_XOSC) {
gclk_connect(SAM0_GCLK_8MHZ,
gclk_connect(SAM0_GCLK_TIMER,
GCLK_SOURCE_ACTIVE_XOSC,
GCLK_GENCTRL_DIV(SAM0_XOSC_FREQ_HZ / MHZ(4)));
}
break;
case SAM0_GCLK_48MHZ:
case SAM0_GCLK_PERIPH:
if (USE_DFLL) {
gclk_connect(SAM0_GCLK_48MHZ, GCLK_SOURCE_DFLL, 0);
gclk_connect(SAM0_GCLK_PERIPH, GCLK_SOURCE_DFLL, 0);
} else if (USE_XOSC) {
gclk_connect(SAM0_GCLK_48MHZ, GCLK_SOURCE_ACTIVE_XOSC, 0);
gclk_connect(SAM0_GCLK_PERIPH, GCLK_SOURCE_ACTIVE_XOSC, 0);
}
break;
@ -257,13 +257,13 @@ uint32_t sam0_gclk_freq(uint8_t id)
return CLOCK_CORECLOCK;
case SAM0_GCLK_32KHZ:
return 32768;
case SAM0_GCLK_8MHZ:
case SAM0_GCLK_TIMER:
if (USE_XOSC) {
return MHZ(4);
} else {
return MHZ(8);
}
case SAM0_GCLK_48MHZ:
case SAM0_GCLK_PERIPH:
if (USE_DFLL) {
return SAM0_DFLL_FREQ_HZ;
} else if (USE_XOSC) {

16
cpu/samd5x/include/periph_cpu.h
View File

@ -61,13 +61,21 @@ extern "C" {
* @{
*/
enum {
SAM0_GCLK_MAIN = 0, /**< 120 MHz main clock */
SAM0_GCLK_32KHZ, /**< 32 kHz clock */
SAM0_GCLK_8MHZ, /**< 8 MHz clock for xTimer */
SAM0_GCLK_48MHZ, /**< 48 MHz DFLL clock */
SAM0_GCLK_MAIN = 0, /**< 120 MHz main clock */
SAM0_GCLK_32KHZ, /**< 32 kHz clock */
SAM0_GCLK_TIMER, /**< 4-8 MHz clock for xTimer */
SAM0_GCLK_PERIPH, /**< 12-48 MHz (DFLL) clock */
};
/** @} */
/**
* @name GCLK compatibility definitions
* @{
*/
#define SAM0_GCLK_8MHZ SAM0_GCLK_TIMER
#define SAM0_GCLK_48MHZ SAM0_GCLK_PERIPH
/** @} */
/**
* @brief Override SPI hardware chip select macro
*