The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the same
Timer peripheral, yet each of them carries it's own copy of the Timer
driver.
This introduces a new timer driver that is common for all sam0 MCUs and
uses structs for configuration instead of defines.
If the .noinit section starts at the beginning of the RAM,
a bootloader that is unaware of it will clear it.
Instead, move it behind the .bss section, hoping that a bootloader
will always use less .bss memory than RIOT proper.
This commit adds the periph_uart_mode USEMODULE
It implements all functionality defined in the common uart driver
This means all parity modes, data bits, and stop bits
Make it possible to specify a section of RAM that is not touched by
the init routing so data can be kept across resets.
This should behave the same as on atmega & lpc2387.
gcc9 started realizing that _sram is basically an uint8_t[1] and thus
HARDFAULT_HANDLER_REQUIRED_STACK_SPACE cannot be added to it without
exceeding the one-sized array.
This commit casts _sram to (uintptr_t) where that happens.
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTT
driver.
Unify the drivers and move them to sam0_common.
This removes doing `filter-out periph_hwrng, $(FEATURES_PROVIDED)`
after processing `cpu/$(CPU)/Makefile.features`.
The current solution is a HACK as `CPU_MODEL` is currently not available
at that moment but will be in the near future.
It will allow always including `cpu/$(CPU)/Makefile.features` after
`boards/$(BOARD)/Makefile.features`.
It is a part of moving `CPU/CPU_MODEL` definitions to `Makefile.features`.
UART devices are now configured using static array in header files instead of static variables in implementation to be able to define UART_NUMOF using the size of the array instead of a variable.
SPI devices are now configured using static array in header files instead of static variables in implementation to be able to define SPI_NUMOF using the size of the array instead of a variable.
I2C devices are now configured using static array in header files instead of static variables in implementation to be able to define I2C_NUMOF using the size of the array instead of a variable.
DAC pins are now configured using static arrays in header files instead of static variables in implementation to be able to define DAC_NUMOF using the size of these arrays instead of a variable.
ADC pins are now configured using static arrays in header files instead of static variables in implementation to be able to define ADC_NUMOF using the size of these arrays instead of a variable.
Functions that are used by ADC and DAC peripherals are moved to a new submodule periph_adc_ctrl. This is necessary to compile separate submodules for ADC and DAC.
`top_of_stack` isn't aligned down to the previous 16 byte aligned address. Furthermore, `top_of_stack` as well as `XT_CP_SIZE` are used unaligned in `cpu/esp_common/vendor/xtensa/portasm.S` in the address computation for the coprocessor save area, .
Aligning pointer `p` down to the previous 16 byte aligned address results in a wrong address of the coprocessor save area during the initialization of the thread context. This leads to wrong values and wrong positions of these values in the coprocessor save area in inital thread context.
Since ESP8266 doesn't have a coprocessor, this bug affects only ESP32.
Functions marked with __atribute__((naked)) may only use basic inline assembly
and must not use any c code. The functions __enter_thread_mode() and
cpu_switch_context_exit() are using C code, so they must not be marked as
naked.
To prevent reordering of accesses to the interrupt control register when link
time optimization (LTO) is enabled, memory barriers are needed. Without LTO
calls to the external functions irq_disable(), irq_restore(), irq_enable() and
irq_is_in() have the same affect as compiler barriers, as the compiler is unable
to prove that reordering of memory accesses is safe (from a single-threaded
point of view). With LTO the compiler can easily prove that reordering is safe
from a single-threaded point of view: Thus, the compiler may move memory
accesses wrapped in irq_disable(), irq_restore() across those calls.
The memory barriers will have no effect on non-LTO builds.
Citing the doc of irq_enable():
@return Previous value of status register. [...]
On atmega however the new value of the status register is returned, not the one
prior to enabling interrupts.
