5 Commits

Author	SHA1	Message	Date
Tristan Bruns	532cdc64ff	cpu/fe310: implement SPI	2020-01-11 13:06:39 +01:00
Alexandre Abadie	97e1c7ba7e	cpu/fe310: reorganize files and includes	2020-01-10 16:41:33 +01:00
Alexandre Abadie	e5c64c739a	cpu/fe310: rework uart driver implem/config	2019-12-20 15:22:09 +01:00
smlng	740eafe93b	cpu/fe310: add missing PERIPH_TIMER_PROVIDES_SET	2018-09-07 22:15:13 +02:00
kenrabold	7d1d5e77d8	cpu/fe310: add RISC-V cpu FE310 ... New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools	2018-05-29 15:21:45 -07:00