3 Commits

Author	SHA1	Message	Date
Martine Lenders	769bf572a0	fe310: mark closing #endif for MODULE_PERIPH_GPIO_IRQ	2018-10-09 15:11:00 +02:00
Hauke Petersen	be94b99eda	cpu/fe310/gpio: use gpio_irq feature	2018-09-21 08:18:14 +02:00
kenrabold	7d1d5e77d8	cpu/fe310: add RISC-V cpu FE310 ... New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools	2018-05-29 15:21:45 -07:00